2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/errno.h>
19 #include <asm/mach/irq.h>
21 #include <mach/hardware.h>
22 #include <mach/common.h>
24 #include "irq-common.h"
27 *****************************************
29 *****************************************
32 #define TZIC_INTCNTL 0x0000 /* Control register */
33 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
34 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
35 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
36 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
37 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
38 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
39 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
40 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
41 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
42 #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
43 #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
44 #define TZIC_PND0 0x0D00 /* Pending Register 0 */
45 #define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
46 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
47 #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
48 #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
50 void __iomem
*tzic_base
; /* Used as irq controller base in entry-macro.S */
53 static int tzic_set_irq_fiq(unsigned int irq
, unsigned int type
)
55 unsigned int index
, mask
, value
;
58 if (unlikely(index
>= 4))
60 mask
= 1U << (irq
& 0x1F);
62 value
= __raw_readl(tzic_base
+ TZIC_INTSEC0(index
)) | mask
;
65 __raw_writel(value
, tzic_base
+ TZIC_INTSEC0(index
));
72 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
74 * @param irq interrupt source number
76 static void tzic_mask_irq(unsigned int irq
)
82 __raw_writel(1 << off
, tzic_base
+ TZIC_ENCLEAR0(index
));
86 * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
88 * @param irq interrupt source number
90 static void tzic_unmask_irq(unsigned int irq
)
96 __raw_writel(1 << off
, tzic_base
+ TZIC_ENSET0(index
));
99 static unsigned int wakeup_intr
[4];
102 * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
104 * @param irq interrupt source number
105 * @param enable enable as wake-up if equal to non-zero
106 * disble as wake-up if equal to zero
108 * @return This function returns 0 on success.
110 static int tzic_set_wake_irq(unsigned int irq
, unsigned int enable
)
112 unsigned int index
, off
;
121 wakeup_intr
[index
] |= (1 << off
);
123 wakeup_intr
[index
] &= ~(1 << off
);
128 static struct mxc_irq_chip mxc_tzic_chip
= {
131 .ack
= tzic_mask_irq
,
132 .mask
= tzic_mask_irq
,
133 .unmask
= tzic_unmask_irq
,
134 .set_wake
= tzic_set_wake_irq
,
137 .set_irq_fiq
= tzic_set_irq_fiq
,
142 * This function initializes the TZIC hardware and disables all the
143 * interrupts. It registers the interrupt enable and disable functions
144 * to the kernel for each interrupt source.
146 void __init
tzic_init_irq(void __iomem
*irqbase
)
151 /* put the TZIC into the reset value with
152 * all interrupts disabled
154 i
= __raw_readl(tzic_base
+ TZIC_INTCNTL
);
156 __raw_writel(0x80010001, tzic_base
+ TZIC_INTCNTL
);
157 __raw_writel(0x1f, tzic_base
+ TZIC_PRIOMASK
);
158 __raw_writel(0x02, tzic_base
+ TZIC_SYNCCTRL
);
160 for (i
= 0; i
< 4; i
++)
161 __raw_writel(0xFFFFFFFF, tzic_base
+ TZIC_INTSEC0(i
));
163 /* disable all interrupts */
164 for (i
= 0; i
< 4; i
++)
165 __raw_writel(0xFFFFFFFF, tzic_base
+ TZIC_ENCLEAR0(i
));
167 /* all IRQ no FIQ Warning :: No selection */
169 for (i
= 0; i
< MXC_INTERNAL_IRQS
; i
++) {
170 set_irq_chip(i
, &mxc_tzic_chip
.base
);
171 set_irq_handler(i
, handle_level_irq
);
172 set_irq_flags(i
, IRQF_VALID
);
180 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
184 * tzic_enable_wake() - enable wakeup interrupt
186 * @param is_idle 1 if called in idle loop (ENSET0 register);
187 * 0 to be used when called from low power entry
188 * @return 0 if successful; non-zero otherwise
190 int tzic_enable_wake(int is_idle
)
194 __raw_writel(1, tzic_base
+ TZIC_DSMINT
);
195 if (unlikely(__raw_readl(tzic_base
+ TZIC_DSMINT
) == 0))
198 for (i
= 0; i
< 4; i
++) {
199 v
= is_idle
? __raw_readl(tzic_base
+ TZIC_ENSET0(i
)) :
201 __raw_writel(v
, tzic_base
+ TZIC_WAKEUP0(i
));