arch/arm/plat-nomadik/timer.c

   1 /*
   2  *  linux/arch/arm/plat-nomadik/timer.c
   3  *
   4  * Copyright (C) 2008 STMicroelectronics
   5  * Copyright (C) 2010 Alessandro Rubini
   6  * Copyright (C) 2010 Linus Walleij for ST-Ericsson
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2, as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/clk.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/err.h>
  20 #include <linux/sched.h>
  21 #include <asm/mach/time.h>
  22 #include <asm/sched_clock.h>
  23
  24 /*
  25  * Guaranteed runtime conversion range in seconds for
  26  * the clocksource and clockevent.
  27  */
  28 #define MTU_MIN_RANGE 4
  29
  30 /*
  31  * The MTU device hosts four different counters, with 4 set of
  32  * registers. These are register names.
  33  */
  34
  35 #define MTU_IMSC        0x00    /* Interrupt mask set/clear */
  36 #define MTU_RIS         0x04    /* Raw interrupt status */
  37 #define MTU_MIS         0x08    /* Masked interrupt status */
  38 #define MTU_ICR         0x0C    /* Interrupt clear register */
  39
  40 /* per-timer registers take 0..3 as argument */
  41 #define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
  42 #define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
  43 #define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
  44 #define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
  45
  46 /* bits for the control register */
  47 #define MTU_CRn_ENA             0x80
  48 #define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
  49 #define MTU_CRn_PRESCALE_MASK   0x0c
  50 #define MTU_CRn_PRESCALE_1              0x00
  51 #define MTU_CRn_PRESCALE_16             0x04
  52 #define MTU_CRn_PRESCALE_256            0x08
  53 #define MTU_CRn_32BITS          0x02
  54 #define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
  55
  56 /* Other registers are usual amba/primecell registers, currently not used */
  57 #define MTU_ITCR        0xff0
  58 #define MTU_ITOP        0xff4
  59
  60 #define MTU_PERIPH_ID0  0xfe0
  61 #define MTU_PERIPH_ID1  0xfe4
  62 #define MTU_PERIPH_ID2  0xfe8
  63 #define MTU_PERIPH_ID3  0xfeC
  64
  65 #define MTU_PCELL0      0xff0
  66 #define MTU_PCELL1      0xff4
  67 #define MTU_PCELL2      0xff8
  68 #define MTU_PCELL3      0xffC
  69
  70 static bool clkevt_periodic;
  71 static u32 clk_prescale;
  72 static u32 nmdk_cycle;          /* write-once */
  73
  74 void __iomem *mtu_base; /* Assigned by machine code */
  75
  76 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
  77 /*
  78  * Override the global weak sched_clock symbol with this
  79  * local implementation which uses the clocksource to get some
  80  * better resolution when scheduling the kernel.
  81  */
  82 static DEFINE_CLOCK_DATA(cd);
  83
  84 unsigned long long notrace sched_clock(void)
  85 {
  86         u32 cyc;
  87
  88         if (unlikely(!mtu_base))
  89                 return 0;
  90
  91         cyc = -readl(mtu_base + MTU_VAL(0));
  92         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  93 }
  94
  95 static void notrace nomadik_update_sched_clock(void)
  96 {
  97         u32 cyc = -readl(mtu_base + MTU_VAL(0));
  98         update_sched_clock(&cd, cyc, (u32)~0);
  99 }
 100 #endif
 101
 102 /* Clockevent device: use one-shot mode */
 103 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
 104 {
 105         writel(1 << 1, mtu_base + MTU_IMSC);
 106         writel(evt, mtu_base + MTU_LR(1));
 107         /* Load highest value, enable device, enable interrupts */
 108         writel(MTU_CRn_ONESHOT | clk_prescale |
 109                MTU_CRn_32BITS | MTU_CRn_ENA,
 110                mtu_base + MTU_CR(1));
 111
 112         return 0;
 113 }
 114
 115 void nmdk_clkevt_reset(void)
 116 {
 117         if (clkevt_periodic) {
 118
 119                 /* Timer: configure load and background-load, and fire it up */
 120                 writel(nmdk_cycle, mtu_base + MTU_LR(1));
 121                 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
 122
 123                 writel(MTU_CRn_PERIODIC | clk_prescale |
 124                        MTU_CRn_32BITS | MTU_CRn_ENA,
 125                        mtu_base + MTU_CR(1));
 126                 writel(1 << 1, mtu_base + MTU_IMSC);
 127         } else {
 128                 /* Generate an interrupt to start the clockevent again */
 129                 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
 130         }
 131 }
 132
 133 static void nmdk_clkevt_mode(enum clock_event_mode mode,
 134                              struct clock_event_device *dev)
 135 {
 136
 137         switch (mode) {
 138         case CLOCK_EVT_MODE_PERIODIC:
 139                 clkevt_periodic = true;
 140                 nmdk_clkevt_reset();
 141                 break;
 142         case CLOCK_EVT_MODE_ONESHOT:
 143                 clkevt_periodic = false;
 144                 break;
 145         case CLOCK_EVT_MODE_SHUTDOWN:
 146         case CLOCK_EVT_MODE_UNUSED:
 147                 writel(0, mtu_base + MTU_IMSC);
 148                 /* disable timer */
 149                 writel(0, mtu_base + MTU_CR(1));
 150                 /* load some high default value */
 151                 writel(0xffffffff, mtu_base + MTU_LR(1));
 152                 break;
 153         case CLOCK_EVT_MODE_RESUME:
 154                 break;
 155         }
 156 }
 157
 158 static struct clock_event_device nmdk_clkevt = {
 159         .name           = "mtu_1",
 160         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 161         .rating         = 200,
 162         .set_mode       = nmdk_clkevt_mode,
 163         .set_next_event = nmdk_clkevt_next,
 164 };
 165
 166 /*
 167  * IRQ Handler for timer 1 of the MTU block.
 168  */
 169 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 170 {
 171         struct clock_event_device *evdev = dev_id;
 172
 173         writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
 174         evdev->event_handler(evdev);
 175         return IRQ_HANDLED;
 176 }
 177
 178 static struct irqaction nmdk_timer_irq = {
 179         .name           = "Nomadik Timer Tick",
 180         .flags          = IRQF_DISABLED | IRQF_TIMER,
 181         .handler        = nmdk_timer_interrupt,
 182         .dev_id         = &nmdk_clkevt,
 183 };
 184
 185 void nmdk_clksrc_reset(void)
 186 {
 187         /* Disable */
 188         writel(0, mtu_base + MTU_CR(0));
 189
 190         /* ClockSource: configure load and background-load, and fire it up */
 191         writel(nmdk_cycle, mtu_base + MTU_LR(0));
 192         writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
 193
 194         writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
 195                mtu_base + MTU_CR(0));
 196 }
 197
 198 void __init nmdk_timer_init(void)
 199 {
 200         unsigned long rate;
 201         struct clk *clk0;
 202
 203         clk0 = clk_get_sys("mtu0", NULL);
 204         BUG_ON(IS_ERR(clk0));
 205
 206         clk_enable(clk0);
 207
 208         /*
 209          * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
 210          * for ux500.
 211          * Use a divide-by-16 counter if the tick rate is more than 32MHz.
 212          * At 32 MHz, the timer (with 32 bit counter) can be programmed
 213          * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
 214          * with 16 gives too low timer resolution.
 215          */
 216         rate = clk_get_rate(clk0);
 217         if (rate > 32000000) {
 218                 rate /= 16;
 219                 clk_prescale = MTU_CRn_PRESCALE_16;
 220         } else {
 221                 clk_prescale = MTU_CRn_PRESCALE_1;
 222         }
 223
 224         nmdk_cycle = (rate + HZ/2) / HZ;
 225
 226
 227         /* Timer 0 is the free running clocksource */
 228         nmdk_clksrc_reset();
 229
 230         if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
 231                         rate, 200, 32, clocksource_mmio_readl_down))
 232                 pr_err("timer: failed to initialize clock source %s\n",
 233                        "mtu_0");
 234 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
 235         init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
 236 #endif
 237         /* Timer 1 is used for events */
 238
 239         clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
 240
 241         nmdk_clkevt.max_delta_ns =
 242                 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
 243         nmdk_clkevt.min_delta_ns =
 244                 clockevent_delta2ns(0x00000002, &nmdk_clkevt);
 245         nmdk_clkevt.cpumask     = cpumask_of(0);
 246
 247         /* Register irq and clockevents */
 248         setup_irq(IRQ_MTU0, &nmdk_timer_irq);
 249         clockevents_register_device(&nmdk_clkevt);
 250 }