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const: constify remaining dev_pm_ops
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE 0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE 0xfffbe400
49 #define OMAP1610_GPIO2_BASE 0xfffbec00
50 #define OMAP1610_GPIO3_BASE 0xfffbb400
51 #define OMAP1610_GPIO4_BASE 0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP7XX specific GPIO registers
72 */
73 #define OMAP7XX_GPIO1_BASE 0xfffbc000
74 #define OMAP7XX_GPIO2_BASE 0xfffbc800
75 #define OMAP7XX_GPIO3_BASE 0xfffbd000
76 #define OMAP7XX_GPIO4_BASE 0xfffbd800
77 #define OMAP7XX_GPIO5_BASE 0xfffbe000
78 #define OMAP7XX_GPIO6_BASE 0xfffbe800
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
85
86 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
87
88 /*
89 * omap24xx specific GPIO registers
90 */
91 #define OMAP242X_GPIO1_BASE 0x48018000
92 #define OMAP242X_GPIO2_BASE 0x4801a000
93 #define OMAP242X_GPIO3_BASE 0x4801c000
94 #define OMAP242X_GPIO4_BASE 0x4801e000
95
96 #define OMAP243X_GPIO1_BASE 0x4900C000
97 #define OMAP243X_GPIO2_BASE 0x4900E000
98 #define OMAP243X_GPIO3_BASE 0x49010000
99 #define OMAP243X_GPIO4_BASE 0x49012000
100 #define OMAP243X_GPIO5_BASE 0x480B6000
101
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
126
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
153 /*
154 * omap34xx specific GPIO registers
155 */
156
157 #define OMAP34XX_GPIO1_BASE 0x48310000
158 #define OMAP34XX_GPIO2_BASE 0x49050000
159 #define OMAP34XX_GPIO3_BASE 0x49052000
160 #define OMAP34XX_GPIO4_BASE 0x49054000
161 #define OMAP34XX_GPIO5_BASE 0x49056000
162 #define OMAP34XX_GPIO6_BASE 0x49058000
163
164 /*
165 * OMAP44XX specific GPIO registers
166 */
167 #define OMAP44XX_GPIO1_BASE 0x4a310000
168 #define OMAP44XX_GPIO2_BASE 0x48055000
169 #define OMAP44XX_GPIO3_BASE 0x48057000
170 #define OMAP44XX_GPIO4_BASE 0x48059000
171 #define OMAP44XX_GPIO5_BASE 0x4805B000
172 #define OMAP44XX_GPIO6_BASE 0x4805D000
173
174 struct gpio_bank {
175 unsigned long pbase;
176 void __iomem *base;
177 u16 irq;
178 u16 virtual_irq_start;
179 int method;
180 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
181 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
182 u32 suspend_wakeup;
183 u32 saved_wakeup;
184 #endif
185 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
186 defined(CONFIG_ARCH_OMAP4)
187 u32 non_wakeup_gpios;
188 u32 enabled_non_wakeup_gpios;
189
190 u32 saved_datain;
191 u32 saved_fallingdetect;
192 u32 saved_risingdetect;
193 #endif
194 u32 level_mask;
195 spinlock_t lock;
196 struct gpio_chip chip;
197 struct clk *dbck;
198 u32 mod_usage;
199 };
200
201 #define METHOD_MPUIO 0
202 #define METHOD_GPIO_1510 1
203 #define METHOD_GPIO_1610 2
204 #define METHOD_GPIO_7XX 3
205 #define METHOD_GPIO_24XX 5
206
207 #ifdef CONFIG_ARCH_OMAP16XX
208 static struct gpio_bank gpio_bank_1610[5] = {
209 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
210 METHOD_MPUIO },
211 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
212 METHOD_GPIO_1610 },
213 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
214 METHOD_GPIO_1610 },
215 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
216 METHOD_GPIO_1610 },
217 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
218 METHOD_GPIO_1610 },
219 };
220 #endif
221
222 #ifdef CONFIG_ARCH_OMAP15XX
223 static struct gpio_bank gpio_bank_1510[2] = {
224 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
225 METHOD_MPUIO },
226 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
227 METHOD_GPIO_1510 }
228 };
229 #endif
230
231 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
232 static struct gpio_bank gpio_bank_7xx[7] = {
233 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
234 METHOD_MPUIO },
235 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
236 METHOD_GPIO_7XX },
237 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
238 METHOD_GPIO_7XX },
239 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
240 METHOD_GPIO_7XX },
241 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
242 METHOD_GPIO_7XX },
243 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
244 METHOD_GPIO_7XX },
245 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
246 METHOD_GPIO_7XX },
247 };
248 #endif
249
250 #ifdef CONFIG_ARCH_OMAP24XX
251
252 static struct gpio_bank gpio_bank_242x[4] = {
253 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
254 METHOD_GPIO_24XX },
255 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
256 METHOD_GPIO_24XX },
257 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
258 METHOD_GPIO_24XX },
259 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
260 METHOD_GPIO_24XX },
261 };
262
263 static struct gpio_bank gpio_bank_243x[5] = {
264 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
265 METHOD_GPIO_24XX },
266 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
267 METHOD_GPIO_24XX },
268 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
269 METHOD_GPIO_24XX },
270 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
271 METHOD_GPIO_24XX },
272 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
273 METHOD_GPIO_24XX },
274 };
275
276 #endif
277
278 #ifdef CONFIG_ARCH_OMAP34XX
279 static struct gpio_bank gpio_bank_34xx[6] = {
280 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
281 METHOD_GPIO_24XX },
282 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
283 METHOD_GPIO_24XX },
284 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
285 METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
287 METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
289 METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
291 METHOD_GPIO_24XX },
292 };
293
294 struct omap3_gpio_regs {
295 u32 sysconfig;
296 u32 irqenable1;
297 u32 irqenable2;
298 u32 wake_en;
299 u32 ctrl;
300 u32 oe;
301 u32 leveldetect0;
302 u32 leveldetect1;
303 u32 risingdetect;
304 u32 fallingdetect;
305 u32 dataout;
306 u32 setwkuena;
307 u32 setdataout;
308 };
309
310 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
311 #endif
312
313 #ifdef CONFIG_ARCH_OMAP4
314 static struct gpio_bank gpio_bank_44xx[6] = {
315 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
316 METHOD_GPIO_24XX },
317 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
318 METHOD_GPIO_24XX },
319 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
320 METHOD_GPIO_24XX },
321 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
322 METHOD_GPIO_24XX },
323 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
324 METHOD_GPIO_24XX },
325 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
326 METHOD_GPIO_24XX },
327 };
328
329 #endif
330
331 static struct gpio_bank *gpio_bank;
332 static int gpio_bank_count;
333
334 static inline struct gpio_bank *get_gpio_bank(int gpio)
335 {
336 if (cpu_is_omap15xx()) {
337 if (OMAP_GPIO_IS_MPUIO(gpio))
338 return &gpio_bank[0];
339 return &gpio_bank[1];
340 }
341 if (cpu_is_omap16xx()) {
342 if (OMAP_GPIO_IS_MPUIO(gpio))
343 return &gpio_bank[0];
344 return &gpio_bank[1 + (gpio >> 4)];
345 }
346 if (cpu_is_omap7xx()) {
347 if (OMAP_GPIO_IS_MPUIO(gpio))
348 return &gpio_bank[0];
349 return &gpio_bank[1 + (gpio >> 5)];
350 }
351 if (cpu_is_omap24xx())
352 return &gpio_bank[gpio >> 5];
353 if (cpu_is_omap34xx() || cpu_is_omap44xx())
354 return &gpio_bank[gpio >> 5];
355 BUG();
356 return NULL;
357 }
358
359 static inline int get_gpio_index(int gpio)
360 {
361 if (cpu_is_omap7xx())
362 return gpio & 0x1f;
363 if (cpu_is_omap24xx())
364 return gpio & 0x1f;
365 if (cpu_is_omap34xx() || cpu_is_omap44xx())
366 return gpio & 0x1f;
367 return gpio & 0x0f;
368 }
369
370 static inline int gpio_valid(int gpio)
371 {
372 if (gpio < 0)
373 return -1;
374 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
375 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
376 return -1;
377 return 0;
378 }
379 if (cpu_is_omap15xx() && gpio < 16)
380 return 0;
381 if ((cpu_is_omap16xx()) && gpio < 64)
382 return 0;
383 if (cpu_is_omap7xx() && gpio < 192)
384 return 0;
385 if (cpu_is_omap24xx() && gpio < 128)
386 return 0;
387 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
388 return 0;
389 return -1;
390 }
391
392 static int check_gpio(int gpio)
393 {
394 if (unlikely(gpio_valid(gpio) < 0)) {
395 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
396 dump_stack();
397 return -1;
398 }
399 return 0;
400 }
401
402 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
403 {
404 void __iomem *reg = bank->base;
405 u32 l;
406
407 switch (bank->method) {
408 #ifdef CONFIG_ARCH_OMAP1
409 case METHOD_MPUIO:
410 reg += OMAP_MPUIO_IO_CNTL;
411 break;
412 #endif
413 #ifdef CONFIG_ARCH_OMAP15XX
414 case METHOD_GPIO_1510:
415 reg += OMAP1510_GPIO_DIR_CONTROL;
416 break;
417 #endif
418 #ifdef CONFIG_ARCH_OMAP16XX
419 case METHOD_GPIO_1610:
420 reg += OMAP1610_GPIO_DIRECTION;
421 break;
422 #endif
423 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
424 case METHOD_GPIO_7XX:
425 reg += OMAP7XX_GPIO_DIR_CONTROL;
426 break;
427 #endif
428 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
429 case METHOD_GPIO_24XX:
430 reg += OMAP24XX_GPIO_OE;
431 break;
432 #endif
433 #if defined(CONFIG_ARCH_OMAP4)
434 case METHOD_GPIO_24XX:
435 reg += OMAP4_GPIO_OE;
436 break;
437 #endif
438 default:
439 WARN_ON(1);
440 return;
441 }
442 l = __raw_readl(reg);
443 if (is_input)
444 l |= 1 << gpio;
445 else
446 l &= ~(1 << gpio);
447 __raw_writel(l, reg);
448 }
449
450 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
451 {
452 void __iomem *reg = bank->base;
453 u32 l = 0;
454
455 switch (bank->method) {
456 #ifdef CONFIG_ARCH_OMAP1
457 case METHOD_MPUIO:
458 reg += OMAP_MPUIO_OUTPUT;
459 l = __raw_readl(reg);
460 if (enable)
461 l |= 1 << gpio;
462 else
463 l &= ~(1 << gpio);
464 break;
465 #endif
466 #ifdef CONFIG_ARCH_OMAP15XX
467 case METHOD_GPIO_1510:
468 reg += OMAP1510_GPIO_DATA_OUTPUT;
469 l = __raw_readl(reg);
470 if (enable)
471 l |= 1 << gpio;
472 else
473 l &= ~(1 << gpio);
474 break;
475 #endif
476 #ifdef CONFIG_ARCH_OMAP16XX
477 case METHOD_GPIO_1610:
478 if (enable)
479 reg += OMAP1610_GPIO_SET_DATAOUT;
480 else
481 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
482 l = 1 << gpio;
483 break;
484 #endif
485 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
486 case METHOD_GPIO_7XX:
487 reg += OMAP7XX_GPIO_DATA_OUTPUT;
488 l = __raw_readl(reg);
489 if (enable)
490 l |= 1 << gpio;
491 else
492 l &= ~(1 << gpio);
493 break;
494 #endif
495 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
496 case METHOD_GPIO_24XX:
497 if (enable)
498 reg += OMAP24XX_GPIO_SETDATAOUT;
499 else
500 reg += OMAP24XX_GPIO_CLEARDATAOUT;
501 l = 1 << gpio;
502 break;
503 #endif
504 #ifdef CONFIG_ARCH_OMAP4
505 case METHOD_GPIO_24XX:
506 if (enable)
507 reg += OMAP4_GPIO_SETDATAOUT;
508 else
509 reg += OMAP4_GPIO_CLEARDATAOUT;
510 l = 1 << gpio;
511 break;
512 #endif
513 default:
514 WARN_ON(1);
515 return;
516 }
517 __raw_writel(l, reg);
518 }
519
520 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
521 {
522 void __iomem *reg;
523
524 if (check_gpio(gpio) < 0)
525 return -EINVAL;
526 reg = bank->base;
527 switch (bank->method) {
528 #ifdef CONFIG_ARCH_OMAP1
529 case METHOD_MPUIO:
530 reg += OMAP_MPUIO_INPUT_LATCH;
531 break;
532 #endif
533 #ifdef CONFIG_ARCH_OMAP15XX
534 case METHOD_GPIO_1510:
535 reg += OMAP1510_GPIO_DATA_INPUT;
536 break;
537 #endif
538 #ifdef CONFIG_ARCH_OMAP16XX
539 case METHOD_GPIO_1610:
540 reg += OMAP1610_GPIO_DATAIN;
541 break;
542 #endif
543 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
544 case METHOD_GPIO_7XX:
545 reg += OMAP7XX_GPIO_DATA_INPUT;
546 break;
547 #endif
548 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
549 case METHOD_GPIO_24XX:
550 reg += OMAP24XX_GPIO_DATAIN;
551 break;
552 #endif
553 #ifdef CONFIG_ARCH_OMAP4
554 case METHOD_GPIO_24XX:
555 reg += OMAP4_GPIO_DATAIN;
556 break;
557 #endif
558 default:
559 return -EINVAL;
560 }
561 return (__raw_readl(reg)
562 & (1 << get_gpio_index(gpio))) != 0;
563 }
564
565 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
566 {
567 void __iomem *reg;
568
569 if (check_gpio(gpio) < 0)
570 return -EINVAL;
571 reg = bank->base;
572
573 switch (bank->method) {
574 #ifdef CONFIG_ARCH_OMAP1
575 case METHOD_MPUIO:
576 reg += OMAP_MPUIO_OUTPUT;
577 break;
578 #endif
579 #ifdef CONFIG_ARCH_OMAP15XX
580 case METHOD_GPIO_1510:
581 reg += OMAP1510_GPIO_DATA_OUTPUT;
582 break;
583 #endif
584 #ifdef CONFIG_ARCH_OMAP16XX
585 case METHOD_GPIO_1610:
586 reg += OMAP1610_GPIO_DATAOUT;
587 break;
588 #endif
589 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
590 case METHOD_GPIO_7XX:
591 reg += OMAP7XX_GPIO_DATA_OUTPUT;
592 break;
593 #endif
594 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
595 defined(CONFIG_ARCH_OMAP4)
596 case METHOD_GPIO_24XX:
597 reg += OMAP24XX_GPIO_DATAOUT;
598 break;
599 #endif
600 default:
601 return -EINVAL;
602 }
603
604 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
605 }
606
607 #define MOD_REG_BIT(reg, bit_mask, set) \
608 do { \
609 int l = __raw_readl(base + reg); \
610 if (set) l |= bit_mask; \
611 else l &= ~bit_mask; \
612 __raw_writel(l, base + reg); \
613 } while(0)
614
615 void omap_set_gpio_debounce(int gpio, int enable)
616 {
617 struct gpio_bank *bank;
618 void __iomem *reg;
619 unsigned long flags;
620 u32 val, l = 1 << get_gpio_index(gpio);
621
622 if (cpu_class_is_omap1())
623 return;
624
625 bank = get_gpio_bank(gpio);
626 reg = bank->base;
627 #ifdef CONFIG_ARCH_OMAP4
628 reg += OMAP4_GPIO_DEBOUNCENABLE;
629 #else
630 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
631 #endif
632 if (!(bank->mod_usage & l)) {
633 printk(KERN_ERR "GPIO %d not requested\n", gpio);
634 return;
635 }
636
637 spin_lock_irqsave(&bank->lock, flags);
638 val = __raw_readl(reg);
639
640 if (enable && !(val & l))
641 val |= l;
642 else if (!enable && (val & l))
643 val &= ~l;
644 else
645 goto done;
646
647 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
648 if (enable)
649 clk_enable(bank->dbck);
650 else
651 clk_disable(bank->dbck);
652 }
653
654 __raw_writel(val, reg);
655 done:
656 spin_unlock_irqrestore(&bank->lock, flags);
657 }
658 EXPORT_SYMBOL(omap_set_gpio_debounce);
659
660 void omap_set_gpio_debounce_time(int gpio, int enc_time)
661 {
662 struct gpio_bank *bank;
663 void __iomem *reg;
664
665 if (cpu_class_is_omap1())
666 return;
667
668 bank = get_gpio_bank(gpio);
669 reg = bank->base;
670
671 if (!bank->mod_usage) {
672 printk(KERN_ERR "GPIO not requested\n");
673 return;
674 }
675
676 enc_time &= 0xff;
677 #ifdef CONFIG_ARCH_OMAP4
678 reg += OMAP4_GPIO_DEBOUNCINGTIME;
679 #else
680 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
681 #endif
682 __raw_writel(enc_time, reg);
683 }
684 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
685
686 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
687 defined(CONFIG_ARCH_OMAP4)
688 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
689 int trigger)
690 {
691 void __iomem *base = bank->base;
692 u32 gpio_bit = 1 << gpio;
693 u32 val;
694
695 if (cpu_is_omap44xx()) {
696 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
697 trigger & IRQ_TYPE_LEVEL_LOW);
698 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
699 trigger & IRQ_TYPE_LEVEL_HIGH);
700 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
701 trigger & IRQ_TYPE_EDGE_RISING);
702 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
703 trigger & IRQ_TYPE_EDGE_FALLING);
704 } else {
705 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
706 trigger & IRQ_TYPE_LEVEL_LOW);
707 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
708 trigger & IRQ_TYPE_LEVEL_HIGH);
709 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
710 trigger & IRQ_TYPE_EDGE_RISING);
711 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
712 trigger & IRQ_TYPE_EDGE_FALLING);
713 }
714 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
715 if (cpu_is_omap44xx()) {
716 if (trigger != 0)
717 __raw_writel(1 << gpio, bank->base+
718 OMAP4_GPIO_IRQWAKEN0);
719 else {
720 val = __raw_readl(bank->base +
721 OMAP4_GPIO_IRQWAKEN0);
722 __raw_writel(val & (~(1 << gpio)), bank->base +
723 OMAP4_GPIO_IRQWAKEN0);
724 }
725 } else {
726 if (trigger != 0)
727 __raw_writel(1 << gpio, bank->base
728 + OMAP24XX_GPIO_SETWKUENA);
729 else
730 __raw_writel(1 << gpio, bank->base
731 + OMAP24XX_GPIO_CLEARWKUENA);
732 }
733 } else {
734 if (trigger != 0)
735 bank->enabled_non_wakeup_gpios |= gpio_bit;
736 else
737 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
738 }
739
740 if (cpu_is_omap44xx()) {
741 bank->level_mask =
742 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
743 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
744 } else {
745 bank->level_mask =
746 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
747 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
748 }
749 }
750 #endif
751
752 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
753 {
754 void __iomem *reg = bank->base;
755 u32 l = 0;
756
757 switch (bank->method) {
758 #ifdef CONFIG_ARCH_OMAP1
759 case METHOD_MPUIO:
760 reg += OMAP_MPUIO_GPIO_INT_EDGE;
761 l = __raw_readl(reg);
762 if (trigger & IRQ_TYPE_EDGE_RISING)
763 l |= 1 << gpio;
764 else if (trigger & IRQ_TYPE_EDGE_FALLING)
765 l &= ~(1 << gpio);
766 else
767 goto bad;
768 break;
769 #endif
770 #ifdef CONFIG_ARCH_OMAP15XX
771 case METHOD_GPIO_1510:
772 reg += OMAP1510_GPIO_INT_CONTROL;
773 l = __raw_readl(reg);
774 if (trigger & IRQ_TYPE_EDGE_RISING)
775 l |= 1 << gpio;
776 else if (trigger & IRQ_TYPE_EDGE_FALLING)
777 l &= ~(1 << gpio);
778 else
779 goto bad;
780 break;
781 #endif
782 #ifdef CONFIG_ARCH_OMAP16XX
783 case METHOD_GPIO_1610:
784 if (gpio & 0x08)
785 reg += OMAP1610_GPIO_EDGE_CTRL2;
786 else
787 reg += OMAP1610_GPIO_EDGE_CTRL1;
788 gpio &= 0x07;
789 l = __raw_readl(reg);
790 l &= ~(3 << (gpio << 1));
791 if (trigger & IRQ_TYPE_EDGE_RISING)
792 l |= 2 << (gpio << 1);
793 if (trigger & IRQ_TYPE_EDGE_FALLING)
794 l |= 1 << (gpio << 1);
795 if (trigger)
796 /* Enable wake-up during idle for dynamic tick */
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
798 else
799 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
800 break;
801 #endif
802 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
803 case METHOD_GPIO_7XX:
804 reg += OMAP7XX_GPIO_INT_CONTROL;
805 l = __raw_readl(reg);
806 if (trigger & IRQ_TYPE_EDGE_RISING)
807 l |= 1 << gpio;
808 else if (trigger & IRQ_TYPE_EDGE_FALLING)
809 l &= ~(1 << gpio);
810 else
811 goto bad;
812 break;
813 #endif
814 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
815 defined(CONFIG_ARCH_OMAP4)
816 case METHOD_GPIO_24XX:
817 set_24xx_gpio_triggering(bank, gpio, trigger);
818 break;
819 #endif
820 default:
821 goto bad;
822 }
823 __raw_writel(l, reg);
824 return 0;
825 bad:
826 return -EINVAL;
827 }
828
829 static int gpio_irq_type(unsigned irq, unsigned type)
830 {
831 struct gpio_bank *bank;
832 unsigned gpio;
833 int retval;
834 unsigned long flags;
835
836 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
837 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
838 else
839 gpio = irq - IH_GPIO_BASE;
840
841 if (check_gpio(gpio) < 0)
842 return -EINVAL;
843
844 if (type & ~IRQ_TYPE_SENSE_MASK)
845 return -EINVAL;
846
847 /* OMAP1 allows only only edge triggering */
848 if (!cpu_class_is_omap2()
849 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
850 return -EINVAL;
851
852 bank = get_irq_chip_data(irq);
853 spin_lock_irqsave(&bank->lock, flags);
854 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
855 if (retval == 0) {
856 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
857 irq_desc[irq].status |= type;
858 }
859 spin_unlock_irqrestore(&bank->lock, flags);
860
861 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
862 __set_irq_handler_unlocked(irq, handle_level_irq);
863 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
864 __set_irq_handler_unlocked(irq, handle_edge_irq);
865
866 return retval;
867 }
868
869 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
870 {
871 void __iomem *reg = bank->base;
872
873 switch (bank->method) {
874 #ifdef CONFIG_ARCH_OMAP1
875 case METHOD_MPUIO:
876 /* MPUIO irqstatus is reset by reading the status register,
877 * so do nothing here */
878 return;
879 #endif
880 #ifdef CONFIG_ARCH_OMAP15XX
881 case METHOD_GPIO_1510:
882 reg += OMAP1510_GPIO_INT_STATUS;
883 break;
884 #endif
885 #ifdef CONFIG_ARCH_OMAP16XX
886 case METHOD_GPIO_1610:
887 reg += OMAP1610_GPIO_IRQSTATUS1;
888 break;
889 #endif
890 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
891 case METHOD_GPIO_7XX:
892 reg += OMAP7XX_GPIO_INT_STATUS;
893 break;
894 #endif
895 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
896 case METHOD_GPIO_24XX:
897 reg += OMAP24XX_GPIO_IRQSTATUS1;
898 break;
899 #endif
900 #if defined(CONFIG_ARCH_OMAP4)
901 case METHOD_GPIO_24XX:
902 reg += OMAP4_GPIO_IRQSTATUS0;
903 break;
904 #endif
905 default:
906 WARN_ON(1);
907 return;
908 }
909 __raw_writel(gpio_mask, reg);
910
911 /* Workaround for clearing DSP GPIO interrupts to allow retention */
912 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
913 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
914 #endif
915 #if defined(CONFIG_ARCH_OMAP4)
916 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
917 #endif
918 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
919 __raw_writel(gpio_mask, reg);
920
921 /* Flush posted write for the irq status to avoid spurious interrupts */
922 __raw_readl(reg);
923 }
924 }
925
926 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
927 {
928 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
929 }
930
931 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
932 {
933 void __iomem *reg = bank->base;
934 int inv = 0;
935 u32 l;
936 u32 mask;
937
938 switch (bank->method) {
939 #ifdef CONFIG_ARCH_OMAP1
940 case METHOD_MPUIO:
941 reg += OMAP_MPUIO_GPIO_MASKIT;
942 mask = 0xffff;
943 inv = 1;
944 break;
945 #endif
946 #ifdef CONFIG_ARCH_OMAP15XX
947 case METHOD_GPIO_1510:
948 reg += OMAP1510_GPIO_INT_MASK;
949 mask = 0xffff;
950 inv = 1;
951 break;
952 #endif
953 #ifdef CONFIG_ARCH_OMAP16XX
954 case METHOD_GPIO_1610:
955 reg += OMAP1610_GPIO_IRQENABLE1;
956 mask = 0xffff;
957 break;
958 #endif
959 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
960 case METHOD_GPIO_7XX:
961 reg += OMAP7XX_GPIO_INT_MASK;
962 mask = 0xffffffff;
963 inv = 1;
964 break;
965 #endif
966 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
967 case METHOD_GPIO_24XX:
968 reg += OMAP24XX_GPIO_IRQENABLE1;
969 mask = 0xffffffff;
970 break;
971 #endif
972 #if defined(CONFIG_ARCH_OMAP4)
973 case METHOD_GPIO_24XX:
974 reg += OMAP4_GPIO_IRQSTATUSSET0;
975 mask = 0xffffffff;
976 break;
977 #endif
978 default:
979 WARN_ON(1);
980 return 0;
981 }
982
983 l = __raw_readl(reg);
984 if (inv)
985 l = ~l;
986 l &= mask;
987 return l;
988 }
989
990 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
991 {
992 void __iomem *reg = bank->base;
993 u32 l;
994
995 switch (bank->method) {
996 #ifdef CONFIG_ARCH_OMAP1
997 case METHOD_MPUIO:
998 reg += OMAP_MPUIO_GPIO_MASKIT;
999 l = __raw_readl(reg);
1000 if (enable)
1001 l &= ~(gpio_mask);
1002 else
1003 l |= gpio_mask;
1004 break;
1005 #endif
1006 #ifdef CONFIG_ARCH_OMAP15XX
1007 case METHOD_GPIO_1510:
1008 reg += OMAP1510_GPIO_INT_MASK;
1009 l = __raw_readl(reg);
1010 if (enable)
1011 l &= ~(gpio_mask);
1012 else
1013 l |= gpio_mask;
1014 break;
1015 #endif
1016 #ifdef CONFIG_ARCH_OMAP16XX
1017 case METHOD_GPIO_1610:
1018 if (enable)
1019 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1020 else
1021 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1022 l = gpio_mask;
1023 break;
1024 #endif
1025 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1026 case METHOD_GPIO_7XX:
1027 reg += OMAP7XX_GPIO_INT_MASK;
1028 l = __raw_readl(reg);
1029 if (enable)
1030 l &= ~(gpio_mask);
1031 else
1032 l |= gpio_mask;
1033 break;
1034 #endif
1035 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1036 case METHOD_GPIO_24XX:
1037 if (enable)
1038 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1039 else
1040 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1041 l = gpio_mask;
1042 break;
1043 #endif
1044 #ifdef CONFIG_ARCH_OMAP4
1045 case METHOD_GPIO_24XX:
1046 if (enable)
1047 reg += OMAP4_GPIO_IRQSTATUSSET0;
1048 else
1049 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1050 l = gpio_mask;
1051 break;
1052 #endif
1053 default:
1054 WARN_ON(1);
1055 return;
1056 }
1057 __raw_writel(l, reg);
1058 }
1059
1060 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1061 {
1062 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1063 }
1064
1065 /*
1066 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1067 * 1510 does not seem to have a wake-up register. If JTAG is connected
1068 * to the target, system will wake up always on GPIO events. While
1069 * system is running all registered GPIO interrupts need to have wake-up
1070 * enabled. When system is suspended, only selected GPIO interrupts need
1071 * to have wake-up enabled.
1072 */
1073 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1074 {
1075 unsigned long flags;
1076
1077 switch (bank->method) {
1078 #ifdef CONFIG_ARCH_OMAP16XX
1079 case METHOD_MPUIO:
1080 case METHOD_GPIO_1610:
1081 spin_lock_irqsave(&bank->lock, flags);
1082 if (enable)
1083 bank->suspend_wakeup |= (1 << gpio);
1084 else
1085 bank->suspend_wakeup &= ~(1 << gpio);
1086 spin_unlock_irqrestore(&bank->lock, flags);
1087 return 0;
1088 #endif
1089 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1090 defined(CONFIG_ARCH_OMAP4)
1091 case METHOD_GPIO_24XX:
1092 if (bank->non_wakeup_gpios & (1 << gpio)) {
1093 printk(KERN_ERR "Unable to modify wakeup on "
1094 "non-wakeup GPIO%d\n",
1095 (bank - gpio_bank) * 32 + gpio);
1096 return -EINVAL;
1097 }
1098 spin_lock_irqsave(&bank->lock, flags);
1099 if (enable)
1100 bank->suspend_wakeup |= (1 << gpio);
1101 else
1102 bank->suspend_wakeup &= ~(1 << gpio);
1103 spin_unlock_irqrestore(&bank->lock, flags);
1104 return 0;
1105 #endif
1106 default:
1107 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1108 bank->method);
1109 return -EINVAL;
1110 }
1111 }
1112
1113 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1114 {
1115 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1116 _set_gpio_irqenable(bank, gpio, 0);
1117 _clear_gpio_irqstatus(bank, gpio);
1118 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1119 }
1120
1121 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1122 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1123 {
1124 unsigned int gpio = irq - IH_GPIO_BASE;
1125 struct gpio_bank *bank;
1126 int retval;
1127
1128 if (check_gpio(gpio) < 0)
1129 return -ENODEV;
1130 bank = get_irq_chip_data(irq);
1131 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1132
1133 return retval;
1134 }
1135
1136 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1137 {
1138 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1139 unsigned long flags;
1140
1141 spin_lock_irqsave(&bank->lock, flags);
1142
1143 /* Set trigger to none. You need to enable the desired trigger with
1144 * request_irq() or set_irq_type().
1145 */
1146 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1147
1148 #ifdef CONFIG_ARCH_OMAP15XX
1149 if (bank->method == METHOD_GPIO_1510) {
1150 void __iomem *reg;
1151
1152 /* Claim the pin for MPU */
1153 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1154 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1155 }
1156 #endif
1157 if (!cpu_class_is_omap1()) {
1158 if (!bank->mod_usage) {
1159 u32 ctrl;
1160 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1161 ctrl &= 0xFFFFFFFE;
1162 /* Module is enabled, clocks are not gated */
1163 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1164 }
1165 bank->mod_usage |= 1 << offset;
1166 }
1167 spin_unlock_irqrestore(&bank->lock, flags);
1168
1169 return 0;
1170 }
1171
1172 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1173 {
1174 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1175 unsigned long flags;
1176
1177 spin_lock_irqsave(&bank->lock, flags);
1178 #ifdef CONFIG_ARCH_OMAP16XX
1179 if (bank->method == METHOD_GPIO_1610) {
1180 /* Disable wake-up during idle for dynamic tick */
1181 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1182 __raw_writel(1 << offset, reg);
1183 }
1184 #endif
1185 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1186 defined(CONFIG_ARCH_OMAP4)
1187 if (bank->method == METHOD_GPIO_24XX) {
1188 /* Disable wake-up during idle for dynamic tick */
1189 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1190 __raw_writel(1 << offset, reg);
1191 }
1192 #endif
1193 if (!cpu_class_is_omap1()) {
1194 bank->mod_usage &= ~(1 << offset);
1195 if (!bank->mod_usage) {
1196 u32 ctrl;
1197 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1198 /* Module is disabled, clocks are gated */
1199 ctrl |= 1;
1200 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1201 }
1202 }
1203 _reset_gpio(bank, bank->chip.base + offset);
1204 spin_unlock_irqrestore(&bank->lock, flags);
1205 }
1206
1207 /*
1208 * We need to unmask the GPIO bank interrupt as soon as possible to
1209 * avoid missing GPIO interrupts for other lines in the bank.
1210 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1211 * in the bank to avoid missing nested interrupts for a GPIO line.
1212 * If we wait to unmask individual GPIO lines in the bank after the
1213 * line's interrupt handler has been run, we may miss some nested
1214 * interrupts.
1215 */
1216 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1217 {
1218 void __iomem *isr_reg = NULL;
1219 u32 isr;
1220 unsigned int gpio_irq;
1221 struct gpio_bank *bank;
1222 u32 retrigger = 0;
1223 int unmasked = 0;
1224
1225 desc->chip->ack(irq);
1226
1227 bank = get_irq_data(irq);
1228 #ifdef CONFIG_ARCH_OMAP1
1229 if (bank->method == METHOD_MPUIO)
1230 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1231 #endif
1232 #ifdef CONFIG_ARCH_OMAP15XX
1233 if (bank->method == METHOD_GPIO_1510)
1234 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1235 #endif
1236 #if defined(CONFIG_ARCH_OMAP16XX)
1237 if (bank->method == METHOD_GPIO_1610)
1238 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1239 #endif
1240 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1241 if (bank->method == METHOD_GPIO_7XX)
1242 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1243 #endif
1244 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1245 if (bank->method == METHOD_GPIO_24XX)
1246 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1247 #endif
1248 #if defined(CONFIG_ARCH_OMAP4)
1249 if (bank->method == METHOD_GPIO_24XX)
1250 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1251 #endif
1252 while(1) {
1253 u32 isr_saved, level_mask = 0;
1254 u32 enabled;
1255
1256 enabled = _get_gpio_irqbank_mask(bank);
1257 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1258
1259 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1260 isr &= 0x0000ffff;
1261
1262 if (cpu_class_is_omap2()) {
1263 level_mask = bank->level_mask & enabled;
1264 }
1265
1266 /* clear edge sensitive interrupts before handler(s) are
1267 called so that we don't miss any interrupt occurred while
1268 executing them */
1269 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1270 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1271 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1272
1273 /* if there is only edge sensitive GPIO pin interrupts
1274 configured, we could unmask GPIO bank interrupt immediately */
1275 if (!level_mask && !unmasked) {
1276 unmasked = 1;
1277 desc->chip->unmask(irq);
1278 }
1279
1280 isr |= retrigger;
1281 retrigger = 0;
1282 if (!isr)
1283 break;
1284
1285 gpio_irq = bank->virtual_irq_start;
1286 for (; isr != 0; isr >>= 1, gpio_irq++) {
1287 if (!(isr & 1))
1288 continue;
1289
1290 generic_handle_irq(gpio_irq);
1291 }
1292 }
1293 /* if bank has any level sensitive GPIO pin interrupt
1294 configured, we must unmask the bank interrupt only after
1295 handler(s) are executed in order to avoid spurious bank
1296 interrupt */
1297 if (!unmasked)
1298 desc->chip->unmask(irq);
1299
1300 }
1301
1302 static void gpio_irq_shutdown(unsigned int irq)
1303 {
1304 unsigned int gpio = irq - IH_GPIO_BASE;
1305 struct gpio_bank *bank = get_irq_chip_data(irq);
1306
1307 _reset_gpio(bank, gpio);
1308 }
1309
1310 static void gpio_ack_irq(unsigned int irq)
1311 {
1312 unsigned int gpio = irq - IH_GPIO_BASE;
1313 struct gpio_bank *bank = get_irq_chip_data(irq);
1314
1315 _clear_gpio_irqstatus(bank, gpio);
1316 }
1317
1318 static void gpio_mask_irq(unsigned int irq)
1319 {
1320 unsigned int gpio = irq - IH_GPIO_BASE;
1321 struct gpio_bank *bank = get_irq_chip_data(irq);
1322
1323 _set_gpio_irqenable(bank, gpio, 0);
1324 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1325 }
1326
1327 static void gpio_unmask_irq(unsigned int irq)
1328 {
1329 unsigned int gpio = irq - IH_GPIO_BASE;
1330 struct gpio_bank *bank = get_irq_chip_data(irq);
1331 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1332 struct irq_desc *desc = irq_to_desc(irq);
1333 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1334
1335 if (trigger)
1336 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1337
1338 /* For level-triggered GPIOs, the clearing must be done after
1339 * the HW source is cleared, thus after the handler has run */
1340 if (bank->level_mask & irq_mask) {
1341 _set_gpio_irqenable(bank, gpio, 0);
1342 _clear_gpio_irqstatus(bank, gpio);
1343 }
1344
1345 _set_gpio_irqenable(bank, gpio, 1);
1346 }
1347
1348 static struct irq_chip gpio_irq_chip = {
1349 .name = "GPIO",
1350 .shutdown = gpio_irq_shutdown,
1351 .ack = gpio_ack_irq,
1352 .mask = gpio_mask_irq,
1353 .unmask = gpio_unmask_irq,
1354 .set_type = gpio_irq_type,
1355 .set_wake = gpio_wake_enable,
1356 };
1357
1358 /*---------------------------------------------------------------------*/
1359
1360 #ifdef CONFIG_ARCH_OMAP1
1361
1362 /* MPUIO uses the always-on 32k clock */
1363
1364 static void mpuio_ack_irq(unsigned int irq)
1365 {
1366 /* The ISR is reset automatically, so do nothing here. */
1367 }
1368
1369 static void mpuio_mask_irq(unsigned int irq)
1370 {
1371 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1372 struct gpio_bank *bank = get_irq_chip_data(irq);
1373
1374 _set_gpio_irqenable(bank, gpio, 0);
1375 }
1376
1377 static void mpuio_unmask_irq(unsigned int irq)
1378 {
1379 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1380 struct gpio_bank *bank = get_irq_chip_data(irq);
1381
1382 _set_gpio_irqenable(bank, gpio, 1);
1383 }
1384
1385 static struct irq_chip mpuio_irq_chip = {
1386 .name = "MPUIO",
1387 .ack = mpuio_ack_irq,
1388 .mask = mpuio_mask_irq,
1389 .unmask = mpuio_unmask_irq,
1390 .set_type = gpio_irq_type,
1391 #ifdef CONFIG_ARCH_OMAP16XX
1392 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1393 .set_wake = gpio_wake_enable,
1394 #endif
1395 };
1396
1397
1398 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1399
1400
1401 #ifdef CONFIG_ARCH_OMAP16XX
1402
1403 #include <linux/platform_device.h>
1404
1405 static int omap_mpuio_suspend_noirq(struct device *dev)
1406 {
1407 struct platform_device *pdev = to_platform_device(dev);
1408 struct gpio_bank *bank = platform_get_drvdata(pdev);
1409 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1410 unsigned long flags;
1411
1412 spin_lock_irqsave(&bank->lock, flags);
1413 bank->saved_wakeup = __raw_readl(mask_reg);
1414 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1415 spin_unlock_irqrestore(&bank->lock, flags);
1416
1417 return 0;
1418 }
1419
1420 static int omap_mpuio_resume_noirq(struct device *dev)
1421 {
1422 struct platform_device *pdev = to_platform_device(dev);
1423 struct gpio_bank *bank = platform_get_drvdata(pdev);
1424 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1425 unsigned long flags;
1426
1427 spin_lock_irqsave(&bank->lock, flags);
1428 __raw_writel(bank->saved_wakeup, mask_reg);
1429 spin_unlock_irqrestore(&bank->lock, flags);
1430
1431 return 0;
1432 }
1433
1434 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1435 .suspend_noirq = omap_mpuio_suspend_noirq,
1436 .resume_noirq = omap_mpuio_resume_noirq,
1437 };
1438
1439 /* use platform_driver for this, now that there's no longer any
1440 * point to sys_device (other than not disturbing old code).
1441 */
1442 static struct platform_driver omap_mpuio_driver = {
1443 .driver = {
1444 .name = "mpuio",
1445 .pm = &omap_mpuio_dev_pm_ops,
1446 },
1447 };
1448
1449 static struct platform_device omap_mpuio_device = {
1450 .name = "mpuio",
1451 .id = -1,
1452 .dev = {
1453 .driver = &omap_mpuio_driver.driver,
1454 }
1455 /* could list the /proc/iomem resources */
1456 };
1457
1458 static inline void mpuio_init(void)
1459 {
1460 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1461
1462 if (platform_driver_register(&omap_mpuio_driver) == 0)
1463 (void) platform_device_register(&omap_mpuio_device);
1464 }
1465
1466 #else
1467 static inline void mpuio_init(void) {}
1468 #endif /* 16xx */
1469
1470 #else
1471
1472 extern struct irq_chip mpuio_irq_chip;
1473
1474 #define bank_is_mpuio(bank) 0
1475 static inline void mpuio_init(void) {}
1476
1477 #endif
1478
1479 /*---------------------------------------------------------------------*/
1480
1481 /* REVISIT these are stupid implementations! replace by ones that
1482 * don't switch on METHOD_* and which mostly avoid spinlocks
1483 */
1484
1485 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1486 {
1487 struct gpio_bank *bank;
1488 unsigned long flags;
1489
1490 bank = container_of(chip, struct gpio_bank, chip);
1491 spin_lock_irqsave(&bank->lock, flags);
1492 _set_gpio_direction(bank, offset, 1);
1493 spin_unlock_irqrestore(&bank->lock, flags);
1494 return 0;
1495 }
1496
1497 static int gpio_is_input(struct gpio_bank *bank, int mask)
1498 {
1499 void __iomem *reg = bank->base;
1500
1501 switch (bank->method) {
1502 case METHOD_MPUIO:
1503 reg += OMAP_MPUIO_IO_CNTL;
1504 break;
1505 case METHOD_GPIO_1510:
1506 reg += OMAP1510_GPIO_DIR_CONTROL;
1507 break;
1508 case METHOD_GPIO_1610:
1509 reg += OMAP1610_GPIO_DIRECTION;
1510 break;
1511 case METHOD_GPIO_7XX:
1512 reg += OMAP7XX_GPIO_DIR_CONTROL;
1513 break;
1514 case METHOD_GPIO_24XX:
1515 reg += OMAP24XX_GPIO_OE;
1516 break;
1517 }
1518 return __raw_readl(reg) & mask;
1519 }
1520
1521 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1522 {
1523 struct gpio_bank *bank;
1524 void __iomem *reg;
1525 int gpio;
1526 u32 mask;
1527
1528 gpio = chip->base + offset;
1529 bank = get_gpio_bank(gpio);
1530 reg = bank->base;
1531 mask = 1 << get_gpio_index(gpio);
1532
1533 if (gpio_is_input(bank, mask))
1534 return _get_gpio_datain(bank, gpio);
1535 else
1536 return _get_gpio_dataout(bank, gpio);
1537 }
1538
1539 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1540 {
1541 struct gpio_bank *bank;
1542 unsigned long flags;
1543
1544 bank = container_of(chip, struct gpio_bank, chip);
1545 spin_lock_irqsave(&bank->lock, flags);
1546 _set_gpio_dataout(bank, offset, value);
1547 _set_gpio_direction(bank, offset, 0);
1548 spin_unlock_irqrestore(&bank->lock, flags);
1549 return 0;
1550 }
1551
1552 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1553 {
1554 struct gpio_bank *bank;
1555 unsigned long flags;
1556
1557 bank = container_of(chip, struct gpio_bank, chip);
1558 spin_lock_irqsave(&bank->lock, flags);
1559 _set_gpio_dataout(bank, offset, value);
1560 spin_unlock_irqrestore(&bank->lock, flags);
1561 }
1562
1563 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1564 {
1565 struct gpio_bank *bank;
1566
1567 bank = container_of(chip, struct gpio_bank, chip);
1568 return bank->virtual_irq_start + offset;
1569 }
1570
1571 /*---------------------------------------------------------------------*/
1572
1573 static int initialized;
1574 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1575 static struct clk * gpio_ick;
1576 #endif
1577
1578 #if defined(CONFIG_ARCH_OMAP2)
1579 static struct clk * gpio_fck;
1580 #endif
1581
1582 #if defined(CONFIG_ARCH_OMAP2430)
1583 static struct clk * gpio5_ick;
1584 static struct clk * gpio5_fck;
1585 #endif
1586
1587 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1588 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1589 #endif
1590
1591 static void __init omap_gpio_show_rev(void)
1592 {
1593 u32 rev;
1594
1595 if (cpu_is_omap16xx())
1596 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1597 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1598 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1599 else if (cpu_is_omap44xx())
1600 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1601 else
1602 return;
1603
1604 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1605 (rev >> 4) & 0x0f, rev & 0x0f);
1606 }
1607
1608 /* This lock class tells lockdep that GPIO irqs are in a different
1609 * category than their parents, so it won't report false recursion.
1610 */
1611 static struct lock_class_key gpio_lock_class;
1612
1613 static int __init _omap_gpio_init(void)
1614 {
1615 int i;
1616 int gpio = 0;
1617 struct gpio_bank *bank;
1618 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1619 char clk_name[11];
1620
1621 initialized = 1;
1622
1623 #if defined(CONFIG_ARCH_OMAP1)
1624 if (cpu_is_omap15xx()) {
1625 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1626 if (IS_ERR(gpio_ick))
1627 printk("Could not get arm_gpio_ck\n");
1628 else
1629 clk_enable(gpio_ick);
1630 }
1631 #endif
1632 #if defined(CONFIG_ARCH_OMAP2)
1633 if (cpu_class_is_omap2()) {
1634 gpio_ick = clk_get(NULL, "gpios_ick");
1635 if (IS_ERR(gpio_ick))
1636 printk("Could not get gpios_ick\n");
1637 else
1638 clk_enable(gpio_ick);
1639 gpio_fck = clk_get(NULL, "gpios_fck");
1640 if (IS_ERR(gpio_fck))
1641 printk("Could not get gpios_fck\n");
1642 else
1643 clk_enable(gpio_fck);
1644
1645 /*
1646 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1647 */
1648 #if defined(CONFIG_ARCH_OMAP2430)
1649 if (cpu_is_omap2430()) {
1650 gpio5_ick = clk_get(NULL, "gpio5_ick");
1651 if (IS_ERR(gpio5_ick))
1652 printk("Could not get gpio5_ick\n");
1653 else
1654 clk_enable(gpio5_ick);
1655 gpio5_fck = clk_get(NULL, "gpio5_fck");
1656 if (IS_ERR(gpio5_fck))
1657 printk("Could not get gpio5_fck\n");
1658 else
1659 clk_enable(gpio5_fck);
1660 }
1661 #endif
1662 }
1663 #endif
1664
1665 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1666 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1667 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1668 sprintf(clk_name, "gpio%d_ick", i + 1);
1669 gpio_iclks[i] = clk_get(NULL, clk_name);
1670 if (IS_ERR(gpio_iclks[i]))
1671 printk(KERN_ERR "Could not get %s\n", clk_name);
1672 else
1673 clk_enable(gpio_iclks[i]);
1674 }
1675 }
1676 #endif
1677
1678
1679 #ifdef CONFIG_ARCH_OMAP15XX
1680 if (cpu_is_omap15xx()) {
1681 gpio_bank_count = 2;
1682 gpio_bank = gpio_bank_1510;
1683 bank_size = SZ_2K;
1684 }
1685 #endif
1686 #if defined(CONFIG_ARCH_OMAP16XX)
1687 if (cpu_is_omap16xx()) {
1688 gpio_bank_count = 5;
1689 gpio_bank = gpio_bank_1610;
1690 bank_size = SZ_2K;
1691 }
1692 #endif
1693 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1694 if (cpu_is_omap7xx()) {
1695 gpio_bank_count = 7;
1696 gpio_bank = gpio_bank_7xx;
1697 bank_size = SZ_2K;
1698 }
1699 #endif
1700 #ifdef CONFIG_ARCH_OMAP24XX
1701 if (cpu_is_omap242x()) {
1702 gpio_bank_count = 4;
1703 gpio_bank = gpio_bank_242x;
1704 }
1705 if (cpu_is_omap243x()) {
1706 gpio_bank_count = 5;
1707 gpio_bank = gpio_bank_243x;
1708 }
1709 #endif
1710 #ifdef CONFIG_ARCH_OMAP34XX
1711 if (cpu_is_omap34xx()) {
1712 gpio_bank_count = OMAP34XX_NR_GPIOS;
1713 gpio_bank = gpio_bank_34xx;
1714 }
1715 #endif
1716 #ifdef CONFIG_ARCH_OMAP4
1717 if (cpu_is_omap44xx()) {
1718 gpio_bank_count = OMAP34XX_NR_GPIOS;
1719 gpio_bank = gpio_bank_44xx;
1720 }
1721 #endif
1722 for (i = 0; i < gpio_bank_count; i++) {
1723 int j, gpio_count = 16;
1724
1725 bank = &gpio_bank[i];
1726 spin_lock_init(&bank->lock);
1727
1728 /* Static mapping, never released */
1729 bank->base = ioremap(bank->pbase, bank_size);
1730 if (!bank->base) {
1731 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1732 continue;
1733 }
1734
1735 if (bank_is_mpuio(bank))
1736 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1737 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1738 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1739 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1740 }
1741 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1742 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1743 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1744 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1745 }
1746 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1747 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1748 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1749
1750 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1751 }
1752
1753 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1754 defined(CONFIG_ARCH_OMAP4)
1755 if (bank->method == METHOD_GPIO_24XX) {
1756 static const u32 non_wakeup_gpios[] = {
1757 0xe203ffc0, 0x08700040
1758 };
1759 if (cpu_is_omap44xx()) {
1760 __raw_writel(0xffffffff, bank->base +
1761 OMAP4_GPIO_IRQSTATUSCLR0);
1762 __raw_writew(0x0015, bank->base +
1763 OMAP4_GPIO_SYSCONFIG);
1764 __raw_writel(0x00000000, bank->base +
1765 OMAP4_GPIO_DEBOUNCENABLE);
1766 /* Initialize interface clock ungated, module enabled */
1767 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1768 } else {
1769 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1770 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1771 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1772 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1773
1774 /* Initialize interface clock ungated, module enabled */
1775 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1776 }
1777 if (i < ARRAY_SIZE(non_wakeup_gpios))
1778 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1779 gpio_count = 32;
1780 }
1781 #endif
1782
1783 bank->mod_usage = 0;
1784 /* REVISIT eventually switch from OMAP-specific gpio structs
1785 * over to the generic ones
1786 */
1787 bank->chip.request = omap_gpio_request;
1788 bank->chip.free = omap_gpio_free;
1789 bank->chip.direction_input = gpio_input;
1790 bank->chip.get = gpio_get;
1791 bank->chip.direction_output = gpio_output;
1792 bank->chip.set = gpio_set;
1793 bank->chip.to_irq = gpio_2irq;
1794 if (bank_is_mpuio(bank)) {
1795 bank->chip.label = "mpuio";
1796 #ifdef CONFIG_ARCH_OMAP16XX
1797 bank->chip.dev = &omap_mpuio_device.dev;
1798 #endif
1799 bank->chip.base = OMAP_MPUIO(0);
1800 } else {
1801 bank->chip.label = "gpio";
1802 bank->chip.base = gpio;
1803 gpio += gpio_count;
1804 }
1805 bank->chip.ngpio = gpio_count;
1806
1807 gpiochip_add(&bank->chip);
1808
1809 for (j = bank->virtual_irq_start;
1810 j < bank->virtual_irq_start + gpio_count; j++) {
1811 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1812 set_irq_chip_data(j, bank);
1813 if (bank_is_mpuio(bank))
1814 set_irq_chip(j, &mpuio_irq_chip);
1815 else
1816 set_irq_chip(j, &gpio_irq_chip);
1817 set_irq_handler(j, handle_simple_irq);
1818 set_irq_flags(j, IRQF_VALID);
1819 }
1820 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1821 set_irq_data(bank->irq, bank);
1822
1823 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1824 sprintf(clk_name, "gpio%d_dbck", i + 1);
1825 bank->dbck = clk_get(NULL, clk_name);
1826 if (IS_ERR(bank->dbck))
1827 printk(KERN_ERR "Could not get %s\n", clk_name);
1828 }
1829 }
1830
1831 /* Enable system clock for GPIO module.
1832 * The CAM_CLK_CTRL *is* really the right place. */
1833 if (cpu_is_omap16xx())
1834 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1835
1836 /* Enable autoidle for the OCP interface */
1837 if (cpu_is_omap24xx())
1838 omap_writel(1 << 0, 0x48019010);
1839 if (cpu_is_omap34xx())
1840 omap_writel(1 << 0, 0x48306814);
1841
1842 omap_gpio_show_rev();
1843
1844 return 0;
1845 }
1846
1847 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1848 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1849 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1850 {
1851 int i;
1852
1853 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1854 return 0;
1855
1856 for (i = 0; i < gpio_bank_count; i++) {
1857 struct gpio_bank *bank = &gpio_bank[i];
1858 void __iomem *wake_status;
1859 void __iomem *wake_clear;
1860 void __iomem *wake_set;
1861 unsigned long flags;
1862
1863 switch (bank->method) {
1864 #ifdef CONFIG_ARCH_OMAP16XX
1865 case METHOD_GPIO_1610:
1866 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1867 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1868 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1869 break;
1870 #endif
1871 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1872 case METHOD_GPIO_24XX:
1873 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1874 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1875 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1876 break;
1877 #endif
1878 #ifdef CONFIG_ARCH_OMAP4
1879 case METHOD_GPIO_24XX:
1880 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1881 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1882 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1883 break;
1884 #endif
1885 default:
1886 continue;
1887 }
1888
1889 spin_lock_irqsave(&bank->lock, flags);
1890 bank->saved_wakeup = __raw_readl(wake_status);
1891 __raw_writel(0xffffffff, wake_clear);
1892 __raw_writel(bank->suspend_wakeup, wake_set);
1893 spin_unlock_irqrestore(&bank->lock, flags);
1894 }
1895
1896 return 0;
1897 }
1898
1899 static int omap_gpio_resume(struct sys_device *dev)
1900 {
1901 int i;
1902
1903 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1904 return 0;
1905
1906 for (i = 0; i < gpio_bank_count; i++) {
1907 struct gpio_bank *bank = &gpio_bank[i];
1908 void __iomem *wake_clear;
1909 void __iomem *wake_set;
1910 unsigned long flags;
1911
1912 switch (bank->method) {
1913 #ifdef CONFIG_ARCH_OMAP16XX
1914 case METHOD_GPIO_1610:
1915 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1916 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1917 break;
1918 #endif
1919 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1920 case METHOD_GPIO_24XX:
1921 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1922 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1923 break;
1924 #endif
1925 #ifdef CONFIG_ARCH_OMAP4
1926 case METHOD_GPIO_24XX:
1927 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1928 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1929 break;
1930 #endif
1931 default:
1932 continue;
1933 }
1934
1935 spin_lock_irqsave(&bank->lock, flags);
1936 __raw_writel(0xffffffff, wake_clear);
1937 __raw_writel(bank->saved_wakeup, wake_set);
1938 spin_unlock_irqrestore(&bank->lock, flags);
1939 }
1940
1941 return 0;
1942 }
1943
1944 static struct sysdev_class omap_gpio_sysclass = {
1945 .name = "gpio",
1946 .suspend = omap_gpio_suspend,
1947 .resume = omap_gpio_resume,
1948 };
1949
1950 static struct sys_device omap_gpio_device = {
1951 .id = 0,
1952 .cls = &omap_gpio_sysclass,
1953 };
1954
1955 #endif
1956
1957 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1958 defined(CONFIG_ARCH_OMAP4)
1959
1960 static int workaround_enabled;
1961
1962 void omap2_gpio_prepare_for_retention(void)
1963 {
1964 int i, c = 0;
1965
1966 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1967 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1968 for (i = 0; i < gpio_bank_count; i++) {
1969 struct gpio_bank *bank = &gpio_bank[i];
1970 u32 l1, l2;
1971
1972 if (!(bank->enabled_non_wakeup_gpios))
1973 continue;
1974 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1975 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1976 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1977 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1978 #endif
1979 #ifdef CONFIG_ARCH_OMAP4
1980 bank->saved_datain = __raw_readl(bank->base +
1981 OMAP4_GPIO_DATAIN);
1982 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1983 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
1984 #endif
1985 bank->saved_fallingdetect = l1;
1986 bank->saved_risingdetect = l2;
1987 l1 &= ~bank->enabled_non_wakeup_gpios;
1988 l2 &= ~bank->enabled_non_wakeup_gpios;
1989 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1990 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1991 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1992 #endif
1993 #ifdef CONFIG_ARCH_OMAP4
1994 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1995 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1996 #endif
1997 c++;
1998 }
1999 if (!c) {
2000 workaround_enabled = 0;
2001 return;
2002 }
2003 workaround_enabled = 1;
2004 }
2005
2006 void omap2_gpio_resume_after_retention(void)
2007 {
2008 int i;
2009
2010 if (!workaround_enabled)
2011 return;
2012 for (i = 0; i < gpio_bank_count; i++) {
2013 struct gpio_bank *bank = &gpio_bank[i];
2014 u32 l, gen, gen0, gen1;
2015
2016 if (!(bank->enabled_non_wakeup_gpios))
2017 continue;
2018 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2019 __raw_writel(bank->saved_fallingdetect,
2020 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2021 __raw_writel(bank->saved_risingdetect,
2022 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2023 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2024 #endif
2025 #ifdef CONFIG_ARCH_OMAP4
2026 __raw_writel(bank->saved_fallingdetect,
2027 bank->base + OMAP4_GPIO_FALLINGDETECT);
2028 __raw_writel(bank->saved_risingdetect,
2029 bank->base + OMAP4_GPIO_RISINGDETECT);
2030 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2031 #endif
2032 /* Check if any of the non-wakeup interrupt GPIOs have changed
2033 * state. If so, generate an IRQ by software. This is
2034 * horribly racy, but it's the best we can do to work around
2035 * this silicon bug. */
2036 l ^= bank->saved_datain;
2037 l &= bank->non_wakeup_gpios;
2038
2039 /*
2040 * No need to generate IRQs for the rising edge for gpio IRQs
2041 * configured with falling edge only; and vice versa.
2042 */
2043 gen0 = l & bank->saved_fallingdetect;
2044 gen0 &= bank->saved_datain;
2045
2046 gen1 = l & bank->saved_risingdetect;
2047 gen1 &= ~(bank->saved_datain);
2048
2049 /* FIXME: Consider GPIO IRQs with level detections properly! */
2050 gen = l & (~(bank->saved_fallingdetect) &
2051 ~(bank->saved_risingdetect));
2052 /* Consider all GPIO IRQs needed to be updated */
2053 gen |= gen0 | gen1;
2054
2055 if (gen) {
2056 u32 old0, old1;
2057 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2058 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2059 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2060 __raw_writel(old0 | gen, bank->base +
2061 OMAP24XX_GPIO_LEVELDETECT0);
2062 __raw_writel(old1 | gen, bank->base +
2063 OMAP24XX_GPIO_LEVELDETECT1);
2064 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2065 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2066 #endif
2067 #ifdef CONFIG_ARCH_OMAP4
2068 old0 = __raw_readl(bank->base +
2069 OMAP4_GPIO_LEVELDETECT0);
2070 old1 = __raw_readl(bank->base +
2071 OMAP4_GPIO_LEVELDETECT1);
2072 __raw_writel(old0 | l, bank->base +
2073 OMAP4_GPIO_LEVELDETECT0);
2074 __raw_writel(old1 | l, bank->base +
2075 OMAP4_GPIO_LEVELDETECT1);
2076 __raw_writel(old0, bank->base +
2077 OMAP4_GPIO_LEVELDETECT0);
2078 __raw_writel(old1, bank->base +
2079 OMAP4_GPIO_LEVELDETECT1);
2080 #endif
2081 }
2082 }
2083
2084 }
2085
2086 #endif
2087
2088 #ifdef CONFIG_ARCH_OMAP34XX
2089 /* save the registers of bank 2-6 */
2090 void omap_gpio_save_context(void)
2091 {
2092 int i;
2093
2094 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2095 for (i = 1; i < gpio_bank_count; i++) {
2096 struct gpio_bank *bank = &gpio_bank[i];
2097 gpio_context[i].sysconfig =
2098 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2099 gpio_context[i].irqenable1 =
2100 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2101 gpio_context[i].irqenable2 =
2102 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2103 gpio_context[i].wake_en =
2104 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2105 gpio_context[i].ctrl =
2106 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2107 gpio_context[i].oe =
2108 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2109 gpio_context[i].leveldetect0 =
2110 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2111 gpio_context[i].leveldetect1 =
2112 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2113 gpio_context[i].risingdetect =
2114 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2115 gpio_context[i].fallingdetect =
2116 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2117 gpio_context[i].dataout =
2118 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2119 gpio_context[i].setwkuena =
2120 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2121 gpio_context[i].setdataout =
2122 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2123 }
2124 }
2125
2126 /* restore the required registers of bank 2-6 */
2127 void omap_gpio_restore_context(void)
2128 {
2129 int i;
2130
2131 for (i = 1; i < gpio_bank_count; i++) {
2132 struct gpio_bank *bank = &gpio_bank[i];
2133 __raw_writel(gpio_context[i].sysconfig,
2134 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2135 __raw_writel(gpio_context[i].irqenable1,
2136 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2137 __raw_writel(gpio_context[i].irqenable2,
2138 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2139 __raw_writel(gpio_context[i].wake_en,
2140 bank->base + OMAP24XX_GPIO_WAKE_EN);
2141 __raw_writel(gpio_context[i].ctrl,
2142 bank->base + OMAP24XX_GPIO_CTRL);
2143 __raw_writel(gpio_context[i].oe,
2144 bank->base + OMAP24XX_GPIO_OE);
2145 __raw_writel(gpio_context[i].leveldetect0,
2146 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2147 __raw_writel(gpio_context[i].leveldetect1,
2148 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2149 __raw_writel(gpio_context[i].risingdetect,
2150 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2151 __raw_writel(gpio_context[i].fallingdetect,
2152 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2153 __raw_writel(gpio_context[i].dataout,
2154 bank->base + OMAP24XX_GPIO_DATAOUT);
2155 __raw_writel(gpio_context[i].setwkuena,
2156 bank->base + OMAP24XX_GPIO_SETWKUENA);
2157 __raw_writel(gpio_context[i].setdataout,
2158 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2159 }
2160 }
2161 #endif
2162
2163 /*
2164 * This may get called early from board specific init
2165 * for boards that have interrupts routed via FPGA.
2166 */
2167 int __init omap_gpio_init(void)
2168 {
2169 if (!initialized)
2170 return _omap_gpio_init();
2171 else
2172 return 0;
2173 }
2174
2175 static int __init omap_gpio_sysinit(void)
2176 {
2177 int ret = 0;
2178
2179 if (!initialized)
2180 ret = _omap_gpio_init();
2181
2182 mpuio_init();
2183
2184 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2185 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2186 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2187 if (ret == 0) {
2188 ret = sysdev_class_register(&omap_gpio_sysclass);
2189 if (ret == 0)
2190 ret = sysdev_register(&omap_gpio_device);
2191 }
2192 }
2193 #endif
2194
2195 return ret;
2196 }
2197
2198 arch_initcall(omap_gpio_sysinit);
2199
2200
2201 #ifdef CONFIG_DEBUG_FS
2202
2203 #include <linux/debugfs.h>
2204 #include <linux/seq_file.h>
2205
2206 static int dbg_gpio_show(struct seq_file *s, void *unused)
2207 {
2208 unsigned i, j, gpio;
2209
2210 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2211 struct gpio_bank *bank = gpio_bank + i;
2212 unsigned bankwidth = 16;
2213 u32 mask = 1;
2214
2215 if (bank_is_mpuio(bank))
2216 gpio = OMAP_MPUIO(0);
2217 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2218 bankwidth = 32;
2219
2220 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2221 unsigned irq, value, is_in, irqstat;
2222 const char *label;
2223
2224 label = gpiochip_is_requested(&bank->chip, j);
2225 if (!label)
2226 continue;
2227
2228 irq = bank->virtual_irq_start + j;
2229 value = gpio_get_value(gpio);
2230 is_in = gpio_is_input(bank, mask);
2231
2232 if (bank_is_mpuio(bank))
2233 seq_printf(s, "MPUIO %2d ", j);
2234 else
2235 seq_printf(s, "GPIO %3d ", gpio);
2236 seq_printf(s, "(%-20.20s): %s %s",
2237 label,
2238 is_in ? "in " : "out",
2239 value ? "hi" : "lo");
2240
2241 /* FIXME for at least omap2, show pullup/pulldown state */
2242
2243 irqstat = irq_desc[irq].status;
2244 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2245 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2246 if (is_in && ((bank->suspend_wakeup & mask)
2247 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2248 char *trigger = NULL;
2249
2250 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2251 case IRQ_TYPE_EDGE_FALLING:
2252 trigger = "falling";
2253 break;
2254 case IRQ_TYPE_EDGE_RISING:
2255 trigger = "rising";
2256 break;
2257 case IRQ_TYPE_EDGE_BOTH:
2258 trigger = "bothedge";
2259 break;
2260 case IRQ_TYPE_LEVEL_LOW:
2261 trigger = "low";
2262 break;
2263 case IRQ_TYPE_LEVEL_HIGH:
2264 trigger = "high";
2265 break;
2266 case IRQ_TYPE_NONE:
2267 trigger = "(?)";
2268 break;
2269 }
2270 seq_printf(s, ", irq-%d %-8s%s",
2271 irq, trigger,
2272 (bank->suspend_wakeup & mask)
2273 ? " wakeup" : "");
2274 }
2275 #endif
2276 seq_printf(s, "\n");
2277 }
2278
2279 if (bank_is_mpuio(bank)) {
2280 seq_printf(s, "\n");
2281 gpio = 0;
2282 }
2283 }
2284 return 0;
2285 }
2286
2287 static int dbg_gpio_open(struct inode *inode, struct file *file)
2288 {
2289 return single_open(file, dbg_gpio_show, &inode->i_private);
2290 }
2291
2292 static const struct file_operations debug_fops = {
2293 .open = dbg_gpio_open,
2294 .read = seq_read,
2295 .llseek = seq_lseek,
2296 .release = single_release,
2297 };
2298
2299 static int __init omap_gpio_debuginit(void)
2300 {
2301 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2302 NULL, NULL, &debug_fops);
2303 return 0;
2304 }
2305 late_initcall(omap_gpio_debuginit);
2306 #endif
Linux kernel - Deliverables
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