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ARM: OMAP: Fix typo for 24xx GPIO resume
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22
23 #include <asm/hardware.h>
24 #include <asm/irq.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
28
29 #include <asm/io.h>
30
31 /*
32 * OMAP1510 GPIO registers
33 */
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43 #define OMAP1510_IH_GPIO_BASE 64
44
45 /*
46 * OMAP1610 specific GPIO registers
47 */
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70 /*
71 * OMAP730 specific GPIO registers
72 */
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
85
86 /*
87 * omap24xx specific GPIO registers
88 */
89 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP24XX_GPIO_REVISION 0x0000
94 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
95 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
96 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
98 #define OMAP24XX_GPIO_CTRL 0x0030
99 #define OMAP24XX_GPIO_OE 0x0034
100 #define OMAP24XX_GPIO_DATAIN 0x0038
101 #define OMAP24XX_GPIO_DATAOUT 0x003c
102 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
103 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
104 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
105 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
106 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
107 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
108 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
109 #define OMAP24XX_GPIO_SETWKUENA 0x0084
110 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
111 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
112
113 struct gpio_bank {
114 void __iomem *base;
115 u16 irq;
116 u16 virtual_irq_start;
117 int method;
118 u32 reserved_map;
119 u32 suspend_wakeup;
120 u32 saved_wakeup;
121 spinlock_t lock;
122 };
123
124 #define METHOD_MPUIO 0
125 #define METHOD_GPIO_1510 1
126 #define METHOD_GPIO_1610 2
127 #define METHOD_GPIO_730 3
128 #define METHOD_GPIO_24XX 4
129
130 #ifdef CONFIG_ARCH_OMAP16XX
131 static struct gpio_bank gpio_bank_1610[5] = {
132 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
133 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
134 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
135 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
136 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
137 };
138 #endif
139
140 #ifdef CONFIG_ARCH_OMAP15XX
141 static struct gpio_bank gpio_bank_1510[2] = {
142 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
143 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
144 };
145 #endif
146
147 #ifdef CONFIG_ARCH_OMAP730
148 static struct gpio_bank gpio_bank_730[7] = {
149 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
150 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
151 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
152 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
153 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
154 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
155 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
156 };
157 #endif
158
159 #ifdef CONFIG_ARCH_OMAP24XX
160 static struct gpio_bank gpio_bank_24xx[4] = {
161 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
162 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
163 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
164 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
165 };
166 #endif
167
168 static struct gpio_bank *gpio_bank;
169 static int gpio_bank_count;
170
171 static inline struct gpio_bank *get_gpio_bank(int gpio)
172 {
173 #ifdef CONFIG_ARCH_OMAP15XX
174 if (cpu_is_omap15xx()) {
175 if (OMAP_GPIO_IS_MPUIO(gpio))
176 return &gpio_bank[0];
177 return &gpio_bank[1];
178 }
179 #endif
180 #if defined(CONFIG_ARCH_OMAP16XX)
181 if (cpu_is_omap16xx()) {
182 if (OMAP_GPIO_IS_MPUIO(gpio))
183 return &gpio_bank[0];
184 return &gpio_bank[1 + (gpio >> 4)];
185 }
186 #endif
187 #ifdef CONFIG_ARCH_OMAP730
188 if (cpu_is_omap730()) {
189 if (OMAP_GPIO_IS_MPUIO(gpio))
190 return &gpio_bank[0];
191 return &gpio_bank[1 + (gpio >> 5)];
192 }
193 #endif
194 #ifdef CONFIG_ARCH_OMAP24XX
195 if (cpu_is_omap24xx())
196 return &gpio_bank[gpio >> 5];
197 #endif
198 }
199
200 static inline int get_gpio_index(int gpio)
201 {
202 #ifdef CONFIG_ARCH_OMAP730
203 if (cpu_is_omap730())
204 return gpio & 0x1f;
205 #endif
206 #ifdef CONFIG_ARCH_OMAP24XX
207 if (cpu_is_omap24xx())
208 return gpio & 0x1f;
209 #endif
210 return gpio & 0x0f;
211 }
212
213 static inline int gpio_valid(int gpio)
214 {
215 if (gpio < 0)
216 return -1;
217 #ifndef CONFIG_ARCH_OMAP24XX
218 if (OMAP_GPIO_IS_MPUIO(gpio)) {
219 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
220 return -1;
221 return 0;
222 }
223 #endif
224 #ifdef CONFIG_ARCH_OMAP15XX
225 if (cpu_is_omap15xx() && gpio < 16)
226 return 0;
227 #endif
228 #if defined(CONFIG_ARCH_OMAP16XX)
229 if ((cpu_is_omap16xx()) && gpio < 64)
230 return 0;
231 #endif
232 #ifdef CONFIG_ARCH_OMAP730
233 if (cpu_is_omap730() && gpio < 192)
234 return 0;
235 #endif
236 #ifdef CONFIG_ARCH_OMAP24XX
237 if (cpu_is_omap24xx() && gpio < 128)
238 return 0;
239 #endif
240 return -1;
241 }
242
243 static int check_gpio(int gpio)
244 {
245 if (unlikely(gpio_valid(gpio)) < 0) {
246 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
247 dump_stack();
248 return -1;
249 }
250 return 0;
251 }
252
253 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
254 {
255 void __iomem *reg = bank->base;
256 u32 l;
257
258 switch (bank->method) {
259 case METHOD_MPUIO:
260 reg += OMAP_MPUIO_IO_CNTL;
261 break;
262 case METHOD_GPIO_1510:
263 reg += OMAP1510_GPIO_DIR_CONTROL;
264 break;
265 case METHOD_GPIO_1610:
266 reg += OMAP1610_GPIO_DIRECTION;
267 break;
268 case METHOD_GPIO_730:
269 reg += OMAP730_GPIO_DIR_CONTROL;
270 break;
271 case METHOD_GPIO_24XX:
272 reg += OMAP24XX_GPIO_OE;
273 break;
274 }
275 l = __raw_readl(reg);
276 if (is_input)
277 l |= 1 << gpio;
278 else
279 l &= ~(1 << gpio);
280 __raw_writel(l, reg);
281 }
282
283 void omap_set_gpio_direction(int gpio, int is_input)
284 {
285 struct gpio_bank *bank;
286
287 if (check_gpio(gpio) < 0)
288 return;
289 bank = get_gpio_bank(gpio);
290 spin_lock(&bank->lock);
291 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
292 spin_unlock(&bank->lock);
293 }
294
295 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
296 {
297 void __iomem *reg = bank->base;
298 u32 l = 0;
299
300 switch (bank->method) {
301 case METHOD_MPUIO:
302 reg += OMAP_MPUIO_OUTPUT;
303 l = __raw_readl(reg);
304 if (enable)
305 l |= 1 << gpio;
306 else
307 l &= ~(1 << gpio);
308 break;
309 case METHOD_GPIO_1510:
310 reg += OMAP1510_GPIO_DATA_OUTPUT;
311 l = __raw_readl(reg);
312 if (enable)
313 l |= 1 << gpio;
314 else
315 l &= ~(1 << gpio);
316 break;
317 case METHOD_GPIO_1610:
318 if (enable)
319 reg += OMAP1610_GPIO_SET_DATAOUT;
320 else
321 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
322 l = 1 << gpio;
323 break;
324 case METHOD_GPIO_730:
325 reg += OMAP730_GPIO_DATA_OUTPUT;
326 l = __raw_readl(reg);
327 if (enable)
328 l |= 1 << gpio;
329 else
330 l &= ~(1 << gpio);
331 break;
332 case METHOD_GPIO_24XX:
333 if (enable)
334 reg += OMAP24XX_GPIO_SETDATAOUT;
335 else
336 reg += OMAP24XX_GPIO_CLEARDATAOUT;
337 l = 1 << gpio;
338 break;
339 default:
340 BUG();
341 return;
342 }
343 __raw_writel(l, reg);
344 }
345
346 void omap_set_gpio_dataout(int gpio, int enable)
347 {
348 struct gpio_bank *bank;
349
350 if (check_gpio(gpio) < 0)
351 return;
352 bank = get_gpio_bank(gpio);
353 spin_lock(&bank->lock);
354 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
355 spin_unlock(&bank->lock);
356 }
357
358 int omap_get_gpio_datain(int gpio)
359 {
360 struct gpio_bank *bank;
361 void __iomem *reg;
362
363 if (check_gpio(gpio) < 0)
364 return -1;
365 bank = get_gpio_bank(gpio);
366 reg = bank->base;
367 switch (bank->method) {
368 case METHOD_MPUIO:
369 reg += OMAP_MPUIO_INPUT_LATCH;
370 break;
371 case METHOD_GPIO_1510:
372 reg += OMAP1510_GPIO_DATA_INPUT;
373 break;
374 case METHOD_GPIO_1610:
375 reg += OMAP1610_GPIO_DATAIN;
376 break;
377 case METHOD_GPIO_730:
378 reg += OMAP730_GPIO_DATA_INPUT;
379 break;
380 case METHOD_GPIO_24XX:
381 reg += OMAP24XX_GPIO_DATAIN;
382 break;
383 default:
384 BUG();
385 return -1;
386 }
387 return (__raw_readl(reg)
388 & (1 << get_gpio_index(gpio))) != 0;
389 }
390
391 #define MOD_REG_BIT(reg, bit_mask, set) \
392 do { \
393 int l = __raw_readl(base + reg); \
394 if (set) l |= bit_mask; \
395 else l &= ~bit_mask; \
396 __raw_writel(l, base + reg); \
397 } while(0)
398
399 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
400 {
401 u32 gpio_bit = 1 << gpio;
402
403 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
404 trigger & __IRQT_LOWLVL);
405 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
406 trigger & __IRQT_HIGHLVL);
407 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
408 trigger & __IRQT_RISEDGE);
409 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
410 trigger & __IRQT_FALEDGE);
411 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
412 * triggering requested. */
413 }
414
415 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
416 {
417 void __iomem *reg = bank->base;
418 u32 l = 0;
419
420 switch (bank->method) {
421 case METHOD_MPUIO:
422 reg += OMAP_MPUIO_GPIO_INT_EDGE;
423 l = __raw_readl(reg);
424 if (trigger & __IRQT_RISEDGE)
425 l |= 1 << gpio;
426 else if (trigger & __IRQT_FALEDGE)
427 l &= ~(1 << gpio);
428 else
429 goto bad;
430 break;
431 case METHOD_GPIO_1510:
432 reg += OMAP1510_GPIO_INT_CONTROL;
433 l = __raw_readl(reg);
434 if (trigger & __IRQT_RISEDGE)
435 l |= 1 << gpio;
436 else if (trigger & __IRQT_FALEDGE)
437 l &= ~(1 << gpio);
438 else
439 goto bad;
440 break;
441 case METHOD_GPIO_1610:
442 if (gpio & 0x08)
443 reg += OMAP1610_GPIO_EDGE_CTRL2;
444 else
445 reg += OMAP1610_GPIO_EDGE_CTRL1;
446 gpio &= 0x07;
447 /* We allow only edge triggering, i.e. two lowest bits */
448 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
449 BUG();
450 l = __raw_readl(reg);
451 l &= ~(3 << (gpio << 1));
452 if (trigger & __IRQT_RISEDGE)
453 l |= 2 << (gpio << 1);
454 if (trigger & __IRQT_FALEDGE)
455 l |= 1 << (gpio << 1);
456 break;
457 case METHOD_GPIO_730:
458 reg += OMAP730_GPIO_INT_CONTROL;
459 l = __raw_readl(reg);
460 if (trigger & __IRQT_RISEDGE)
461 l |= 1 << gpio;
462 else if (trigger & __IRQT_FALEDGE)
463 l &= ~(1 << gpio);
464 else
465 goto bad;
466 break;
467 case METHOD_GPIO_24XX:
468 set_24xx_gpio_triggering(reg, gpio, trigger);
469 break;
470 default:
471 BUG();
472 goto bad;
473 }
474 __raw_writel(l, reg);
475 return 0;
476 bad:
477 return -EINVAL;
478 }
479
480 static int gpio_irq_type(unsigned irq, unsigned type)
481 {
482 struct gpio_bank *bank;
483 unsigned gpio;
484 int retval;
485
486 if (irq > IH_MPUIO_BASE)
487 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
488 else
489 gpio = irq - IH_GPIO_BASE;
490
491 if (check_gpio(gpio) < 0)
492 return -EINVAL;
493
494 if (type & IRQT_PROBE)
495 return -EINVAL;
496 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
497 return -EINVAL;
498
499 bank = get_gpio_bank(gpio);
500 spin_lock(&bank->lock);
501 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
502 spin_unlock(&bank->lock);
503 return retval;
504 }
505
506 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
507 {
508 void __iomem *reg = bank->base;
509
510 switch (bank->method) {
511 case METHOD_MPUIO:
512 /* MPUIO irqstatus is reset by reading the status register,
513 * so do nothing here */
514 return;
515 case METHOD_GPIO_1510:
516 reg += OMAP1510_GPIO_INT_STATUS;
517 break;
518 case METHOD_GPIO_1610:
519 reg += OMAP1610_GPIO_IRQSTATUS1;
520 break;
521 case METHOD_GPIO_730:
522 reg += OMAP730_GPIO_INT_STATUS;
523 break;
524 case METHOD_GPIO_24XX:
525 reg += OMAP24XX_GPIO_IRQSTATUS1;
526 break;
527 default:
528 BUG();
529 return;
530 }
531 __raw_writel(gpio_mask, reg);
532 }
533
534 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
535 {
536 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
537 }
538
539 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
540 {
541 void __iomem *reg = bank->base;
542 int inv = 0;
543 u32 l;
544 u32 mask;
545
546 switch (bank->method) {
547 case METHOD_MPUIO:
548 reg += OMAP_MPUIO_GPIO_MASKIT;
549 mask = 0xffff;
550 inv = 1;
551 break;
552 case METHOD_GPIO_1510:
553 reg += OMAP1510_GPIO_INT_MASK;
554 mask = 0xffff;
555 inv = 1;
556 break;
557 case METHOD_GPIO_1610:
558 reg += OMAP1610_GPIO_IRQENABLE1;
559 mask = 0xffff;
560 break;
561 case METHOD_GPIO_730:
562 reg += OMAP730_GPIO_INT_MASK;
563 mask = 0xffffffff;
564 inv = 1;
565 break;
566 case METHOD_GPIO_24XX:
567 reg += OMAP24XX_GPIO_IRQENABLE1;
568 mask = 0xffffffff;
569 break;
570 default:
571 BUG();
572 return 0;
573 }
574
575 l = __raw_readl(reg);
576 if (inv)
577 l = ~l;
578 l &= mask;
579 return l;
580 }
581
582 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
583 {
584 void __iomem *reg = bank->base;
585 u32 l;
586
587 switch (bank->method) {
588 case METHOD_MPUIO:
589 reg += OMAP_MPUIO_GPIO_MASKIT;
590 l = __raw_readl(reg);
591 if (enable)
592 l &= ~(gpio_mask);
593 else
594 l |= gpio_mask;
595 break;
596 case METHOD_GPIO_1510:
597 reg += OMAP1510_GPIO_INT_MASK;
598 l = __raw_readl(reg);
599 if (enable)
600 l &= ~(gpio_mask);
601 else
602 l |= gpio_mask;
603 break;
604 case METHOD_GPIO_1610:
605 if (enable)
606 reg += OMAP1610_GPIO_SET_IRQENABLE1;
607 else
608 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
609 l = gpio_mask;
610 break;
611 case METHOD_GPIO_730:
612 reg += OMAP730_GPIO_INT_MASK;
613 l = __raw_readl(reg);
614 if (enable)
615 l &= ~(gpio_mask);
616 else
617 l |= gpio_mask;
618 break;
619 case METHOD_GPIO_24XX:
620 if (enable)
621 reg += OMAP24XX_GPIO_SETIRQENABLE1;
622 else
623 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
624 l = gpio_mask;
625 break;
626 default:
627 BUG();
628 return;
629 }
630 __raw_writel(l, reg);
631 }
632
633 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
634 {
635 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
636 }
637
638 /*
639 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
640 * 1510 does not seem to have a wake-up register. If JTAG is connected
641 * to the target, system will wake up always on GPIO events. While
642 * system is running all registered GPIO interrupts need to have wake-up
643 * enabled. When system is suspended, only selected GPIO interrupts need
644 * to have wake-up enabled.
645 */
646 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
647 {
648 switch (bank->method) {
649 case METHOD_GPIO_1610:
650 case METHOD_GPIO_24XX:
651 spin_lock(&bank->lock);
652 if (enable)
653 bank->suspend_wakeup |= (1 << gpio);
654 else
655 bank->suspend_wakeup &= ~(1 << gpio);
656 spin_unlock(&bank->lock);
657 return 0;
658 default:
659 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
660 bank->method);
661 return -EINVAL;
662 }
663 }
664
665 static void _reset_gpio(struct gpio_bank *bank, int gpio)
666 {
667 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
668 _set_gpio_irqenable(bank, gpio, 0);
669 _clear_gpio_irqstatus(bank, gpio);
670 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
671 }
672
673 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
674 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
675 {
676 unsigned int gpio = irq - IH_GPIO_BASE;
677 struct gpio_bank *bank;
678 int retval;
679
680 if (check_gpio(gpio) < 0)
681 return -ENODEV;
682 bank = get_gpio_bank(gpio);
683 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
684
685 return retval;
686 }
687
688 int omap_request_gpio(int gpio)
689 {
690 struct gpio_bank *bank;
691
692 if (check_gpio(gpio) < 0)
693 return -EINVAL;
694
695 bank = get_gpio_bank(gpio);
696 spin_lock(&bank->lock);
697 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
698 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
699 dump_stack();
700 spin_unlock(&bank->lock);
701 return -1;
702 }
703 bank->reserved_map |= (1 << get_gpio_index(gpio));
704
705 /* Set trigger to none. You need to enable the desired trigger with
706 * request_irq() or set_irq_type().
707 */
708 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
709
710 #ifdef CONFIG_ARCH_OMAP15XX
711 if (bank->method == METHOD_GPIO_1510) {
712 void __iomem *reg;
713
714 /* Claim the pin for MPU */
715 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
716 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
717 }
718 #endif
719 #ifdef CONFIG_ARCH_OMAP16XX
720 if (bank->method == METHOD_GPIO_1610) {
721 /* Enable wake-up during idle for dynamic tick */
722 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
723 __raw_writel(1 << get_gpio_index(gpio), reg);
724 }
725 #endif
726 #ifdef CONFIG_ARCH_OMAP24XX
727 if (bank->method == METHOD_GPIO_24XX) {
728 /* Enable wake-up during idle for dynamic tick */
729 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
730 __raw_writel(1 << get_gpio_index(gpio), reg);
731 }
732 #endif
733 spin_unlock(&bank->lock);
734
735 return 0;
736 }
737
738 void omap_free_gpio(int gpio)
739 {
740 struct gpio_bank *bank;
741
742 if (check_gpio(gpio) < 0)
743 return;
744 bank = get_gpio_bank(gpio);
745 spin_lock(&bank->lock);
746 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
747 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
748 dump_stack();
749 spin_unlock(&bank->lock);
750 return;
751 }
752 #ifdef CONFIG_ARCH_OMAP16XX
753 if (bank->method == METHOD_GPIO_1610) {
754 /* Disable wake-up during idle for dynamic tick */
755 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
756 __raw_writel(1 << get_gpio_index(gpio), reg);
757 }
758 #endif
759 #ifdef CONFIG_ARCH_OMAP24XX
760 if (bank->method == METHOD_GPIO_24XX) {
761 /* Disable wake-up during idle for dynamic tick */
762 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
763 __raw_writel(1 << get_gpio_index(gpio), reg);
764 }
765 #endif
766 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
767 _reset_gpio(bank, gpio);
768 spin_unlock(&bank->lock);
769 }
770
771 /*
772 * We need to unmask the GPIO bank interrupt as soon as possible to
773 * avoid missing GPIO interrupts for other lines in the bank.
774 * Then we need to mask-read-clear-unmask the triggered GPIO lines
775 * in the bank to avoid missing nested interrupts for a GPIO line.
776 * If we wait to unmask individual GPIO lines in the bank after the
777 * line's interrupt handler has been run, we may miss some nested
778 * interrupts.
779 */
780 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
781 struct pt_regs *regs)
782 {
783 void __iomem *isr_reg = NULL;
784 u32 isr;
785 unsigned int gpio_irq;
786 struct gpio_bank *bank;
787 u32 retrigger = 0;
788 int unmasked = 0;
789
790 desc->chip->ack(irq);
791
792 bank = get_irq_data(irq);
793 if (bank->method == METHOD_MPUIO)
794 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
795 #ifdef CONFIG_ARCH_OMAP15XX
796 if (bank->method == METHOD_GPIO_1510)
797 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
798 #endif
799 #if defined(CONFIG_ARCH_OMAP16XX)
800 if (bank->method == METHOD_GPIO_1610)
801 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
802 #endif
803 #ifdef CONFIG_ARCH_OMAP730
804 if (bank->method == METHOD_GPIO_730)
805 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
806 #endif
807 #ifdef CONFIG_ARCH_OMAP24XX
808 if (bank->method == METHOD_GPIO_24XX)
809 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
810 #endif
811 while(1) {
812 u32 isr_saved, level_mask = 0;
813 u32 enabled;
814
815 enabled = _get_gpio_irqbank_mask(bank);
816 isr_saved = isr = __raw_readl(isr_reg) & enabled;
817
818 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
819 isr &= 0x0000ffff;
820
821 if (cpu_is_omap24xx()) {
822 level_mask =
823 __raw_readl(bank->base +
824 OMAP24XX_GPIO_LEVELDETECT0) |
825 __raw_readl(bank->base +
826 OMAP24XX_GPIO_LEVELDETECT1);
827 level_mask &= enabled;
828 }
829
830 /* clear edge sensitive interrupts before handler(s) are
831 called so that we don't miss any interrupt occurred while
832 executing them */
833 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
834 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
835 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
836
837 /* if there is only edge sensitive GPIO pin interrupts
838 configured, we could unmask GPIO bank interrupt immediately */
839 if (!level_mask && !unmasked) {
840 unmasked = 1;
841 desc->chip->unmask(irq);
842 }
843
844 isr |= retrigger;
845 retrigger = 0;
846 if (!isr)
847 break;
848
849 gpio_irq = bank->virtual_irq_start;
850 for (; isr != 0; isr >>= 1, gpio_irq++) {
851 struct irqdesc *d;
852 int irq_mask;
853 if (!(isr & 1))
854 continue;
855 d = irq_desc + gpio_irq;
856 /* Don't run the handler if it's already running
857 * or was disabled lazely.
858 */
859 if (unlikely((d->depth ||
860 (d->status & IRQ_INPROGRESS)))) {
861 irq_mask = 1 <<
862 (gpio_irq - bank->virtual_irq_start);
863 /* The unmasking will be done by
864 * enable_irq in case it is disabled or
865 * after returning from the handler if
866 * it's already running.
867 */
868 _enable_gpio_irqbank(bank, irq_mask, 0);
869 if (!d->depth) {
870 /* Level triggered interrupts
871 * won't ever be reentered
872 */
873 BUG_ON(level_mask & irq_mask);
874 d->status |= IRQ_PENDING;
875 }
876 continue;
877 }
878
879 desc_handle_irq(gpio_irq, d, regs);
880
881 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
882 irq_mask = 1 <<
883 (gpio_irq - bank->virtual_irq_start);
884 d->status &= ~IRQ_PENDING;
885 _enable_gpio_irqbank(bank, irq_mask, 1);
886 retrigger |= irq_mask;
887 }
888 }
889
890 if (cpu_is_omap24xx()) {
891 /* clear level sensitive interrupts after handler(s) */
892 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
893 _clear_gpio_irqbank(bank, isr_saved & level_mask);
894 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
895 }
896
897 }
898 /* if bank has any level sensitive GPIO pin interrupt
899 configured, we must unmask the bank interrupt only after
900 handler(s) are executed in order to avoid spurious bank
901 interrupt */
902 if (!unmasked)
903 desc->chip->unmask(irq);
904
905 }
906
907 static void gpio_irq_shutdown(unsigned int irq)
908 {
909 unsigned int gpio = irq - IH_GPIO_BASE;
910 struct gpio_bank *bank = get_gpio_bank(gpio);
911
912 _reset_gpio(bank, gpio);
913 }
914
915 static void gpio_ack_irq(unsigned int irq)
916 {
917 unsigned int gpio = irq - IH_GPIO_BASE;
918 struct gpio_bank *bank = get_gpio_bank(gpio);
919
920 _clear_gpio_irqstatus(bank, gpio);
921 }
922
923 static void gpio_mask_irq(unsigned int irq)
924 {
925 unsigned int gpio = irq - IH_GPIO_BASE;
926 struct gpio_bank *bank = get_gpio_bank(gpio);
927
928 _set_gpio_irqenable(bank, gpio, 0);
929 }
930
931 static void gpio_unmask_irq(unsigned int irq)
932 {
933 unsigned int gpio = irq - IH_GPIO_BASE;
934 unsigned int gpio_idx = get_gpio_index(gpio);
935 struct gpio_bank *bank = get_gpio_bank(gpio);
936
937 _set_gpio_irqenable(bank, gpio_idx, 1);
938 }
939
940 static void mpuio_ack_irq(unsigned int irq)
941 {
942 /* The ISR is reset automatically, so do nothing here. */
943 }
944
945 static void mpuio_mask_irq(unsigned int irq)
946 {
947 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
948 struct gpio_bank *bank = get_gpio_bank(gpio);
949
950 _set_gpio_irqenable(bank, gpio, 0);
951 }
952
953 static void mpuio_unmask_irq(unsigned int irq)
954 {
955 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
956 struct gpio_bank *bank = get_gpio_bank(gpio);
957
958 _set_gpio_irqenable(bank, gpio, 1);
959 }
960
961 static struct irq_chip gpio_irq_chip = {
962 .name = "GPIO",
963 .shutdown = gpio_irq_shutdown,
964 .ack = gpio_ack_irq,
965 .mask = gpio_mask_irq,
966 .unmask = gpio_unmask_irq,
967 .set_type = gpio_irq_type,
968 .set_wake = gpio_wake_enable,
969 };
970
971 static struct irq_chip mpuio_irq_chip = {
972 .name = "MPUIO",
973 .ack = mpuio_ack_irq,
974 .mask = mpuio_mask_irq,
975 .unmask = mpuio_unmask_irq
976 };
977
978 static int initialized;
979 static struct clk * gpio_ick;
980 static struct clk * gpio_fck;
981
982 static int __init _omap_gpio_init(void)
983 {
984 int i;
985 struct gpio_bank *bank;
986
987 initialized = 1;
988
989 if (cpu_is_omap15xx()) {
990 gpio_ick = clk_get(NULL, "arm_gpio_ck");
991 if (IS_ERR(gpio_ick))
992 printk("Could not get arm_gpio_ck\n");
993 else
994 clk_enable(gpio_ick);
995 }
996 if (cpu_is_omap24xx()) {
997 gpio_ick = clk_get(NULL, "gpios_ick");
998 if (IS_ERR(gpio_ick))
999 printk("Could not get gpios_ick\n");
1000 else
1001 clk_enable(gpio_ick);
1002 gpio_fck = clk_get(NULL, "gpios_fck");
1003 if (IS_ERR(gpio_ick))
1004 printk("Could not get gpios_fck\n");
1005 else
1006 clk_enable(gpio_fck);
1007 }
1008
1009 #ifdef CONFIG_ARCH_OMAP15XX
1010 if (cpu_is_omap15xx()) {
1011 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1012 gpio_bank_count = 2;
1013 gpio_bank = gpio_bank_1510;
1014 }
1015 #endif
1016 #if defined(CONFIG_ARCH_OMAP16XX)
1017 if (cpu_is_omap16xx()) {
1018 u32 rev;
1019
1020 gpio_bank_count = 5;
1021 gpio_bank = gpio_bank_1610;
1022 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1023 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1024 (rev >> 4) & 0x0f, rev & 0x0f);
1025 }
1026 #endif
1027 #ifdef CONFIG_ARCH_OMAP730
1028 if (cpu_is_omap730()) {
1029 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1030 gpio_bank_count = 7;
1031 gpio_bank = gpio_bank_730;
1032 }
1033 #endif
1034 #ifdef CONFIG_ARCH_OMAP24XX
1035 if (cpu_is_omap24xx()) {
1036 int rev;
1037
1038 gpio_bank_count = 4;
1039 gpio_bank = gpio_bank_24xx;
1040 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1041 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1042 (rev >> 4) & 0x0f, rev & 0x0f);
1043 }
1044 #endif
1045 for (i = 0; i < gpio_bank_count; i++) {
1046 int j, gpio_count = 16;
1047
1048 bank = &gpio_bank[i];
1049 bank->reserved_map = 0;
1050 bank->base = IO_ADDRESS(bank->base);
1051 spin_lock_init(&bank->lock);
1052 if (bank->method == METHOD_MPUIO) {
1053 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1054 }
1055 #ifdef CONFIG_ARCH_OMAP15XX
1056 if (bank->method == METHOD_GPIO_1510) {
1057 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1058 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1059 }
1060 #endif
1061 #if defined(CONFIG_ARCH_OMAP16XX)
1062 if (bank->method == METHOD_GPIO_1610) {
1063 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1064 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1065 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1066 }
1067 #endif
1068 #ifdef CONFIG_ARCH_OMAP730
1069 if (bank->method == METHOD_GPIO_730) {
1070 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1071 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1072
1073 gpio_count = 32; /* 730 has 32-bit GPIOs */
1074 }
1075 #endif
1076 #ifdef CONFIG_ARCH_OMAP24XX
1077 if (bank->method == METHOD_GPIO_24XX) {
1078 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1079 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1080
1081 gpio_count = 32;
1082 }
1083 #endif
1084 for (j = bank->virtual_irq_start;
1085 j < bank->virtual_irq_start + gpio_count; j++) {
1086 if (bank->method == METHOD_MPUIO)
1087 set_irq_chip(j, &mpuio_irq_chip);
1088 else
1089 set_irq_chip(j, &gpio_irq_chip);
1090 set_irq_handler(j, do_simple_IRQ);
1091 set_irq_flags(j, IRQF_VALID);
1092 }
1093 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1094 set_irq_data(bank->irq, bank);
1095 }
1096
1097 /* Enable system clock for GPIO module.
1098 * The CAM_CLK_CTRL *is* really the right place. */
1099 if (cpu_is_omap16xx())
1100 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1101
1102 return 0;
1103 }
1104
1105 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1106 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1107 {
1108 int i;
1109
1110 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1111 return 0;
1112
1113 for (i = 0; i < gpio_bank_count; i++) {
1114 struct gpio_bank *bank = &gpio_bank[i];
1115 void __iomem *wake_status;
1116 void __iomem *wake_clear;
1117 void __iomem *wake_set;
1118
1119 switch (bank->method) {
1120 case METHOD_GPIO_1610:
1121 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1122 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1123 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1124 break;
1125 case METHOD_GPIO_24XX:
1126 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1127 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1128 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1129 break;
1130 default:
1131 continue;
1132 }
1133
1134 spin_lock(&bank->lock);
1135 bank->saved_wakeup = __raw_readl(wake_status);
1136 __raw_writel(0xffffffff, wake_clear);
1137 __raw_writel(bank->suspend_wakeup, wake_set);
1138 spin_unlock(&bank->lock);
1139 }
1140
1141 return 0;
1142 }
1143
1144 static int omap_gpio_resume(struct sys_device *dev)
1145 {
1146 int i;
1147
1148 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1149 return 0;
1150
1151 for (i = 0; i < gpio_bank_count; i++) {
1152 struct gpio_bank *bank = &gpio_bank[i];
1153 void __iomem *wake_clear;
1154 void __iomem *wake_set;
1155
1156 switch (bank->method) {
1157 case METHOD_GPIO_1610:
1158 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1159 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1160 break;
1161 case METHOD_GPIO_24XX:
1162 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1163 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1164 break;
1165 default:
1166 continue;
1167 }
1168
1169 spin_lock(&bank->lock);
1170 __raw_writel(0xffffffff, wake_clear);
1171 __raw_writel(bank->saved_wakeup, wake_set);
1172 spin_unlock(&bank->lock);
1173 }
1174
1175 return 0;
1176 }
1177
1178 static struct sysdev_class omap_gpio_sysclass = {
1179 set_kset_name("gpio"),
1180 .suspend = omap_gpio_suspend,
1181 .resume = omap_gpio_resume,
1182 };
1183
1184 static struct sys_device omap_gpio_device = {
1185 .id = 0,
1186 .cls = &omap_gpio_sysclass,
1187 };
1188 #endif
1189
1190 /*
1191 * This may get called early from board specific init
1192 * for boards that have interrupts routed via FPGA.
1193 */
1194 int omap_gpio_init(void)
1195 {
1196 if (!initialized)
1197 return _omap_gpio_init();
1198 else
1199 return 0;
1200 }
1201
1202 static int __init omap_gpio_sysinit(void)
1203 {
1204 int ret = 0;
1205
1206 if (!initialized)
1207 ret = _omap_gpio_init();
1208
1209 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1210 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1211 if (ret == 0) {
1212 ret = sysdev_class_register(&omap_gpio_sysclass);
1213 if (ret == 0)
1214 ret = sysdev_register(&omap_gpio_device);
1215 }
1216 }
1217 #endif
1218
1219 return ret;
1220 }
1221
1222 EXPORT_SYMBOL(omap_request_gpio);
1223 EXPORT_SYMBOL(omap_free_gpio);
1224 EXPORT_SYMBOL(omap_set_gpio_direction);
1225 EXPORT_SYMBOL(omap_set_gpio_dataout);
1226 EXPORT_SYMBOL(omap_get_gpio_datain);
1227
1228 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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