arch/arm/plat-omap/include/plat/dmtimer.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/dmtimer.h
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * Platform device conversion and hwmod support.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  14  * PWM and clock framwork support by Timo Teras.
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * You should have received a copy of the  GNU General Public License along
  31  * with this program; if not, write  to the Free Software Foundation, Inc.,
  32  * 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #ifndef __ASM_ARCH_DMTIMER_H
  36 #define __ASM_ARCH_DMTIMER_H
  37
  38 /* clock sources */
  39 #define OMAP_TIMER_SRC_SYS_CLK                  0x00
  40 #define OMAP_TIMER_SRC_32_KHZ                   0x01
  41 #define OMAP_TIMER_SRC_EXT_CLK                  0x02
  42
  43 /* timer interrupt enable bits */
  44 #define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
  45 #define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
  46 #define OMAP_TIMER_INT_MATCH                    (1 << 0)
  47
  48 /* trigger types */
  49 #define OMAP_TIMER_TRIGGER_NONE                 0x00
  50 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
  51 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
  52
  53 /*
  54  * IP revision identifier so that Highlander IP
  55  * in OMAP4 can be distinguished.
  56  */
  57 #define OMAP_TIMER_IP_VERSION_1                        0x1
  58 struct omap_dm_timer;
  59 extern struct omap_dm_timer *gptimer_wakeup;
  60 struct clk;
  61
  62 int omap_dm_timer_init(void);
  63
  64 struct omap_dm_timer *omap_dm_timer_request(void);
  65 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
  66 void omap_dm_timer_free(struct omap_dm_timer *timer);
  67 void omap_dm_timer_enable(struct omap_dm_timer *timer);
  68 void omap_dm_timer_disable(struct omap_dm_timer *timer);
  69
  70 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
  71
  72 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
  73 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
  74
  75 void omap_dm_timer_trigger(struct omap_dm_timer *timer);
  76 void omap_dm_timer_start(struct omap_dm_timer *timer);
  77 void omap_dm_timer_stop(struct omap_dm_timer *timer);
  78
  79 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
  80 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
  81 void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
  82 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
  83 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
  84 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
  85
  86 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
  87
  88 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
  89 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
  90 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
  91 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
  92
  93 int omap_dm_timers_active(void);
  94
  95 /*
  96  * Do not use the defines below, they are not needed. They should be only
  97  * used by dmtimer.c and sys_timer related code.
  98  */
  99
 100 /* register offsets */
 101 #define _OMAP_TIMER_ID_OFFSET           0x00
 102 #define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
 103 #define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
 104 #define _OMAP_TIMER_STAT_OFFSET         0x18
 105 #define _OMAP_TIMER_INT_EN_OFFSET       0x1c
 106 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 107 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 108 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
 109 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
 110 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
 111 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
 112 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
 113 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
 114 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
 115 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
 116 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
 117 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
 118 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
 119 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
 120 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
 121 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
 122 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
 123 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
 124 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
 125 #define         WP_NONE                 0       /* no write pending bit */
 126 #define         WP_TCLR                 (1 << 0)
 127 #define         WP_TCRR                 (1 << 1)
 128 #define         WP_TLDR                 (1 << 2)
 129 #define         WP_TTGR                 (1 << 3)
 130 #define         WP_TMAR                 (1 << 4)
 131 #define         WP_TPIR                 (1 << 5)
 132 #define         WP_TNIR                 (1 << 6)
 133 #define         WP_TCVR                 (1 << 7)
 134 #define         WP_TOCR                 (1 << 8)
 135 #define         WP_TOWR                 (1 << 9)
 136 #define _OMAP_TIMER_MATCH_OFFSET        0x38
 137 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
 138 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
 139 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
 140 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
 141 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
 142 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
 143 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
 144 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
 145
 146 /* register offsets with the write pending bit encoded */
 147 #define WPSHIFT                                 16
 148
 149 #define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
 150                                                         | (WP_NONE << WPSHIFT))
 151
 152 #define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
 153                                                         | (WP_NONE << WPSHIFT))
 154
 155 #define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
 156                                                         | (WP_NONE << WPSHIFT))
 157
 158 #define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
 159                                                         | (WP_NONE << WPSHIFT))
 160
 161 #define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
 162                                                         | (WP_NONE << WPSHIFT))
 163
 164 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
 165                                                         | (WP_NONE << WPSHIFT))
 166
 167 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
 168                                                         | (WP_TCLR << WPSHIFT))
 169
 170 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
 171                                                         | (WP_TCRR << WPSHIFT))
 172
 173 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
 174                                                         | (WP_TLDR << WPSHIFT))
 175
 176 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
 177                                                         | (WP_TTGR << WPSHIFT))
 178
 179 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
 180                                                         | (WP_NONE << WPSHIFT))
 181
 182 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
 183                                                         | (WP_TMAR << WPSHIFT))
 184
 185 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
 186                                                         | (WP_NONE << WPSHIFT))
 187
 188 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
 189                                                         | (WP_NONE << WPSHIFT))
 190
 191 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
 192                                                         | (WP_NONE << WPSHIFT))
 193
 194 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
 195                                                         | (WP_TPIR << WPSHIFT))
 196
 197 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
 198                                                         | (WP_TNIR << WPSHIFT))
 199
 200 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
 201                                                         | (WP_TCVR << WPSHIFT))
 202
 203 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
 204                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
 205
 206 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
 207                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 208
 209 struct omap_dm_timer {
 210         unsigned long phys_base;
 211         int irq;
 212 #ifdef CONFIG_ARCH_OMAP2PLUS
 213         struct clk *iclk, *fclk;
 214 #endif
 215         void __iomem *io_base;
 216         unsigned reserved:1;
 217         unsigned enabled:1;
 218         unsigned posted:1;
 219 };
 220
 221 #endif /* __ASM_ARCH_DMTIMER_H */