arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-2012 Texas Instruments
  10  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/cpu.h>
  30
  31 #include "sram.h"
  32
  33 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
  34 #include "../mach-omap2/iomap.h"
  35 #include "../mach-omap2/prm2xxx_3xxx.h"
  36 #include "../mach-omap2/sdrc.h"
  37
  38 #define OMAP1_SRAM_PA           0x20000000
  39 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  40 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  41 #ifdef CONFIG_OMAP4_ERRATA_I688
  42 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  43 #else
  44 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  45 #endif
  46 #define OMAP5_SRAM_PA           0x40300000
  47
  48 #if defined(CONFIG_ARCH_OMAP2PLUS)
  49 #define SRAM_BOOTLOADER_SZ      0x00
  50 #else
  51 #define SRAM_BOOTLOADER_SZ      0x80
  52 #endif
  53
  54 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  55 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  56 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  57
  58 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  59 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  60 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  61 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  62 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  63
  64 #define GP_DEVICE               0x300
  65
  66 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  67
  68 static unsigned long omap_sram_start;
  69 static void __iomem *omap_sram_base;
  70 static unsigned long omap_sram_skip;
  71 static unsigned long omap_sram_size;
  72 static void __iomem *omap_sram_ceil;
  73
  74 /*
  75  * Depending on the target RAMFS firewall setup, the public usable amount of
  76  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  77  * device allows ARM11 but not other initiators for full size. This
  78  * functionality seems ok until some nice security API happens.
  79  */
  80 static int is_sram_locked(void)
  81 {
  82         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  83                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  84                 if (cpu_is_omap242x()) {
  85                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  86                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  87                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  88                 }
  89                 if (cpu_is_omap34xx()) {
  90                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  91                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  92                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  93                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  94                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  95                 }
  96                 return 0;
  97         } else
  98                 return 1; /* assume locked with no PPA or security driver */
  99 }
 100
 101 /*
 102  * The amount of SRAM depends on the core type.
 103  * Note that we cannot try to test for SRAM here because writes
 104  * to secure SRAM will hang the system. Also the SRAM is not
 105  * yet mapped at this point.
 106  */
 107 static void __init omap_detect_sram(void)
 108 {
 109         omap_sram_skip = SRAM_BOOTLOADER_SZ;
 110         if (cpu_class_is_omap2()) {
 111                 if (is_sram_locked()) {
 112                         if (cpu_is_omap34xx()) {
 113                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 114                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 115                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 116                                         omap_sram_size = 0x7000; /* 28K */
 117                                         omap_sram_skip += SZ_16K;
 118                                 } else {
 119                                         omap_sram_size = 0x8000; /* 32K */
 120                                 }
 121                         } else if (cpu_is_omap44xx()) {
 122                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 123                                 omap_sram_size = 0xa000; /* 40K */
 124                         } else if (soc_is_omap54xx()) {
 125                                 omap_sram_start = OMAP5_SRAM_PA;
 126                                 omap_sram_size = SZ_128K; /* 128KB */
 127                         } else {
 128                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 129                                 omap_sram_size = 0x800; /* 2K */
 130                         }
 131                 } else {
 132                         if (soc_is_am33xx()) {
 133                                 omap_sram_start = AM33XX_SRAM_PA;
 134                                 omap_sram_size = 0x10000; /* 64K */
 135                         } else if (cpu_is_omap34xx()) {
 136                                 omap_sram_start = OMAP3_SRAM_PA;
 137                                 omap_sram_size = 0x10000; /* 64K */
 138                         } else if (cpu_is_omap44xx()) {
 139                                 omap_sram_start = OMAP4_SRAM_PA;
 140                                 omap_sram_size = 0xe000; /* 56K */
 141                         } else if (soc_is_omap54xx()) {
 142                                 omap_sram_start = OMAP5_SRAM_PA;
 143                                 omap_sram_size = SZ_128K; /* 128KB */
 144                         } else {
 145                                 omap_sram_start = OMAP2_SRAM_PA;
 146                                 if (cpu_is_omap242x())
 147                                         omap_sram_size = 0xa0000; /* 640K */
 148                                 else if (cpu_is_omap243x())
 149                                         omap_sram_size = 0x10000; /* 64K */
 150                         }
 151                 }
 152         } else {
 153                 omap_sram_start = OMAP1_SRAM_PA;
 154
 155                 if (cpu_is_omap7xx())
 156                         omap_sram_size = 0x32000;       /* 200K */
 157                 else if (cpu_is_omap15xx())
 158                         omap_sram_size = 0x30000;       /* 192K */
 159                 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
 160                                 cpu_is_omap1621() || cpu_is_omap1710())
 161                         omap_sram_size = 0x4000;        /* 16K */
 162                 else {
 163                         pr_err("Could not detect SRAM size\n");
 164                         omap_sram_size = 0x4000;
 165                 }
 166         }
 167 }
 168
 169 /*
 170  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 171  */
 172 static void __init omap_map_sram(void)
 173 {
 174         int cached = 1;
 175
 176         if (omap_sram_size == 0)
 177                 return;
 178
 179 #ifdef CONFIG_OMAP4_ERRATA_I688
 180         if (cpu_is_omap44xx()) {
 181                 omap_sram_start += PAGE_SIZE;
 182                 omap_sram_size -= SZ_16K;
 183         }
 184 #endif
 185         if (cpu_is_omap34xx()) {
 186                 /*
 187                  * SRAM must be marked as non-cached on OMAP3 since the
 188                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 189                  * SDRAM controller disabled, and if it is marked cached,
 190                  * the ARM may attempt to write cache lines back to SDRAM
 191                  * which will cause the system to hang.
 192                  */
 193                 cached = 0;
 194         }
 195
 196         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
 197         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
 198                                                 cached);
 199         if (!omap_sram_base) {
 200                 pr_err("SRAM: Could not map\n");
 201                 return;
 202         }
 203
 204         omap_sram_ceil = omap_sram_base + omap_sram_size;
 205
 206         /*
 207          * Looks like we need to preserve some bootloader code at the
 208          * beginning of SRAM for jumping to flash for reboot to work...
 209          */
 210         memset_io(omap_sram_base + omap_sram_skip, 0,
 211                   omap_sram_size - omap_sram_skip);
 212 }
 213
 214 /*
 215  * Memory allocator for SRAM: calculates the new ceiling address
 216  * for pushing a function using the fncpy API.
 217  *
 218  * Note that fncpy requires the returned address to be aligned
 219  * to an 8-byte boundary.
 220  */
 221 void *omap_sram_push_address(unsigned long size)
 222 {
 223         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 224
 225         available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
 226
 227         if (size > available) {
 228                 pr_err("Not enough space in SRAM\n");
 229                 return NULL;
 230         }
 231
 232         new_ceil -= size;
 233         new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
 234         omap_sram_ceil = IOMEM(new_ceil);
 235
 236         return (void *)omap_sram_ceil;
 237 }
 238
 239 #ifdef CONFIG_ARCH_OMAP1
 240
 241 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 242
 243 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 244 {
 245         BUG_ON(!_omap_sram_reprogram_clock);
 246         /* On 730, bit 13 must always be 1 */
 247         if (cpu_is_omap7xx())
 248                 ckctl |= 0x2000;
 249         _omap_sram_reprogram_clock(dpllctl, ckctl);
 250 }
 251
 252 static int __init omap1_sram_init(void)
 253 {
 254         _omap_sram_reprogram_clock =
 255                         omap_sram_push(omap1_sram_reprogram_clock,
 256                                         omap1_sram_reprogram_clock_sz);
 257
 258         return 0;
 259 }
 260
 261 #else
 262 #define omap1_sram_init()       do {} while (0)
 263 #endif
 264
 265 #if defined(CONFIG_ARCH_OMAP2)
 266
 267 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 268                               u32 base_cs, u32 force_unlock);
 269
 270 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 271                    u32 base_cs, u32 force_unlock)
 272 {
 273         BUG_ON(!_omap2_sram_ddr_init);
 274         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 275                              base_cs, force_unlock);
 276 }
 277
 278 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 279                                           u32 mem_type);
 280
 281 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 282 {
 283         BUG_ON(!_omap2_sram_reprogram_sdrc);
 284         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 285 }
 286
 287 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 288
 289 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 290 {
 291         BUG_ON(!_omap2_set_prcm);
 292         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 293 }
 294 #endif
 295
 296 #ifdef CONFIG_SOC_OMAP2420
 297 static int __init omap242x_sram_init(void)
 298 {
 299         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 300                                         omap242x_sram_ddr_init_sz);
 301
 302         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 303                                             omap242x_sram_reprogram_sdrc_sz);
 304
 305         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 306                                          omap242x_sram_set_prcm_sz);
 307
 308         return 0;
 309 }
 310 #else
 311 static inline int omap242x_sram_init(void)
 312 {
 313         return 0;
 314 }
 315 #endif
 316
 317 #ifdef CONFIG_SOC_OMAP2430
 318 static int __init omap243x_sram_init(void)
 319 {
 320         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 321                                         omap243x_sram_ddr_init_sz);
 322
 323         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 324                                             omap243x_sram_reprogram_sdrc_sz);
 325
 326         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 327                                          omap243x_sram_set_prcm_sz);
 328
 329         return 0;
 330 }
 331 #else
 332 static inline int omap243x_sram_init(void)
 333 {
 334         return 0;
 335 }
 336 #endif
 337
 338 #ifdef CONFIG_ARCH_OMAP3
 339
 340 static u32 (*_omap3_sram_configure_core_dpll)(
 341                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 342                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 343                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 344                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 345                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 346
 347 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 348                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 349                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 350                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 351                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 352 {
 353         BUG_ON(!_omap3_sram_configure_core_dpll);
 354         return _omap3_sram_configure_core_dpll(
 355                         m2, unlock_dll, f, inc,
 356                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 357                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 358                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 359                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 360 }
 361
 362 void omap3_sram_restore_context(void)
 363 {
 364         omap_sram_ceil = omap_sram_base + omap_sram_size;
 365
 366         _omap3_sram_configure_core_dpll =
 367                 omap_sram_push(omap3_sram_configure_core_dpll,
 368                                omap3_sram_configure_core_dpll_sz);
 369         omap_push_sram_idle();
 370 }
 371
 372 static inline int omap34xx_sram_init(void)
 373 {
 374         omap3_sram_restore_context();
 375         return 0;
 376 }
 377 #else
 378 static inline int omap34xx_sram_init(void)
 379 {
 380         return 0;
 381 }
 382 #endif /* CONFIG_ARCH_OMAP3 */
 383
 384 static inline int am33xx_sram_init(void)
 385 {
 386         return 0;
 387 }
 388
 389 int __init omap_sram_init(void)
 390 {
 391         omap_detect_sram();
 392         omap_map_sram();
 393
 394         if (!(cpu_class_is_omap2()))
 395                 omap1_sram_init();
 396         else if (cpu_is_omap242x())
 397                 omap242x_sram_init();
 398         else if (cpu_is_omap2430())
 399                 omap243x_sram_init();
 400         else if (soc_is_am33xx())
 401                 am33xx_sram_init();
 402         else if (cpu_is_omap34xx())
 403                 omap34xx_sram_init();
 404
 405         return 0;
 406 }