arch/arm/plat-omap/timer32k.c

   1 /*
   2  * linux/arch/arm/plat-omap/timer32k.c
   3  *
   4  * OMAP 32K Timer
   5  *
   6  * Copyright (C) 2004 - 2005 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  * OMAP Dual-mode timer framework support by Timo Teras
  11  *
  12  * MPU timer code based on the older MPU timer code for OMAP
  13  * Copyright (C) 2000 RidgeRun, Inc.
  14  * Author: Greg Lonnon <glonnon@ridgerun.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * You should have received a copy of the  GNU General Public License along
  33  * with this program; if not, write  to the Free Software Foundation, Inc.,
  34  * 675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/sched.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/err.h>
  44 #include <linux/clk.h>
  45
  46 #include <asm/system.h>
  47 #include <asm/hardware.h>
  48 #include <asm/io.h>
  49 #include <asm/leds.h>
  50 #include <asm/irq.h>
  51 #include <asm/mach/irq.h>
  52 #include <asm/mach/time.h>
  53 #include <asm/arch/dmtimer.h>
  54
  55 struct sys_timer omap_timer;
  56
  57 /*
  58  * ---------------------------------------------------------------------------
  59  * 32KHz OS timer
  60  *
  61  * This currently works only on 16xx, as 1510 does not have the continuous
  62  * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
  63  * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
  64  * on 1510 would be possible, but the timer would not be as accurate as
  65  * with the 32KHz synchronized timer.
  66  * ---------------------------------------------------------------------------
  67  */
  68
  69 #if defined(CONFIG_ARCH_OMAP16XX)
  70 #define TIMER_32K_SYNCHRONIZED          0xfffbc410
  71 #elif defined(CONFIG_ARCH_OMAP24XX)
  72 #define TIMER_32K_SYNCHRONIZED          0x48004010
  73 #else
  74 #error OMAP 32KHz timer does not currently work on 15XX!
  75 #endif
  76
  77 /* 16xx specific defines */
  78 #define OMAP1_32K_TIMER_BASE            0xfffb9000
  79 #define OMAP1_32K_TIMER_CR              0x08
  80 #define OMAP1_32K_TIMER_TVR             0x00
  81 #define OMAP1_32K_TIMER_TCR             0x04
  82
  83 #define OMAP_32K_TICKS_PER_HZ           (32768 / HZ)
  84
  85 /*
  86  * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
  87  * so with HZ = 128, TVR = 255.
  88  */
  89 #define OMAP_32K_TIMER_TICK_PERIOD      ((32768 / HZ) - 1)
  90
  91 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
  92                                 (((nr_jiffies) * (clock_rate)) / HZ)
  93
  94 #if defined(CONFIG_ARCH_OMAP1)
  95
  96 static inline void omap_32k_timer_write(int val, int reg)
  97 {
  98         omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
  99 }
 100
 101 static inline unsigned long omap_32k_timer_read(int reg)
 102 {
 103         return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
 104 }
 105
 106 static inline void omap_32k_timer_start(unsigned long load_val)
 107 {
 108         if (!load_val)
 109                 load_val = 1;
 110         omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
 111         omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
 112 }
 113
 114 static inline void omap_32k_timer_stop(void)
 115 {
 116         omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
 117 }
 118
 119 #define omap_32k_timer_ack_irq()
 120
 121 #elif defined(CONFIG_ARCH_OMAP2)
 122
 123 static struct omap_dm_timer *gptimer;
 124
 125 static inline void omap_32k_timer_start(unsigned long load_val)
 126 {
 127         omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
 128         omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
 129         omap_dm_timer_start(gptimer);
 130 }
 131
 132 static inline void omap_32k_timer_stop(void)
 133 {
 134         omap_dm_timer_stop(gptimer);
 135 }
 136
 137 static inline void omap_32k_timer_ack_irq(void)
 138 {
 139         u32 status = omap_dm_timer_read_status(gptimer);
 140         omap_dm_timer_write_status(gptimer, status);
 141 }
 142
 143 #endif
 144
 145 /*
 146  * The 32KHz synchronized timer is an additional timer on 16xx.
 147  * It is always running.
 148  */
 149 static inline unsigned long omap_32k_sync_timer_read(void)
 150 {
 151         return omap_readl(TIMER_32K_SYNCHRONIZED);
 152 }
 153
 154 /*
 155  * Rounds down to nearest usec. Note that this will overflow for larger values.
 156  */
 157 static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
 158 {
 159         return (ticks_32k * 5*5*5*5*5*5) >> 9;
 160 }
 161
 162 /*
 163  * Rounds down to nearest nsec.
 164  */
 165 static inline unsigned long long
 166 omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
 167 {
 168         return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
 169 }
 170
 171 static unsigned long omap_32k_last_tick = 0;
 172
 173 /*
 174  * Returns elapsed usecs since last 32k timer interrupt
 175  */
 176 static unsigned long omap_32k_timer_gettimeoffset(void)
 177 {
 178         unsigned long now = omap_32k_sync_timer_read();
 179         return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
 180 }
 181
 182 /*
 183  * Returns current time from boot in nsecs. It's OK for this to wrap
 184  * around for now, as it's just a relative time stamp.
 185  */
 186 unsigned long long sched_clock(void)
 187 {
 188         return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
 189 }
 190
 191 /*
 192  * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
 193  * function is also called from other interrupts to remove latency
 194  * issues with dynamic tick. In the dynamic tick case, we need to lock
 195  * with irqsave.
 196  */
 197 static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id)
 198 {
 199         unsigned long now;
 200
 201         omap_32k_timer_ack_irq();
 202         now = omap_32k_sync_timer_read();
 203
 204         while ((signed long)(now - omap_32k_last_tick)
 205                                                 >= OMAP_32K_TICKS_PER_HZ) {
 206                 omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
 207                 timer_tick();
 208         }
 209
 210         /* Restart timer so we don't drift off due to modulo or dynamic tick.
 211          * By default we program the next timer to be continuous to avoid
 212          * latencies during high system load. During dynamic tick operation the
 213          * continuous timer can be overridden from pm_idle to be longer.
 214          */
 215         omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
 216
 217         return IRQ_HANDLED;
 218 }
 219
 220 static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id)
 221 {
 222         return _omap_32k_timer_interrupt(irq, dev_id);
 223 }
 224
 225 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 226 {
 227         unsigned long flags;
 228
 229         write_seqlock_irqsave(&xtime_lock, flags);
 230         _omap_32k_timer_interrupt(irq, dev_id);
 231         write_sequnlock_irqrestore(&xtime_lock, flags);
 232
 233         return IRQ_HANDLED;
 234 }
 235
 236 #ifdef CONFIG_NO_IDLE_HZ
 237 /*
 238  * Programs the next timer interrupt needed. Called when dynamic tick is
 239  * enabled, and to reprogram the ticks to skip from pm_idle. Note that
 240  * we can keep the timer continuous, and don't need to set it to run in
 241  * one-shot mode. This is because the timer will get reprogrammed again
 242  * after next interrupt.
 243  */
 244 void omap_32k_timer_reprogram(unsigned long next_tick)
 245 {
 246         unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
 247         unsigned long now = omap_32k_sync_timer_read();
 248         unsigned long idled = now - omap_32k_last_tick;
 249
 250         if (idled + 1 < ticks)
 251                 ticks -= idled;
 252         else
 253                 ticks = 1;
 254         omap_32k_timer_start(ticks);
 255 }
 256
 257 static struct irqaction omap_32k_timer_irq;
 258 extern struct timer_update_handler timer_update;
 259
 260 static int omap_32k_timer_enable_dyn_tick(void)
 261 {
 262         /* No need to reprogram timer, just use the next interrupt */
 263         return 0;
 264 }
 265
 266 static int omap_32k_timer_disable_dyn_tick(void)
 267 {
 268         omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
 269         return 0;
 270 }
 271
 272 static struct dyn_tick_timer omap_dyn_tick_timer = {
 273         .enable         = omap_32k_timer_enable_dyn_tick,
 274         .disable        = omap_32k_timer_disable_dyn_tick,
 275         .reprogram      = omap_32k_timer_reprogram,
 276         .handler        = omap_32k_timer_handler,
 277 };
 278 #endif  /* CONFIG_NO_IDLE_HZ */
 279
 280 static struct irqaction omap_32k_timer_irq = {
 281         .name           = "32KHz timer",
 282         .flags          = IRQF_DISABLED | IRQF_TIMER,
 283         .handler        = omap_32k_timer_interrupt,
 284 };
 285
 286 static __init void omap_init_32k_timer(void)
 287 {
 288 #ifdef CONFIG_NO_IDLE_HZ
 289         omap_timer.dyn_tick = &omap_dyn_tick_timer;
 290 #endif
 291
 292         if (cpu_class_is_omap1())
 293                 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
 294         omap_timer.offset  = omap_32k_timer_gettimeoffset;
 295         omap_32k_last_tick = omap_32k_sync_timer_read();
 296
 297 #ifdef CONFIG_ARCH_OMAP2
 298         /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
 299         if (cpu_is_omap24xx()) {
 300                 gptimer = omap_dm_timer_request_specific(1);
 301                 BUG_ON(gptimer == NULL);
 302
 303                 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
 304                 setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
 305                 omap_dm_timer_set_int_enable(gptimer,
 306                         OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
 307                         OMAP_TIMER_INT_MATCH);
 308         }
 309 #endif
 310
 311         omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
 312 }
 313
 314 /*
 315  * ---------------------------------------------------------------------------
 316  * Timer initialization
 317  * ---------------------------------------------------------------------------
 318  */
 319 static void __init omap_timer_init(void)
 320 {
 321 #ifdef CONFIG_OMAP_DM_TIMER
 322         omap_dm_timer_init();
 323 #endif
 324         omap_init_32k_timer();
 325 }
 326
 327 struct sys_timer omap_timer = {
 328         .init           = omap_timer_init,
 329         .offset         = NULL,         /* Initialized later */
 330 };