2 * arch/arm/plat-orion/gpio.c
4 * Marvell Orion SoC GPIO handling.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/bitops.h>
21 #include <linux/gpio.h>
22 #include <linux/leds.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <plat/orion-gpio.h>
29 * GPIO unit register offsets.
31 #define GPIO_OUT_OFF 0x0000
32 #define GPIO_IO_CONF_OFF 0x0004
33 #define GPIO_BLINK_EN_OFF 0x0008
34 #define GPIO_IN_POL_OFF 0x000c
35 #define GPIO_DATA_IN_OFF 0x0010
36 #define GPIO_EDGE_CAUSE_OFF 0x0014
37 #define GPIO_EDGE_MASK_OFF 0x0018
38 #define GPIO_LEVEL_MASK_OFF 0x001c
40 struct orion_gpio_chip
{
41 struct gpio_chip chip
;
44 unsigned long valid_input
;
45 unsigned long valid_output
;
47 int secondary_irq_base
;
48 struct irq_domain
*domain
;
51 static void __iomem
*GPIO_OUT(struct orion_gpio_chip
*ochip
)
53 return ochip
->base
+ GPIO_OUT_OFF
;
56 static void __iomem
*GPIO_IO_CONF(struct orion_gpio_chip
*ochip
)
58 return ochip
->base
+ GPIO_IO_CONF_OFF
;
61 static void __iomem
*GPIO_BLINK_EN(struct orion_gpio_chip
*ochip
)
63 return ochip
->base
+ GPIO_BLINK_EN_OFF
;
66 static void __iomem
*GPIO_IN_POL(struct orion_gpio_chip
*ochip
)
68 return ochip
->base
+ GPIO_IN_POL_OFF
;
71 static void __iomem
*GPIO_DATA_IN(struct orion_gpio_chip
*ochip
)
73 return ochip
->base
+ GPIO_DATA_IN_OFF
;
76 static void __iomem
*GPIO_EDGE_CAUSE(struct orion_gpio_chip
*ochip
)
78 return ochip
->base
+ GPIO_EDGE_CAUSE_OFF
;
81 static void __iomem
*GPIO_EDGE_MASK(struct orion_gpio_chip
*ochip
)
83 return ochip
->base
+ ochip
->mask_offset
+ GPIO_EDGE_MASK_OFF
;
86 static void __iomem
*GPIO_LEVEL_MASK(struct orion_gpio_chip
*ochip
)
88 return ochip
->base
+ ochip
->mask_offset
+ GPIO_LEVEL_MASK_OFF
;
92 static struct orion_gpio_chip orion_gpio_chips
[2];
93 static int orion_gpio_chip_count
;
96 __set_direction(struct orion_gpio_chip
*ochip
, unsigned pin
, int input
)
100 u
= readl(GPIO_IO_CONF(ochip
));
105 writel(u
, GPIO_IO_CONF(ochip
));
108 static void __set_level(struct orion_gpio_chip
*ochip
, unsigned pin
, int high
)
112 u
= readl(GPIO_OUT(ochip
));
117 writel(u
, GPIO_OUT(ochip
));
121 __set_blinking(struct orion_gpio_chip
*ochip
, unsigned pin
, int blink
)
125 u
= readl(GPIO_BLINK_EN(ochip
));
130 writel(u
, GPIO_BLINK_EN(ochip
));
134 orion_gpio_is_valid(struct orion_gpio_chip
*ochip
, unsigned pin
, int mode
)
136 if (pin
>= ochip
->chip
.ngpio
)
139 if ((mode
& GPIO_INPUT_OK
) && !test_bit(pin
, &ochip
->valid_input
))
142 if ((mode
& GPIO_OUTPUT_OK
) && !test_bit(pin
, &ochip
->valid_output
))
148 pr_debug("%s: invalid GPIO %d\n", __func__
, pin
);
155 static int orion_gpio_request(struct gpio_chip
*chip
, unsigned pin
)
157 struct orion_gpio_chip
*ochip
=
158 container_of(chip
, struct orion_gpio_chip
, chip
);
160 if (orion_gpio_is_valid(ochip
, pin
, GPIO_INPUT_OK
) ||
161 orion_gpio_is_valid(ochip
, pin
, GPIO_OUTPUT_OK
))
167 static int orion_gpio_direction_input(struct gpio_chip
*chip
, unsigned pin
)
169 struct orion_gpio_chip
*ochip
=
170 container_of(chip
, struct orion_gpio_chip
, chip
);
173 if (!orion_gpio_is_valid(ochip
, pin
, GPIO_INPUT_OK
))
176 spin_lock_irqsave(&ochip
->lock
, flags
);
177 __set_direction(ochip
, pin
, 1);
178 spin_unlock_irqrestore(&ochip
->lock
, flags
);
183 static int orion_gpio_get(struct gpio_chip
*chip
, unsigned pin
)
185 struct orion_gpio_chip
*ochip
=
186 container_of(chip
, struct orion_gpio_chip
, chip
);
189 if (readl(GPIO_IO_CONF(ochip
)) & (1 << pin
)) {
190 val
= readl(GPIO_DATA_IN(ochip
)) ^ readl(GPIO_IN_POL(ochip
));
192 val
= readl(GPIO_OUT(ochip
));
195 return (val
>> pin
) & 1;
199 orion_gpio_direction_output(struct gpio_chip
*chip
, unsigned pin
, int value
)
201 struct orion_gpio_chip
*ochip
=
202 container_of(chip
, struct orion_gpio_chip
, chip
);
205 if (!orion_gpio_is_valid(ochip
, pin
, GPIO_OUTPUT_OK
))
208 spin_lock_irqsave(&ochip
->lock
, flags
);
209 __set_blinking(ochip
, pin
, 0);
210 __set_level(ochip
, pin
, value
);
211 __set_direction(ochip
, pin
, 0);
212 spin_unlock_irqrestore(&ochip
->lock
, flags
);
217 static void orion_gpio_set(struct gpio_chip
*chip
, unsigned pin
, int value
)
219 struct orion_gpio_chip
*ochip
=
220 container_of(chip
, struct orion_gpio_chip
, chip
);
223 spin_lock_irqsave(&ochip
->lock
, flags
);
224 __set_level(ochip
, pin
, value
);
225 spin_unlock_irqrestore(&ochip
->lock
, flags
);
228 static int orion_gpio_to_irq(struct gpio_chip
*chip
, unsigned pin
)
230 struct orion_gpio_chip
*ochip
=
231 container_of(chip
, struct orion_gpio_chip
, chip
);
233 return irq_create_mapping(ochip
->domain
,
234 ochip
->secondary_irq_base
+ pin
);
238 * Orion-specific GPIO API extensions.
240 static struct orion_gpio_chip
*orion_gpio_chip_find(int pin
)
244 for (i
= 0; i
< orion_gpio_chip_count
; i
++) {
245 struct orion_gpio_chip
*ochip
= orion_gpio_chips
+ i
;
246 struct gpio_chip
*chip
= &ochip
->chip
;
248 if (pin
>= chip
->base
&& pin
< chip
->base
+ chip
->ngpio
)
255 void __init
orion_gpio_set_unused(unsigned pin
)
257 struct orion_gpio_chip
*ochip
= orion_gpio_chip_find(pin
);
262 pin
-= ochip
->chip
.base
;
264 /* Configure as output, drive low. */
265 __set_level(ochip
, pin
, 0);
266 __set_direction(ochip
, pin
, 0);
269 void __init
orion_gpio_set_valid(unsigned pin
, int mode
)
271 struct orion_gpio_chip
*ochip
= orion_gpio_chip_find(pin
);
276 pin
-= ochip
->chip
.base
;
279 mode
= GPIO_INPUT_OK
| GPIO_OUTPUT_OK
;
281 if (mode
& GPIO_INPUT_OK
)
282 __set_bit(pin
, &ochip
->valid_input
);
284 __clear_bit(pin
, &ochip
->valid_input
);
286 if (mode
& GPIO_OUTPUT_OK
)
287 __set_bit(pin
, &ochip
->valid_output
);
289 __clear_bit(pin
, &ochip
->valid_output
);
292 void orion_gpio_set_blink(unsigned pin
, int blink
)
294 struct orion_gpio_chip
*ochip
= orion_gpio_chip_find(pin
);
300 spin_lock_irqsave(&ochip
->lock
, flags
);
301 __set_level(ochip
, pin
& 31, 0);
302 __set_blinking(ochip
, pin
& 31, blink
);
303 spin_unlock_irqrestore(&ochip
->lock
, flags
);
305 EXPORT_SYMBOL(orion_gpio_set_blink
);
307 #define ORION_BLINK_HALF_PERIOD 100 /* ms */
309 int orion_gpio_led_blink_set(struct gpio_desc
*desc
, int state
,
310 unsigned long *delay_on
, unsigned long *delay_off
)
312 unsigned gpio
= desc_to_gpio(desc
);
314 if (delay_on
&& delay_off
&& !*delay_on
&& !*delay_off
)
315 *delay_on
= *delay_off
= ORION_BLINK_HALF_PERIOD
;
318 case GPIO_LED_NO_BLINK_LOW
:
319 case GPIO_LED_NO_BLINK_HIGH
:
320 orion_gpio_set_blink(gpio
, 0);
321 gpio_set_value(gpio
, state
);
324 orion_gpio_set_blink(gpio
, 1);
328 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set
);
331 /*****************************************************************************
334 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
335 * value of the line or the opposite value.
337 * Level IRQ handlers: DATA_IN is used directly as cause register.
338 * Interrupt are masked by LEVEL_MASK registers.
339 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
340 * Interrupt are masked by EDGE_MASK registers.
341 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
342 * the polarity to catch the next line transaction.
343 * This is a race condition that might not perfectly
344 * work on some use cases.
346 * Every eight GPIO lines are grouped (OR'ed) before going up to main
350 * data-in /--------| |-----| |----\
351 * -----| |----- ---- to main cause reg
352 * X \----------------| |----/
353 * polarity LEVEL mask
355 ****************************************************************************/
357 static int gpio_irq_set_type(struct irq_data
*d
, u32 type
)
359 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
360 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
361 struct orion_gpio_chip
*ochip
= gc
->private;
365 pin
= d
->hwirq
- ochip
->secondary_irq_base
;
367 u
= readl(GPIO_IO_CONF(ochip
)) & (1 << pin
);
372 type
&= IRQ_TYPE_SENSE_MASK
;
373 if (type
== IRQ_TYPE_NONE
)
376 /* Check if we need to change chip and handler */
377 if (!(ct
->type
& type
))
378 if (irq_setup_alt_chip(d
, type
))
382 * Configure interrupt polarity.
384 if (type
== IRQ_TYPE_EDGE_RISING
|| type
== IRQ_TYPE_LEVEL_HIGH
) {
385 u
= readl(GPIO_IN_POL(ochip
));
387 writel(u
, GPIO_IN_POL(ochip
));
388 } else if (type
== IRQ_TYPE_EDGE_FALLING
|| type
== IRQ_TYPE_LEVEL_LOW
) {
389 u
= readl(GPIO_IN_POL(ochip
));
391 writel(u
, GPIO_IN_POL(ochip
));
392 } else if (type
== IRQ_TYPE_EDGE_BOTH
) {
395 v
= readl(GPIO_IN_POL(ochip
)) ^ readl(GPIO_DATA_IN(ochip
));
398 * set initial polarity based on current input level
400 u
= readl(GPIO_IN_POL(ochip
));
402 u
|= 1 << pin
; /* falling */
404 u
&= ~(1 << pin
); /* rising */
405 writel(u
, GPIO_IN_POL(ochip
));
410 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
412 struct orion_gpio_chip
*ochip
= irq_get_handler_data(irq
);
419 cause
= readl(GPIO_DATA_IN(ochip
)) & readl(GPIO_LEVEL_MASK(ochip
));
420 cause
|= readl(GPIO_EDGE_CAUSE(ochip
)) & readl(GPIO_EDGE_MASK(ochip
));
422 for (i
= 0; i
< ochip
->chip
.ngpio
; i
++) {
425 irq
= ochip
->secondary_irq_base
+ i
;
427 if (!(cause
& (1 << i
)))
430 type
= irq_get_trigger_type(irq
);
431 if ((type
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
) {
432 /* Swap polarity (race with GPIO line) */
435 polarity
= readl(GPIO_IN_POL(ochip
));
437 writel(polarity
, GPIO_IN_POL(ochip
));
439 generic_handle_irq(irq
);
443 #ifdef CONFIG_DEBUG_FS
444 #include <linux/seq_file.h>
446 static void orion_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
448 struct orion_gpio_chip
*ochip
=
449 container_of(chip
, struct orion_gpio_chip
, chip
);
450 u32 out
, io_conf
, blink
, in_pol
, data_in
, cause
, edg_msk
, lvl_msk
;
453 out
= readl_relaxed(GPIO_OUT(ochip
));
454 io_conf
= readl_relaxed(GPIO_IO_CONF(ochip
));
455 blink
= readl_relaxed(GPIO_BLINK_EN(ochip
));
456 in_pol
= readl_relaxed(GPIO_IN_POL(ochip
));
457 data_in
= readl_relaxed(GPIO_DATA_IN(ochip
));
458 cause
= readl_relaxed(GPIO_EDGE_CAUSE(ochip
));
459 edg_msk
= readl_relaxed(GPIO_EDGE_MASK(ochip
));
460 lvl_msk
= readl_relaxed(GPIO_LEVEL_MASK(ochip
));
462 for (i
= 0; i
< chip
->ngpio
; i
++) {
467 label
= gpiochip_is_requested(chip
, i
);
472 is_out
= !(io_conf
& msk
);
474 seq_printf(s
, " gpio-%-3d (%-20.20s)", chip
->base
+ i
, label
);
477 seq_printf(s
, " out %s %s\n",
478 out
& msk
? "hi" : "lo",
479 blink
& msk
? "(blink )" : "");
483 seq_printf(s
, " in %s (act %s) - IRQ",
484 (data_in
^ in_pol
) & msk
? "hi" : "lo",
485 in_pol
& msk
? "lo" : "hi");
486 if (!((edg_msk
| lvl_msk
) & msk
)) {
487 seq_printf(s
, " disabled\n");
491 seq_printf(s
, " edge ");
493 seq_printf(s
, " level");
494 seq_printf(s
, " (%s)\n", cause
& msk
? "pending" : "clear ");
498 #define orion_gpio_dbg_show NULL
501 static void orion_gpio_unmask_irq(struct irq_data
*d
)
503 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
504 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
509 reg_val
= irq_reg_readl(gc
, ct
->regs
.mask
);
511 irq_reg_writel(gc
, reg_val
, ct
->regs
.mask
);
515 static void orion_gpio_mask_irq(struct irq_data
*d
)
517 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
518 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
523 reg_val
= irq_reg_readl(gc
, ct
->regs
.mask
);
525 irq_reg_writel(gc
, reg_val
, ct
->regs
.mask
);
529 void __init
orion_gpio_init(struct device_node
*np
,
530 int gpio_base
, int ngpio
,
531 void __iomem
*base
, int mask_offset
,
532 int secondary_irq_base
,
535 struct orion_gpio_chip
*ochip
;
536 struct irq_chip_generic
*gc
;
537 struct irq_chip_type
*ct
;
541 if (orion_gpio_chip_count
== ARRAY_SIZE(orion_gpio_chips
))
544 snprintf(gc_label
, sizeof(gc_label
), "orion_gpio%d",
545 orion_gpio_chip_count
);
547 ochip
= orion_gpio_chips
+ orion_gpio_chip_count
;
548 ochip
->chip
.label
= kstrdup(gc_label
, GFP_KERNEL
);
549 ochip
->chip
.request
= orion_gpio_request
;
550 ochip
->chip
.direction_input
= orion_gpio_direction_input
;
551 ochip
->chip
.get
= orion_gpio_get
;
552 ochip
->chip
.direction_output
= orion_gpio_direction_output
;
553 ochip
->chip
.set
= orion_gpio_set
;
554 ochip
->chip
.to_irq
= orion_gpio_to_irq
;
555 ochip
->chip
.base
= gpio_base
;
556 ochip
->chip
.ngpio
= ngpio
;
557 ochip
->chip
.can_sleep
= 0;
559 ochip
->chip
.of_node
= np
;
561 ochip
->chip
.dbg_show
= orion_gpio_dbg_show
;
563 spin_lock_init(&ochip
->lock
);
564 ochip
->base
= (void __iomem
*)base
;
565 ochip
->valid_input
= 0;
566 ochip
->valid_output
= 0;
567 ochip
->mask_offset
= mask_offset
;
568 ochip
->secondary_irq_base
= secondary_irq_base
;
570 gpiochip_add(&ochip
->chip
);
573 * Mask and clear GPIO interrupts.
575 writel(0, GPIO_EDGE_CAUSE(ochip
));
576 writel(0, GPIO_EDGE_MASK(ochip
));
577 writel(0, GPIO_LEVEL_MASK(ochip
));
579 /* Setup the interrupt handlers. Each chip can have up to 4
580 * interrupt handlers, with each handler dealing with 8 GPIO
583 for (i
= 0; i
< 4; i
++) {
585 irq_set_handler_data(irqs
[i
], ochip
);
586 irq_set_chained_handler(irqs
[i
], gpio_irq_handler
);
590 gc
= irq_alloc_generic_chip("orion_gpio_irq", 2,
592 ochip
->base
, handle_level_irq
);
595 ct
->regs
.mask
= ochip
->mask_offset
+ GPIO_LEVEL_MASK_OFF
;
596 ct
->type
= IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
;
597 ct
->chip
.irq_mask
= orion_gpio_mask_irq
;
598 ct
->chip
.irq_unmask
= orion_gpio_unmask_irq
;
599 ct
->chip
.irq_set_type
= gpio_irq_set_type
;
600 ct
->chip
.name
= ochip
->chip
.label
;
603 ct
->regs
.mask
= ochip
->mask_offset
+ GPIO_EDGE_MASK_OFF
;
604 ct
->regs
.ack
= GPIO_EDGE_CAUSE_OFF
;
605 ct
->type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
606 ct
->chip
.irq_ack
= irq_gc_ack_clr_bit
;
607 ct
->chip
.irq_mask
= orion_gpio_mask_irq
;
608 ct
->chip
.irq_unmask
= orion_gpio_unmask_irq
;
609 ct
->chip
.irq_set_type
= gpio_irq_set_type
;
610 ct
->handler
= handle_edge_irq
;
611 ct
->chip
.name
= ochip
->chip
.label
;
613 irq_setup_generic_chip(gc
, IRQ_MSK(ngpio
), IRQ_GC_INIT_MASK_CACHE
,
614 IRQ_NOREQUEST
, IRQ_LEVEL
| IRQ_NOPROBE
);
616 /* Setup irq domain on top of the generic chip. */
617 ochip
->domain
= irq_domain_add_legacy(np
,
619 ochip
->secondary_irq_base
,
620 ochip
->secondary_irq_base
,
621 &irq_domain_simple_ops
,
624 panic("%s: couldn't allocate irq domain (DT).\n",
627 orion_gpio_chip_count
++;