arch/arm/plat-s3c24xx/cpu.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * S3C24XX CPU Support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/delay.h>
  32 #include <linux/io.h>
  33
  34 #include <mach/hardware.h>
  35 #include <mach/regs-clock.h>
  36 #include <asm/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/map.h>
  41
  42 #include <mach/regs-gpio.h>
  43 #include <plat/regs-serial.h>
  44
  45 #include <plat/cpu.h>
  46 #include <plat/devs.h>
  47 #include <plat/clock.h>
  48 #include <plat/s3c2410.h>
  49 #include <plat/s3c2412.h>
  50 #include <plat/s3c2416.h>
  51 #include <plat/s3c244x.h>
  52 #include <plat/s3c2443.h>
  53
  54 /* table of supported CPUs */
  55
  56 static const char name_s3c2410[]  = "S3C2410";
  57 static const char name_s3c2412[]  = "S3C2412";
  58 static const char name_s3c2416[]  = "S3C2416/S3C2450";
  59 static const char name_s3c2440[]  = "S3C2440";
  60 static const char name_s3c2442[]  = "S3C2442";
  61 static const char name_s3c2442b[]  = "S3C2442B";
  62 static const char name_s3c2443[]  = "S3C2443";
  63 static const char name_s3c2410a[] = "S3C2410A";
  64 static const char name_s3c2440a[] = "S3C2440A";
  65
  66 static struct cpu_table cpu_ids[] __initdata = {
  67         {
  68                 .idcode         = 0x32410000,
  69                 .idmask         = 0xffffffff,
  70                 .map_io         = s3c2410_map_io,
  71                 .init_clocks    = s3c2410_init_clocks,
  72                 .init_uarts     = s3c2410_init_uarts,
  73                 .init           = s3c2410_init,
  74                 .name           = name_s3c2410
  75         },
  76         {
  77                 .idcode         = 0x32410002,
  78                 .idmask         = 0xffffffff,
  79                 .map_io         = s3c2410_map_io,
  80                 .init_clocks    = s3c2410_init_clocks,
  81                 .init_uarts     = s3c2410_init_uarts,
  82                 .init           = s3c2410a_init,
  83                 .name           = name_s3c2410a
  84         },
  85         {
  86                 .idcode         = 0x32440000,
  87                 .idmask         = 0xffffffff,
  88                 .map_io         = s3c2440_map_io,
  89                 .init_clocks    = s3c244x_init_clocks,
  90                 .init_uarts     = s3c244x_init_uarts,
  91                 .init           = s3c2440_init,
  92                 .name           = name_s3c2440
  93         },
  94         {
  95                 .idcode         = 0x32440001,
  96                 .idmask         = 0xffffffff,
  97                 .map_io         = s3c2440_map_io,
  98                 .init_clocks    = s3c244x_init_clocks,
  99                 .init_uarts     = s3c244x_init_uarts,
 100                 .init           = s3c2440_init,
 101                 .name           = name_s3c2440a
 102         },
 103         {
 104                 .idcode         = 0x32440aaa,
 105                 .idmask         = 0xffffffff,
 106                 .map_io         = s3c2442_map_io,
 107                 .init_clocks    = s3c244x_init_clocks,
 108                 .init_uarts     = s3c244x_init_uarts,
 109                 .init           = s3c2442_init,
 110                 .name           = name_s3c2442
 111         },
 112         {
 113                 .idcode         = 0x32440aab,
 114                 .idmask         = 0xffffffff,
 115                 .map_io         = s3c2442_map_io,
 116                 .init_clocks    = s3c244x_init_clocks,
 117                 .init_uarts     = s3c244x_init_uarts,
 118                 .init           = s3c2442_init,
 119                 .name           = name_s3c2442b
 120         },
 121         {
 122                 .idcode         = 0x32412001,
 123                 .idmask         = 0xffffffff,
 124                 .map_io         = s3c2412_map_io,
 125                 .init_clocks    = s3c2412_init_clocks,
 126                 .init_uarts     = s3c2412_init_uarts,
 127                 .init           = s3c2412_init,
 128                 .name           = name_s3c2412,
 129         },
 130         {                       /* a newer version of the s3c2412 */
 131                 .idcode         = 0x32412003,
 132                 .idmask         = 0xffffffff,
 133                 .map_io         = s3c2412_map_io,
 134                 .init_clocks    = s3c2412_init_clocks,
 135                 .init_uarts     = s3c2412_init_uarts,
 136                 .init           = s3c2412_init,
 137                 .name           = name_s3c2412,
 138         },
 139         {                       /* a strange version of the s3c2416 */
 140                 .idcode         = 0x32450003,
 141                 .idmask         = 0xffffffff,
 142                 .map_io         = s3c2416_map_io,
 143                 .init_clocks    = s3c2416_init_clocks,
 144                 .init_uarts     = s3c2416_init_uarts,
 145                 .init           = s3c2416_init,
 146                 .name           = name_s3c2416,
 147         },
 148         {
 149                 .idcode         = 0x32443001,
 150                 .idmask         = 0xffffffff,
 151                 .map_io         = s3c2443_map_io,
 152                 .init_clocks    = s3c2443_init_clocks,
 153                 .init_uarts     = s3c2443_init_uarts,
 154                 .init           = s3c2443_init,
 155                 .name           = name_s3c2443,
 156         },
 157 };
 158
 159 /* minimal IO mapping */
 160
 161 static struct map_desc s3c_iodesc[] __initdata = {
 162         IODESC_ENT(GPIO),
 163         IODESC_ENT(IRQ),
 164         IODESC_ENT(MEMCTRL),
 165         IODESC_ENT(UART)
 166 };
 167
 168 /* read cpu identificaiton code */
 169
 170 static unsigned long s3c24xx_read_idcode_v5(void)
 171 {
 172 #if defined(CONFIG_CPU_S3C2416)
 173         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 174
 175         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 176
 177         /* test for s3c2416 or similar device */
 178         if ((gs >> 16) == 0x3245)
 179                 return gs;
 180 #endif
 181
 182 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 183         return __raw_readl(S3C2412_GSTATUS1);
 184 #else
 185         return 1UL;     /* don't look like an 2400 */
 186 #endif
 187 }
 188
 189 static unsigned long s3c24xx_read_idcode_v4(void)
 190 {
 191         return __raw_readl(S3C2410_GSTATUS1);
 192 }
 193
 194 static void s3c24xx_default_idle(void)
 195 {
 196         unsigned long tmp;
 197         int i;
 198
 199         /* idle the system by using the idle mode which will wait for an
 200          * interrupt to happen before restarting the system.
 201          */
 202
 203         /* Warning: going into idle state upsets jtag scanning */
 204
 205         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 206                      S3C2410_CLKCON);
 207
 208         /* the samsung port seems to do a loop and then unset idle.. */
 209         for (i = 0; i < 50; i++)
 210                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 211
 212         /* this bit is not cleared on re-start... */
 213
 214         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 215                      S3C2410_CLKCON);
 216 }
 217
 218 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 219 {
 220         arm_pm_idle = s3c24xx_default_idle;
 221
 222         /* initialise the io descriptors we need for initialisation */
 223         iotable_init(mach_desc, size);
 224         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 225
 226         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 227                 samsung_cpu_id = s3c24xx_read_idcode_v5();
 228         } else {
 229                 samsung_cpu_id = s3c24xx_read_idcode_v4();
 230         }
 231         s3c24xx_init_cpu();
 232
 233         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 234 }