2 * linux/arch/arm/vfp/vfpsingle.c
4 * This code is derived in part from John R. Housers softfloat library, which
5 * carries the following notice:
7 * ===========================================================================
8 * This C source file is part of the SoftFloat IEC/IEEE Floating-point
9 * Arithmetic Package, Release 2.
11 * Written by John R. Hauser. This work was made possible in part by the
12 * International Computer Science Institute, located at Suite 600, 1947 Center
13 * Street, Berkeley, California 94704. Funding was partially provided by the
14 * National Science Foundation under grant MIP-9311980. The original version
15 * of this code was written as part of a project to build a fixed-point vector
16 * processor in collaboration with the University of California at Berkeley,
17 * overseen by Profs. Nelson Morgan and John Wawrzynek. More information
18 * is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
19 * arithmetic/softfloat.html'.
21 * THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
22 * has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
23 * TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
24 * PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
25 * AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
27 * Derivative works are acceptable, even for commercial purposes, so long as
28 * (1) they include prominent notice that the work is derivative, and (2) they
29 * include prominent notice akin to these three paragraphs for those parts of
30 * this code that are retained.
31 * ===========================================================================
33 #include <linux/kernel.h>
34 #include <linux/bitops.h>
36 #include <asm/div64.h>
37 #include <asm/ptrace.h>
43 static struct vfp_single vfp_single_default_qnan
= {
46 .significand
= VFP_SINGLE_SIGNIFICAND_QNAN
,
49 static void vfp_single_dump(const char *str
, struct vfp_single
*s
)
51 pr_debug("VFP: %s: sign=%d exponent=%d significand=%08x\n",
52 str
, s
->sign
!= 0, s
->exponent
, s
->significand
);
55 static void vfp_single_normalise_denormal(struct vfp_single
*vs
)
57 int bits
= 31 - fls(vs
->significand
);
59 vfp_single_dump("normalise_denormal: in", vs
);
62 vs
->exponent
-= bits
- 1;
63 vs
->significand
<<= bits
;
66 vfp_single_dump("normalise_denormal: out", vs
);
70 #define vfp_single_normaliseround(sd,vsd,fpscr,except,func) __vfp_single_normaliseround(sd,vsd,fpscr,except)
71 u32
__vfp_single_normaliseround(int sd
, struct vfp_single
*vs
, u32 fpscr
, u32 exceptions
)
73 u32
vfp_single_normaliseround(int sd
, struct vfp_single
*vs
, u32 fpscr
, u32 exceptions
, const char *func
)
76 u32 significand
, incr
, rmode
;
77 int exponent
, shift
, underflow
;
79 vfp_single_dump("pack: in", vs
);
82 * Infinities and NaNs are a special case.
84 if (vs
->exponent
== 255 && (vs
->significand
== 0 || exceptions
))
90 if (vs
->significand
== 0) {
95 exponent
= vs
->exponent
;
96 significand
= vs
->significand
;
99 * Normalise first. Note that we shift the significand up to
100 * bit 31, so we have VFP_SINGLE_LOW_BITS + 1 below the least
103 shift
= 32 - fls(significand
);
104 if (shift
< 32 && shift
) {
106 significand
<<= shift
;
110 vs
->exponent
= exponent
;
111 vs
->significand
= significand
;
112 vfp_single_dump("pack: normalised", vs
);
118 underflow
= exponent
< 0;
120 significand
= vfp_shiftright32jamming(significand
, -exponent
);
123 vs
->exponent
= exponent
;
124 vs
->significand
= significand
;
125 vfp_single_dump("pack: tiny number", vs
);
127 if (!(significand
& ((1 << (VFP_SINGLE_LOW_BITS
+ 1)) - 1)))
132 * Select rounding increment.
135 rmode
= fpscr
& FPSCR_RMODE_MASK
;
137 if (rmode
== FPSCR_ROUND_NEAREST
) {
138 incr
= 1 << VFP_SINGLE_LOW_BITS
;
139 if ((significand
& (1 << (VFP_SINGLE_LOW_BITS
+ 1))) == 0)
141 } else if (rmode
== FPSCR_ROUND_TOZERO
) {
143 } else if ((rmode
== FPSCR_ROUND_PLUSINF
) ^ (vs
->sign
!= 0))
144 incr
= (1 << (VFP_SINGLE_LOW_BITS
+ 1)) - 1;
146 pr_debug("VFP: rounding increment = 0x%08x\n", incr
);
149 * Is our rounding going to overflow?
151 if ((significand
+ incr
) < significand
) {
153 significand
= (significand
>> 1) | (significand
& 1);
156 vs
->exponent
= exponent
;
157 vs
->significand
= significand
;
158 vfp_single_dump("pack: overflow", vs
);
163 * If any of the low bits (which will be shifted out of the
164 * number) are non-zero, the result is inexact.
166 if (significand
& ((1 << (VFP_SINGLE_LOW_BITS
+ 1)) - 1))
167 exceptions
|= FPSCR_IXC
;
177 if (exponent
>= 254) {
178 exceptions
|= FPSCR_OFC
| FPSCR_IXC
;
181 vs
->significand
= 0x7fffffff;
183 vs
->exponent
= 255; /* infinity */
187 if (significand
>> (VFP_SINGLE_LOW_BITS
+ 1) == 0)
189 if (exponent
|| significand
> 0x80000000)
192 exceptions
|= FPSCR_UFC
;
193 vs
->exponent
= exponent
;
194 vs
->significand
= significand
>> 1;
198 vfp_single_dump("pack: final", vs
);
200 s32 d
= vfp_single_pack(vs
);
201 pr_debug("VFP: %s: d(s%d)=%08x exceptions=%08x\n", func
,
203 vfp_put_float(d
, sd
);
210 * Propagate the NaN, setting exceptions if it is signalling.
211 * 'n' is always a NaN. 'm' may be a number, NaN or infinity.
214 vfp_propagate_nan(struct vfp_single
*vsd
, struct vfp_single
*vsn
,
215 struct vfp_single
*vsm
, u32 fpscr
)
217 struct vfp_single
*nan
;
220 tn
= vfp_single_type(vsn
);
223 tm
= vfp_single_type(vsm
);
225 if (fpscr
& FPSCR_DEFAULT_NAN
)
227 * Default NaN mode - always returns a quiet NaN
229 nan
= &vfp_single_default_qnan
;
232 * Contemporary mode - select the first signalling
233 * NAN, or if neither are signalling, the first
236 if (tn
== VFP_SNAN
|| (tm
!= VFP_SNAN
&& tn
== VFP_QNAN
))
241 * Make the NaN quiet.
243 nan
->significand
|= VFP_SINGLE_SIGNIFICAND_QNAN
;
249 * If one was a signalling NAN, raise invalid operation.
251 return tn
== VFP_SNAN
|| tm
== VFP_SNAN
? FPSCR_IOC
: VFP_NAN_FLAG
;
256 * Extended operations
258 static u32
vfp_single_fabs(int sd
, int unused
, s32 m
, u32 fpscr
)
260 vfp_put_float(vfp_single_packed_abs(m
), sd
);
264 static u32
vfp_single_fcpy(int sd
, int unused
, s32 m
, u32 fpscr
)
266 vfp_put_float(m
, sd
);
270 static u32
vfp_single_fneg(int sd
, int unused
, s32 m
, u32 fpscr
)
272 vfp_put_float(vfp_single_packed_negate(m
), sd
);
276 static const u16 sqrt_oddadjust
[] = {
277 0x0004, 0x0022, 0x005d, 0x00b1, 0x011d, 0x019f, 0x0236, 0x02e0,
278 0x039c, 0x0468, 0x0545, 0x0631, 0x072b, 0x0832, 0x0946, 0x0a67
281 static const u16 sqrt_evenadjust
[] = {
282 0x0a2d, 0x08af, 0x075a, 0x0629, 0x051a, 0x0429, 0x0356, 0x029e,
283 0x0200, 0x0179, 0x0109, 0x00af, 0x0068, 0x0034, 0x0012, 0x0002
286 u32
vfp_estimate_sqrt_significand(u32 exponent
, u32 significand
)
291 if ((significand
& 0xc0000000) != 0x40000000) {
292 printk(KERN_WARNING
"VFP: estimate_sqrt: invalid significand\n");
295 a
= significand
<< 1;
296 index
= (a
>> 27) & 15;
298 z
= 0x4000 + (a
>> 17) - sqrt_oddadjust
[index
];
299 z
= ((a
/ z
) << 14) + (z
<< 15);
302 z
= 0x8000 + (a
>> 17) - sqrt_evenadjust
[index
];
304 z
= (z
>= 0x20000) ? 0xffff8000 : (z
<< 15);
309 u64 v
= (u64
)a
<< 31;
315 static u32
vfp_single_fsqrt(int sd
, int unused
, s32 m
, u32 fpscr
)
317 struct vfp_single vsm
, vsd
;
320 vfp_single_unpack(&vsm
, m
);
321 tm
= vfp_single_type(&vsm
);
322 if (tm
& (VFP_NAN
|VFP_INFINITY
)) {
323 struct vfp_single
*vsp
= &vsd
;
326 ret
= vfp_propagate_nan(vsp
, &vsm
, NULL
, fpscr
);
327 else if (vsm
.sign
== 0) {
333 vsp
= &vfp_single_default_qnan
;
336 vfp_put_float(vfp_single_pack(vsp
), sd
);
341 * sqrt(+/- 0) == +/- 0
347 * Normalise a denormalised number
349 if (tm
& VFP_DENORMAL
)
350 vfp_single_normalise_denormal(&vsm
);
358 vfp_single_dump("sqrt", &vsm
);
361 * Estimate the square root.
364 vsd
.exponent
= ((vsm
.exponent
- 127) >> 1) + 127;
365 vsd
.significand
= vfp_estimate_sqrt_significand(vsm
.exponent
, vsm
.significand
) + 2;
367 vfp_single_dump("sqrt estimate", &vsd
);
372 if ((vsd
.significand
& VFP_SINGLE_LOW_BITS_MASK
) <= 5) {
373 if (vsd
.significand
< 2) {
374 vsd
.significand
= 0xffffffff;
378 vsm
.significand
<<= !(vsm
.exponent
& 1);
379 term
= (u64
)vsd
.significand
* vsd
.significand
;
380 rem
= ((u64
)vsm
.significand
<< 32) - term
;
382 pr_debug("VFP: term=%016llx rem=%016llx\n", term
, rem
);
385 vsd
.significand
-= 1;
386 rem
+= ((u64
)vsd
.significand
<< 1) | 1;
388 vsd
.significand
|= rem
!= 0;
391 vsd
.significand
= vfp_shiftright32jamming(vsd
.significand
, 1);
393 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, 0, "fsqrt");
402 static u32
vfp_compare(int sd
, int signal_on_qnan
, s32 m
, u32 fpscr
)
407 d
= vfp_get_float(sd
);
408 if (vfp_single_packed_exponent(m
) == 255 && vfp_single_packed_mantissa(m
)) {
409 ret
|= FPSCR_C
| FPSCR_V
;
410 if (signal_on_qnan
|| !(vfp_single_packed_mantissa(m
) & (1 << (VFP_SINGLE_MANTISSA_BITS
- 1))))
412 * Signalling NaN, or signalling on quiet NaN
417 if (vfp_single_packed_exponent(d
) == 255 && vfp_single_packed_mantissa(d
)) {
418 ret
|= FPSCR_C
| FPSCR_V
;
419 if (signal_on_qnan
|| !(vfp_single_packed_mantissa(d
) & (1 << (VFP_SINGLE_MANTISSA_BITS
- 1))))
421 * Signalling NaN, or signalling on quiet NaN
427 if (d
== m
|| vfp_single_packed_abs(d
| m
) == 0) {
431 ret
|= FPSCR_Z
| FPSCR_C
;
432 } else if (vfp_single_packed_sign(d
^ m
)) {
436 if (vfp_single_packed_sign(d
))
438 * d is negative, so d < m
443 * d is positive, so d > m
446 } else if ((vfp_single_packed_sign(d
) != 0) ^ (d
< m
)) {
451 } else if ((vfp_single_packed_sign(d
) != 0) ^ (d
> m
)) {
461 static u32
vfp_single_fcmp(int sd
, int unused
, s32 m
, u32 fpscr
)
463 return vfp_compare(sd
, 0, m
, fpscr
);
466 static u32
vfp_single_fcmpe(int sd
, int unused
, s32 m
, u32 fpscr
)
468 return vfp_compare(sd
, 1, m
, fpscr
);
471 static u32
vfp_single_fcmpz(int sd
, int unused
, s32 m
, u32 fpscr
)
473 return vfp_compare(sd
, 0, 0, fpscr
);
476 static u32
vfp_single_fcmpez(int sd
, int unused
, s32 m
, u32 fpscr
)
478 return vfp_compare(sd
, 1, 0, fpscr
);
481 static u32
vfp_single_fcvtd(int dd
, int unused
, s32 m
, u32 fpscr
)
483 struct vfp_single vsm
;
484 struct vfp_double vdd
;
488 vfp_single_unpack(&vsm
, m
);
490 tm
= vfp_single_type(&vsm
);
493 * If we have a signalling NaN, signal invalid operation.
496 exceptions
= FPSCR_IOC
;
498 if (tm
& VFP_DENORMAL
)
499 vfp_single_normalise_denormal(&vsm
);
502 vdd
.significand
= (u64
)vsm
.significand
<< 32;
505 * If we have an infinity or NaN, the exponent must be 2047.
507 if (tm
& (VFP_INFINITY
|VFP_NAN
)) {
510 vdd
.significand
|= VFP_DOUBLE_SIGNIFICAND_QNAN
;
512 } else if (tm
& VFP_ZERO
)
515 vdd
.exponent
= vsm
.exponent
+ (1023 - 127);
517 return vfp_double_normaliseround(dd
, &vdd
, fpscr
, exceptions
, "fcvtd");
520 vfp_put_double(vfp_double_pack(&vdd
), dd
);
524 static u32
vfp_single_fuito(int sd
, int unused
, s32 m
, u32 fpscr
)
526 struct vfp_single vs
;
529 vs
.exponent
= 127 + 31 - 1;
530 vs
.significand
= (u32
)m
;
532 return vfp_single_normaliseround(sd
, &vs
, fpscr
, 0, "fuito");
535 static u32
vfp_single_fsito(int sd
, int unused
, s32 m
, u32 fpscr
)
537 struct vfp_single vs
;
539 vs
.sign
= (m
& 0x80000000) >> 16;
540 vs
.exponent
= 127 + 31 - 1;
541 vs
.significand
= vs
.sign
? -m
: m
;
543 return vfp_single_normaliseround(sd
, &vs
, fpscr
, 0, "fsito");
546 static u32
vfp_single_ftoui(int sd
, int unused
, s32 m
, u32 fpscr
)
548 struct vfp_single vsm
;
549 u32 d
, exceptions
= 0;
550 int rmode
= fpscr
& FPSCR_RMODE_MASK
;
553 vfp_single_unpack(&vsm
, m
);
554 vfp_single_dump("VSM", &vsm
);
557 * Do we have a denormalised number?
559 tm
= vfp_single_type(&vsm
);
560 if (tm
& VFP_DENORMAL
)
561 exceptions
|= FPSCR_IDC
;
566 if (vsm
.exponent
>= 127 + 32) {
567 d
= vsm
.sign
? 0 : 0xffffffff;
568 exceptions
= FPSCR_IOC
;
569 } else if (vsm
.exponent
>= 127 - 1) {
570 int shift
= 127 + 31 - vsm
.exponent
;
574 * 2^0 <= m < 2^32-2^8
576 d
= (vsm
.significand
<< 1) >> shift
;
577 rem
= vsm
.significand
<< (33 - shift
);
579 if (rmode
== FPSCR_ROUND_NEAREST
) {
583 } else if (rmode
== FPSCR_ROUND_TOZERO
) {
585 } else if ((rmode
== FPSCR_ROUND_PLUSINF
) ^ (vsm
.sign
!= 0)) {
589 if ((rem
+ incr
) < rem
) {
593 exceptions
|= FPSCR_IOC
;
598 exceptions
|= FPSCR_IOC
;
600 exceptions
|= FPSCR_IXC
;
603 if (vsm
.exponent
| vsm
.significand
) {
604 exceptions
|= FPSCR_IXC
;
605 if (rmode
== FPSCR_ROUND_PLUSINF
&& vsm
.sign
== 0)
607 else if (rmode
== FPSCR_ROUND_MINUSINF
&& vsm
.sign
) {
609 exceptions
|= FPSCR_IOC
;
614 pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd
, d
, exceptions
);
616 vfp_put_float(d
, sd
);
621 static u32
vfp_single_ftouiz(int sd
, int unused
, s32 m
, u32 fpscr
)
623 return vfp_single_ftoui(sd
, unused
, m
, FPSCR_ROUND_TOZERO
);
626 static u32
vfp_single_ftosi(int sd
, int unused
, s32 m
, u32 fpscr
)
628 struct vfp_single vsm
;
629 u32 d
, exceptions
= 0;
630 int rmode
= fpscr
& FPSCR_RMODE_MASK
;
633 vfp_single_unpack(&vsm
, m
);
634 vfp_single_dump("VSM", &vsm
);
637 * Do we have a denormalised number?
639 tm
= vfp_single_type(&vsm
);
640 if (vfp_single_type(&vsm
) & VFP_DENORMAL
)
641 exceptions
|= FPSCR_IDC
;
645 exceptions
|= FPSCR_IOC
;
646 } else if (vsm
.exponent
>= 127 + 32) {
648 * m >= 2^31-2^7: invalid
653 exceptions
|= FPSCR_IOC
;
654 } else if (vsm
.exponent
>= 127 - 1) {
655 int shift
= 127 + 31 - vsm
.exponent
;
658 /* 2^0 <= m <= 2^31-2^7 */
659 d
= (vsm
.significand
<< 1) >> shift
;
660 rem
= vsm
.significand
<< (33 - shift
);
662 if (rmode
== FPSCR_ROUND_NEAREST
) {
666 } else if (rmode
== FPSCR_ROUND_TOZERO
) {
668 } else if ((rmode
== FPSCR_ROUND_PLUSINF
) ^ (vsm
.sign
!= 0)) {
672 if ((rem
+ incr
) < rem
&& d
< 0xffffffff)
674 if (d
> 0x7fffffff + (vsm
.sign
!= 0)) {
675 d
= 0x7fffffff + (vsm
.sign
!= 0);
676 exceptions
|= FPSCR_IOC
;
678 exceptions
|= FPSCR_IXC
;
684 if (vsm
.exponent
| vsm
.significand
) {
685 exceptions
|= FPSCR_IXC
;
686 if (rmode
== FPSCR_ROUND_PLUSINF
&& vsm
.sign
== 0)
688 else if (rmode
== FPSCR_ROUND_MINUSINF
&& vsm
.sign
)
693 pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd
, d
, exceptions
);
695 vfp_put_float((s32
)d
, sd
);
700 static u32
vfp_single_ftosiz(int sd
, int unused
, s32 m
, u32 fpscr
)
702 return vfp_single_ftosi(sd
, unused
, m
, FPSCR_ROUND_TOZERO
);
705 static struct op fops_ext
[32] = {
706 [FEXT_TO_IDX(FEXT_FCPY
)] = { vfp_single_fcpy
, 0 },
707 [FEXT_TO_IDX(FEXT_FABS
)] = { vfp_single_fabs
, 0 },
708 [FEXT_TO_IDX(FEXT_FNEG
)] = { vfp_single_fneg
, 0 },
709 [FEXT_TO_IDX(FEXT_FSQRT
)] = { vfp_single_fsqrt
, 0 },
710 [FEXT_TO_IDX(FEXT_FCMP
)] = { vfp_single_fcmp
, OP_SCALAR
},
711 [FEXT_TO_IDX(FEXT_FCMPE
)] = { vfp_single_fcmpe
, OP_SCALAR
},
712 [FEXT_TO_IDX(FEXT_FCMPZ
)] = { vfp_single_fcmpz
, OP_SCALAR
},
713 [FEXT_TO_IDX(FEXT_FCMPEZ
)] = { vfp_single_fcmpez
, OP_SCALAR
},
714 [FEXT_TO_IDX(FEXT_FCVT
)] = { vfp_single_fcvtd
, OP_SCALAR
|OP_DD
},
715 [FEXT_TO_IDX(FEXT_FUITO
)] = { vfp_single_fuito
, OP_SCALAR
},
716 [FEXT_TO_IDX(FEXT_FSITO
)] = { vfp_single_fsito
, OP_SCALAR
},
717 [FEXT_TO_IDX(FEXT_FTOUI
)] = { vfp_single_ftoui
, OP_SCALAR
},
718 [FEXT_TO_IDX(FEXT_FTOUIZ
)] = { vfp_single_ftouiz
, OP_SCALAR
},
719 [FEXT_TO_IDX(FEXT_FTOSI
)] = { vfp_single_ftosi
, OP_SCALAR
},
720 [FEXT_TO_IDX(FEXT_FTOSIZ
)] = { vfp_single_ftosiz
, OP_SCALAR
},
728 vfp_single_fadd_nonnumber(struct vfp_single
*vsd
, struct vfp_single
*vsn
,
729 struct vfp_single
*vsm
, u32 fpscr
)
731 struct vfp_single
*vsp
;
735 tn
= vfp_single_type(vsn
);
736 tm
= vfp_single_type(vsm
);
738 if (tn
& tm
& VFP_INFINITY
) {
740 * Two infinities. Are they different signs?
742 if (vsn
->sign
^ vsm
->sign
) {
744 * different signs -> invalid
746 exceptions
= FPSCR_IOC
;
747 vsp
= &vfp_single_default_qnan
;
750 * same signs -> valid
754 } else if (tn
& VFP_INFINITY
&& tm
& VFP_NUMBER
) {
756 * One infinity and one number -> infinity
761 * 'n' is a NaN of some type
763 return vfp_propagate_nan(vsd
, vsn
, vsm
, fpscr
);
770 vfp_single_add(struct vfp_single
*vsd
, struct vfp_single
*vsn
,
771 struct vfp_single
*vsm
, u32 fpscr
)
775 if (vsn
->significand
& 0x80000000 ||
776 vsm
->significand
& 0x80000000) {
777 pr_info("VFP: bad FP values in %s\n", __func__
);
778 vfp_single_dump("VSN", vsn
);
779 vfp_single_dump("VSM", vsm
);
783 * Ensure that 'n' is the largest magnitude number. Note that
784 * if 'n' and 'm' have equal exponents, we do not swap them.
785 * This ensures that NaN propagation works correctly.
787 if (vsn
->exponent
< vsm
->exponent
) {
788 struct vfp_single
*t
= vsn
;
794 * Is 'n' an infinity or a NaN? Note that 'm' may be a number,
795 * infinity or a NaN here.
797 if (vsn
->exponent
== 255)
798 return vfp_single_fadd_nonnumber(vsd
, vsn
, vsm
, fpscr
);
801 * We have two proper numbers, where 'vsn' is the larger magnitude.
803 * Copy 'n' to 'd' before doing the arithmetic.
808 * Align both numbers.
810 exp_diff
= vsn
->exponent
- vsm
->exponent
;
811 m_sig
= vfp_shiftright32jamming(vsm
->significand
, exp_diff
);
814 * If the signs are different, we are really subtracting.
816 if (vsn
->sign
^ vsm
->sign
) {
817 m_sig
= vsn
->significand
- m_sig
;
818 if ((s32
)m_sig
< 0) {
819 vsd
->sign
= vfp_sign_negate(vsd
->sign
);
821 } else if (m_sig
== 0) {
822 vsd
->sign
= (fpscr
& FPSCR_RMODE_MASK
) ==
823 FPSCR_ROUND_MINUSINF
? 0x8000 : 0;
826 m_sig
= vsn
->significand
+ m_sig
;
828 vsd
->significand
= m_sig
;
834 vfp_single_multiply(struct vfp_single
*vsd
, struct vfp_single
*vsn
, struct vfp_single
*vsm
, u32 fpscr
)
836 vfp_single_dump("VSN", vsn
);
837 vfp_single_dump("VSM", vsm
);
840 * Ensure that 'n' is the largest magnitude number. Note that
841 * if 'n' and 'm' have equal exponents, we do not swap them.
842 * This ensures that NaN propagation works correctly.
844 if (vsn
->exponent
< vsm
->exponent
) {
845 struct vfp_single
*t
= vsn
;
848 pr_debug("VFP: swapping M <-> N\n");
851 vsd
->sign
= vsn
->sign
^ vsm
->sign
;
854 * If 'n' is an infinity or NaN, handle it. 'm' may be anything.
856 if (vsn
->exponent
== 255) {
857 if (vsn
->significand
|| (vsm
->exponent
== 255 && vsm
->significand
))
858 return vfp_propagate_nan(vsd
, vsn
, vsm
, fpscr
);
859 if ((vsm
->exponent
| vsm
->significand
) == 0) {
860 *vsd
= vfp_single_default_qnan
;
863 vsd
->exponent
= vsn
->exponent
;
864 vsd
->significand
= 0;
869 * If 'm' is zero, the result is always zero. In this case,
870 * 'n' may be zero or a number, but it doesn't matter which.
872 if ((vsm
->exponent
| vsm
->significand
) == 0) {
874 vsd
->significand
= 0;
879 * We add 2 to the destination exponent for the same reason as
880 * the addition case - though this time we have +1 from each
883 vsd
->exponent
= vsn
->exponent
+ vsm
->exponent
- 127 + 2;
884 vsd
->significand
= vfp_hi64to32jamming((u64
)vsn
->significand
* vsm
->significand
);
886 vfp_single_dump("VSD", vsd
);
890 #define NEG_MULTIPLY (1 << 0)
891 #define NEG_SUBTRACT (1 << 1)
894 vfp_single_multiply_accumulate(int sd
, int sn
, s32 m
, u32 fpscr
, u32 negate
, char *func
)
896 struct vfp_single vsd
, vsp
, vsn
, vsm
;
900 v
= vfp_get_float(sn
);
901 pr_debug("VFP: s%u = %08x\n", sn
, v
);
902 vfp_single_unpack(&vsn
, v
);
903 if (vsn
.exponent
== 0 && vsn
.significand
)
904 vfp_single_normalise_denormal(&vsn
);
906 vfp_single_unpack(&vsm
, m
);
907 if (vsm
.exponent
== 0 && vsm
.significand
)
908 vfp_single_normalise_denormal(&vsm
);
910 exceptions
= vfp_single_multiply(&vsp
, &vsn
, &vsm
, fpscr
);
911 if (negate
& NEG_MULTIPLY
)
912 vsp
.sign
= vfp_sign_negate(vsp
.sign
);
914 v
= vfp_get_float(sd
);
915 pr_debug("VFP: s%u = %08x\n", sd
, v
);
916 vfp_single_unpack(&vsn
, v
);
917 if (negate
& NEG_SUBTRACT
)
918 vsn
.sign
= vfp_sign_negate(vsn
.sign
);
920 exceptions
|= vfp_single_add(&vsd
, &vsn
, &vsp
, fpscr
);
922 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, func
);
926 * Standard operations
930 * sd = sd + (sn * sm)
932 static u32
vfp_single_fmac(int sd
, int sn
, s32 m
, u32 fpscr
)
934 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, 0, "fmac");
938 * sd = sd - (sn * sm)
940 static u32
vfp_single_fnmac(int sd
, int sn
, s32 m
, u32 fpscr
)
942 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, NEG_MULTIPLY
, "fnmac");
946 * sd = -sd + (sn * sm)
948 static u32
vfp_single_fmsc(int sd
, int sn
, s32 m
, u32 fpscr
)
950 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, NEG_SUBTRACT
, "fmsc");
954 * sd = -sd - (sn * sm)
956 static u32
vfp_single_fnmsc(int sd
, int sn
, s32 m
, u32 fpscr
)
958 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, NEG_SUBTRACT
| NEG_MULTIPLY
, "fnmsc");
964 static u32
vfp_single_fmul(int sd
, int sn
, s32 m
, u32 fpscr
)
966 struct vfp_single vsd
, vsn
, vsm
;
968 s32 n
= vfp_get_float(sn
);
970 pr_debug("VFP: s%u = %08x\n", sn
, n
);
972 vfp_single_unpack(&vsn
, n
);
973 if (vsn
.exponent
== 0 && vsn
.significand
)
974 vfp_single_normalise_denormal(&vsn
);
976 vfp_single_unpack(&vsm
, m
);
977 if (vsm
.exponent
== 0 && vsm
.significand
)
978 vfp_single_normalise_denormal(&vsm
);
980 exceptions
= vfp_single_multiply(&vsd
, &vsn
, &vsm
, fpscr
);
981 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, "fmul");
987 static u32
vfp_single_fnmul(int sd
, int sn
, s32 m
, u32 fpscr
)
989 struct vfp_single vsd
, vsn
, vsm
;
991 s32 n
= vfp_get_float(sn
);
993 pr_debug("VFP: s%u = %08x\n", sn
, n
);
995 vfp_single_unpack(&vsn
, n
);
996 if (vsn
.exponent
== 0 && vsn
.significand
)
997 vfp_single_normalise_denormal(&vsn
);
999 vfp_single_unpack(&vsm
, m
);
1000 if (vsm
.exponent
== 0 && vsm
.significand
)
1001 vfp_single_normalise_denormal(&vsm
);
1003 exceptions
= vfp_single_multiply(&vsd
, &vsn
, &vsm
, fpscr
);
1004 vsd
.sign
= vfp_sign_negate(vsd
.sign
);
1005 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, "fnmul");
1011 static u32
vfp_single_fadd(int sd
, int sn
, s32 m
, u32 fpscr
)
1013 struct vfp_single vsd
, vsn
, vsm
;
1015 s32 n
= vfp_get_float(sn
);
1017 pr_debug("VFP: s%u = %08x\n", sn
, n
);
1020 * Unpack and normalise denormals.
1022 vfp_single_unpack(&vsn
, n
);
1023 if (vsn
.exponent
== 0 && vsn
.significand
)
1024 vfp_single_normalise_denormal(&vsn
);
1026 vfp_single_unpack(&vsm
, m
);
1027 if (vsm
.exponent
== 0 && vsm
.significand
)
1028 vfp_single_normalise_denormal(&vsm
);
1030 exceptions
= vfp_single_add(&vsd
, &vsn
, &vsm
, fpscr
);
1032 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, "fadd");
1038 static u32
vfp_single_fsub(int sd
, int sn
, s32 m
, u32 fpscr
)
1041 * Subtraction is addition with one sign inverted.
1043 return vfp_single_fadd(sd
, sn
, vfp_single_packed_negate(m
), fpscr
);
1049 static u32
vfp_single_fdiv(int sd
, int sn
, s32 m
, u32 fpscr
)
1051 struct vfp_single vsd
, vsn
, vsm
;
1053 s32 n
= vfp_get_float(sn
);
1056 pr_debug("VFP: s%u = %08x\n", sn
, n
);
1058 vfp_single_unpack(&vsn
, n
);
1059 vfp_single_unpack(&vsm
, m
);
1061 vsd
.sign
= vsn
.sign
^ vsm
.sign
;
1063 tn
= vfp_single_type(&vsn
);
1064 tm
= vfp_single_type(&vsm
);
1079 * If n and m are infinity, the result is invalid
1080 * If n and m are zero, the result is invalid
1082 if (tm
& tn
& (VFP_INFINITY
|VFP_ZERO
))
1086 * If n is infinity, the result is infinity
1088 if (tn
& VFP_INFINITY
)
1092 * If m is zero, raise div0 exception
1098 * If m is infinity, or n is zero, the result is zero
1100 if (tm
& VFP_INFINITY
|| tn
& VFP_ZERO
)
1103 if (tn
& VFP_DENORMAL
)
1104 vfp_single_normalise_denormal(&vsn
);
1105 if (tm
& VFP_DENORMAL
)
1106 vfp_single_normalise_denormal(&vsm
);
1109 * Ok, we have two numbers, we can perform division.
1111 vsd
.exponent
= vsn
.exponent
- vsm
.exponent
+ 127 - 1;
1112 vsm
.significand
<<= 1;
1113 if (vsm
.significand
<= (2 * vsn
.significand
)) {
1114 vsn
.significand
>>= 1;
1118 u64 significand
= (u64
)vsn
.significand
<< 32;
1119 do_div(significand
, vsm
.significand
);
1120 vsd
.significand
= significand
;
1122 if ((vsd
.significand
& 0x3f) == 0)
1123 vsd
.significand
|= ((u64
)vsm
.significand
* vsd
.significand
!= (u64
)vsn
.significand
<< 32);
1125 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, 0, "fdiv");
1128 exceptions
= vfp_propagate_nan(&vsd
, &vsn
, &vsm
, fpscr
);
1130 vfp_put_float(vfp_single_pack(&vsd
), sd
);
1134 exceptions
= vfp_propagate_nan(&vsd
, &vsm
, &vsn
, fpscr
);
1139 vsd
.significand
= 0;
1143 exceptions
= FPSCR_DZC
;
1146 vsd
.significand
= 0;
1150 vfp_put_float(vfp_single_pack(&vfp_single_default_qnan
), sd
);
1154 static struct op fops
[16] = {
1155 [FOP_TO_IDX(FOP_FMAC
)] = { vfp_single_fmac
, 0 },
1156 [FOP_TO_IDX(FOP_FNMAC
)] = { vfp_single_fnmac
, 0 },
1157 [FOP_TO_IDX(FOP_FMSC
)] = { vfp_single_fmsc
, 0 },
1158 [FOP_TO_IDX(FOP_FNMSC
)] = { vfp_single_fnmsc
, 0 },
1159 [FOP_TO_IDX(FOP_FMUL
)] = { vfp_single_fmul
, 0 },
1160 [FOP_TO_IDX(FOP_FNMUL
)] = { vfp_single_fnmul
, 0 },
1161 [FOP_TO_IDX(FOP_FADD
)] = { vfp_single_fadd
, 0 },
1162 [FOP_TO_IDX(FOP_FSUB
)] = { vfp_single_fsub
, 0 },
1163 [FOP_TO_IDX(FOP_FDIV
)] = { vfp_single_fdiv
, 0 },
1166 #define FREG_BANK(x) ((x) & 0x18)
1167 #define FREG_IDX(x) ((x) & 7)
1169 u32
vfp_single_cpdo(u32 inst
, u32 fpscr
)
1171 u32 op
= inst
& FOP_MASK
;
1174 unsigned int sn
= vfp_get_sn(inst
);
1175 unsigned int sm
= vfp_get_sm(inst
);
1176 unsigned int vecitr
, veclen
, vecstride
;
1179 vecstride
= 1 + ((fpscr
& FPSCR_STRIDE_MASK
) == FPSCR_STRIDE_MASK
);
1181 fop
= (op
== FOP_EXT
) ? &fops_ext
[FEXT_TO_IDX(inst
)] : &fops
[FOP_TO_IDX(op
)];
1184 * fcvtsd takes a dN register number as destination, not sN.
1185 * Technically, if bit 0 of dd is set, this is an invalid
1186 * instruction. However, we ignore this for efficiency.
1187 * It also only operates on scalars.
1189 if (fop
->flags
& OP_DD
)
1190 dest
= vfp_get_dd(inst
);
1192 dest
= vfp_get_sd(inst
);
1195 * If destination bank is zero, vector length is always '1'.
1196 * ARM DDI0100F C5.1.3, C5.3.2.
1198 if ((fop
->flags
& OP_SCALAR
) || FREG_BANK(dest
) == 0)
1201 veclen
= fpscr
& FPSCR_LENGTH_MASK
;
1203 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride
,
1204 (veclen
>> FPSCR_LENGTH_BIT
) + 1);
1209 for (vecitr
= 0; vecitr
<= veclen
; vecitr
+= 1 << FPSCR_LENGTH_BIT
) {
1210 s32 m
= vfp_get_float(sm
);
1214 type
= fop
->flags
& OP_DD
? 'd' : 's';
1216 pr_debug("VFP: itr%d (%c%u) = op[%u] (s%u=%08x)\n",
1217 vecitr
>> FPSCR_LENGTH_BIT
, type
, dest
, sn
,
1220 pr_debug("VFP: itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)\n",
1221 vecitr
>> FPSCR_LENGTH_BIT
, type
, dest
, sn
,
1222 FOP_TO_IDX(op
), sm
, m
);
1224 except
= fop
->fn(dest
, sn
, m
, fpscr
);
1225 pr_debug("VFP: itr%d: exceptions=%08x\n",
1226 vecitr
>> FPSCR_LENGTH_BIT
, except
);
1228 exceptions
|= except
;
1231 * CHECK: It appears to be undefined whether we stop when
1232 * we encounter an exception. We continue.
1234 dest
= FREG_BANK(dest
) + ((FREG_IDX(dest
) + vecstride
) & 7);
1235 sn
= FREG_BANK(sn
) + ((FREG_IDX(sn
) + vecstride
) & 7);
1236 if (FREG_BANK(sm
) != 0)
1237 sm
= FREG_BANK(sm
) + ((FREG_IDX(sm
) + vecstride
) & 7);