Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm64 / Kconfig
1 config ARM64
2 def_bool y
3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
13 select ARM_AMBA
14 select ARM_ARCH_TIMER
15 select ARM_GIC
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
18 select ARM_GIC_V3
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
22 select COMMON_CLK
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_BITREVERSE
43 select HAVE_ARCH_JUMP_LABEL
44 select HAVE_ARCH_KGDB
45 select HAVE_ARCH_SECCOMP_FILTER
46 select HAVE_ARCH_TRACEHOOK
47 select HAVE_BPF_JIT
48 select HAVE_C_RECORDMCOUNT
49 select HAVE_CC_STACKPROTECTOR
50 select HAVE_CMPXCHG_DOUBLE
51 select HAVE_DEBUG_BUGVERBOSE
52 select HAVE_DEBUG_KMEMLEAK
53 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_ATTRS
55 select HAVE_DMA_CONTIGUOUS
56 select HAVE_DYNAMIC_FTRACE
57 select HAVE_EFFICIENT_UNALIGNED_ACCESS
58 select HAVE_FTRACE_MCOUNT_RECORD
59 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
61 select HAVE_GENERIC_DMA_COHERENT
62 select HAVE_HW_BREAKPOINT if PERF_EVENTS
63 select HAVE_MEMBLOCK
64 select HAVE_PATA_PLATFORM
65 select HAVE_PERF_EVENTS
66 select HAVE_PERF_REGS
67 select HAVE_PERF_USER_STACK_DUMP
68 select HAVE_RCU_TABLE_FREE
69 select HAVE_SYSCALL_TRACEPOINTS
70 select IRQ_DOMAIN
71 select MODULES_USE_ELF_RELA
72 select NO_BOOTMEM
73 select OF
74 select OF_EARLY_FLATTREE
75 select OF_RESERVED_MEM
76 select PERF_USE_VMALLOC
77 select POWER_RESET
78 select POWER_SUPPLY
79 select RTC_LIB
80 select SPARSE_IRQ
81 select SYSCTL_EXCEPTION_TRACE
82 select HAVE_CONTEXT_TRACKING
83 help
84 ARM 64-bit (AArch64) Linux support.
85
86 config 64BIT
87 def_bool y
88
89 config ARCH_PHYS_ADDR_T_64BIT
90 def_bool y
91
92 config MMU
93 def_bool y
94
95 config NO_IOPORT_MAP
96 def_bool y if !PCI
97
98 config STACKTRACE_SUPPORT
99 def_bool y
100
101 config LOCKDEP_SUPPORT
102 def_bool y
103
104 config TRACE_IRQFLAGS_SUPPORT
105 def_bool y
106
107 config RWSEM_XCHGADD_ALGORITHM
108 def_bool y
109
110 config GENERIC_HWEIGHT
111 def_bool y
112
113 config GENERIC_CSUM
114 def_bool y
115
116 config GENERIC_CALIBRATE_DELAY
117 def_bool y
118
119 config ZONE_DMA
120 def_bool y
121
122 config HAVE_GENERIC_RCU_GUP
123 def_bool y
124
125 config ARCH_DMA_ADDR_T_64BIT
126 def_bool y
127
128 config NEED_DMA_MAP_STATE
129 def_bool y
130
131 config NEED_SG_DMA_LENGTH
132 def_bool y
133
134 config SWIOTLB
135 def_bool y
136
137 config IOMMU_HELPER
138 def_bool SWIOTLB
139
140 config KERNEL_MODE_NEON
141 def_bool y
142
143 config FIX_EARLYCON_MEM
144 def_bool y
145
146 source "init/Kconfig"
147
148 source "kernel/Kconfig.freezer"
149
150 menu "Platform selection"
151
152 config ARCH_SEATTLE
153 bool "AMD Seattle SoC Family"
154 help
155 This enables support for AMD Seattle SOC Family
156
157 config ARCH_THUNDER
158 bool "Cavium Inc. Thunder SoC Family"
159 help
160 This enables support for Cavium's Thunder Family of SoCs.
161
162 config ARCH_VEXPRESS
163 bool "ARMv8 software model (Versatile Express)"
164 select ARCH_REQUIRE_GPIOLIB
165 select COMMON_CLK_VERSATILE
166 select POWER_RESET_VEXPRESS
167 select VEXPRESS_CONFIG
168 help
169 This enables support for the ARMv8 software model (Versatile
170 Express).
171
172 config ARCH_XGENE
173 bool "AppliedMicro X-Gene SOC Family"
174 help
175 This enables support for AppliedMicro X-Gene SOC Family
176
177 endmenu
178
179 menu "Bus support"
180
181 config PCI
182 bool "PCI support"
183 help
184 This feature enables support for PCI bus system. If you say Y
185 here, the kernel will include drivers and infrastructure code
186 to support PCI bus devices.
187
188 config PCI_DOMAINS
189 def_bool PCI
190
191 config PCI_DOMAINS_GENERIC
192 def_bool PCI
193
194 config PCI_SYSCALL
195 def_bool PCI
196
197 source "drivers/pci/Kconfig"
198 source "drivers/pci/pcie/Kconfig"
199 source "drivers/pci/hotplug/Kconfig"
200
201 endmenu
202
203 menu "Kernel Features"
204
205 menu "ARM errata workarounds via the alternatives framework"
206
207 config ARM64_ERRATUM_826319
208 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
209 default y
210 help
211 This option adds an alternative code sequence to work around ARM
212 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
213 AXI master interface and an L2 cache.
214
215 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
216 and is unable to accept a certain write via this interface, it will
217 not progress on read data presented on the read data channel and the
218 system can deadlock.
219
220 The workaround promotes data cache clean instructions to
221 data cache clean-and-invalidate.
222 Please note that this does not necessarily enable the workaround,
223 as it depends on the alternative framework, which will only patch
224 the kernel if an affected CPU is detected.
225
226 If unsure, say Y.
227
228 config ARM64_ERRATUM_827319
229 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
230 default y
231 help
232 This option adds an alternative code sequence to work around ARM
233 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
234 master interface and an L2 cache.
235
236 Under certain conditions this erratum can cause a clean line eviction
237 to occur at the same time as another transaction to the same address
238 on the AMBA 5 CHI interface, which can cause data corruption if the
239 interconnect reorders the two transactions.
240
241 The workaround promotes data cache clean instructions to
242 data cache clean-and-invalidate.
243 Please note that this does not necessarily enable the workaround,
244 as it depends on the alternative framework, which will only patch
245 the kernel if an affected CPU is detected.
246
247 If unsure, say Y.
248
249 config ARM64_ERRATUM_824069
250 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
251 default y
252 help
253 This option adds an alternative code sequence to work around ARM
254 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
255 to a coherent interconnect.
256
257 If a Cortex-A53 processor is executing a store or prefetch for
258 write instruction at the same time as a processor in another
259 cluster is executing a cache maintenance operation to the same
260 address, then this erratum might cause a clean cache line to be
261 incorrectly marked as dirty.
262
263 The workaround promotes data cache clean instructions to
264 data cache clean-and-invalidate.
265 Please note that this option does not necessarily enable the
266 workaround, as it depends on the alternative framework, which will
267 only patch the kernel if an affected CPU is detected.
268
269 If unsure, say Y.
270
271 config ARM64_ERRATUM_819472
272 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
273 default y
274 help
275 This option adds an alternative code sequence to work around ARM
276 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
277 present when it is connected to a coherent interconnect.
278
279 If the processor is executing a load and store exclusive sequence at
280 the same time as a processor in another cluster is executing a cache
281 maintenance operation to the same address, then this erratum might
282 cause data corruption.
283
284 The workaround promotes data cache clean instructions to
285 data cache clean-and-invalidate.
286 Please note that this does not necessarily enable the workaround,
287 as it depends on the alternative framework, which will only patch
288 the kernel if an affected CPU is detected.
289
290 If unsure, say Y.
291
292 config ARM64_ERRATUM_832075
293 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
294 default y
295 help
296 This option adds an alternative code sequence to work around ARM
297 erratum 832075 on Cortex-A57 parts up to r1p2.
298
299 Affected Cortex-A57 parts might deadlock when exclusive load/store
300 instructions to Write-Back memory are mixed with Device loads.
301
302 The workaround is to promote device loads to use Load-Acquire
303 semantics.
304 Please note that this does not necessarily enable the workaround,
305 as it depends on the alternative framework, which will only patch
306 the kernel if an affected CPU is detected.
307
308 If unsure, say Y.
309
310 endmenu
311
312
313 choice
314 prompt "Page size"
315 default ARM64_4K_PAGES
316 help
317 Page size (translation granule) configuration.
318
319 config ARM64_4K_PAGES
320 bool "4KB"
321 help
322 This feature enables 4KB pages support.
323
324 config ARM64_64K_PAGES
325 bool "64KB"
326 help
327 This feature enables 64KB pages support (4KB by default)
328 allowing only two levels of page tables and faster TLB
329 look-up. AArch32 emulation is not available when this feature
330 is enabled.
331
332 endchoice
333
334 choice
335 prompt "Virtual address space size"
336 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
337 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
338 help
339 Allows choosing one of multiple possible virtual address
340 space sizes. The level of translation table is determined by
341 a combination of page size and virtual address space size.
342
343 config ARM64_VA_BITS_39
344 bool "39-bit"
345 depends on ARM64_4K_PAGES
346
347 config ARM64_VA_BITS_42
348 bool "42-bit"
349 depends on ARM64_64K_PAGES
350
351 config ARM64_VA_BITS_48
352 bool "48-bit"
353
354 endchoice
355
356 config ARM64_VA_BITS
357 int
358 default 39 if ARM64_VA_BITS_39
359 default 42 if ARM64_VA_BITS_42
360 default 48 if ARM64_VA_BITS_48
361
362 config ARM64_PGTABLE_LEVELS
363 int
364 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
365 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
366 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
367 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
368
369 config CPU_BIG_ENDIAN
370 bool "Build big-endian kernel"
371 help
372 Say Y if you plan on running a kernel in big-endian mode.
373
374 config SMP
375 bool "Symmetric Multi-Processing"
376 help
377 This enables support for systems with more than one CPU. If
378 you say N here, the kernel will run on single and
379 multiprocessor machines, but will use only one CPU of a
380 multiprocessor machine. If you say Y here, the kernel will run
381 on many, but not all, single processor machines. On a single
382 processor machine, the kernel will run faster if you say N
383 here.
384
385 If you don't know what to do here, say N.
386
387 config SCHED_MC
388 bool "Multi-core scheduler support"
389 depends on SMP
390 help
391 Multi-core scheduler support improves the CPU scheduler's decision
392 making when dealing with multi-core CPU chips at a cost of slightly
393 increased overhead in some places. If unsure say N here.
394
395 config SCHED_SMT
396 bool "SMT scheduler support"
397 depends on SMP
398 help
399 Improves the CPU scheduler's decision making when dealing with
400 MultiThreading at a cost of slightly increased overhead in some
401 places. If unsure say N here.
402
403 config NR_CPUS
404 int "Maximum number of CPUs (2-64)"
405 range 2 64
406 depends on SMP
407 # These have to remain sorted largest to smallest
408 default "64"
409
410 config HOTPLUG_CPU
411 bool "Support for hot-pluggable CPUs"
412 depends on SMP
413 help
414 Say Y here to experiment with turning CPUs off and on. CPUs
415 can be controlled through /sys/devices/system/cpu.
416
417 source kernel/Kconfig.preempt
418
419 config HZ
420 int
421 default 100
422
423 config ARCH_HAS_HOLES_MEMORYMODEL
424 def_bool y if SPARSEMEM
425
426 config ARCH_SPARSEMEM_ENABLE
427 def_bool y
428 select SPARSEMEM_VMEMMAP_ENABLE
429
430 config ARCH_SPARSEMEM_DEFAULT
431 def_bool ARCH_SPARSEMEM_ENABLE
432
433 config ARCH_SELECT_MEMORY_MODEL
434 def_bool ARCH_SPARSEMEM_ENABLE
435
436 config HAVE_ARCH_PFN_VALID
437 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
438
439 config HW_PERF_EVENTS
440 bool "Enable hardware performance counter support for perf events"
441 depends on PERF_EVENTS
442 default y
443 help
444 Enable hardware performance counter support for perf events. If
445 disabled, perf events will use software events only.
446
447 config SYS_SUPPORTS_HUGETLBFS
448 def_bool y
449
450 config ARCH_WANT_GENERAL_HUGETLB
451 def_bool y
452
453 config ARCH_WANT_HUGE_PMD_SHARE
454 def_bool y if !ARM64_64K_PAGES
455
456 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
457 def_bool y
458
459 config ARCH_HAS_CACHE_LINE_SIZE
460 def_bool y
461
462 source "mm/Kconfig"
463
464 config SECCOMP
465 bool "Enable seccomp to safely compute untrusted bytecode"
466 ---help---
467 This kernel feature is useful for number crunching applications
468 that may need to compute untrusted bytecode during their
469 execution. By using pipes or other transports made available to
470 the process as file descriptors supporting the read/write
471 syscalls, it's possible to isolate those applications in
472 their own address space using seccomp. Once seccomp is
473 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
474 and the task is only allowed to execute a few safe syscalls
475 defined by each seccomp mode.
476
477 config XEN_DOM0
478 def_bool y
479 depends on XEN
480
481 config XEN
482 bool "Xen guest support on ARM64"
483 depends on ARM64 && OF
484 select SWIOTLB_XEN
485 help
486 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
487
488 config FORCE_MAX_ZONEORDER
489 int
490 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
491 default "11"
492
493 menuconfig ARMV8_DEPRECATED
494 bool "Emulate deprecated/obsolete ARMv8 instructions"
495 depends on COMPAT
496 help
497 Legacy software support may require certain instructions
498 that have been deprecated or obsoleted in the architecture.
499
500 Enable this config to enable selective emulation of these
501 features.
502
503 If unsure, say Y
504
505 if ARMV8_DEPRECATED
506
507 config SWP_EMULATION
508 bool "Emulate SWP/SWPB instructions"
509 help
510 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
511 they are always undefined. Say Y here to enable software
512 emulation of these instructions for userspace using LDXR/STXR.
513
514 In some older versions of glibc [<=2.8] SWP is used during futex
515 trylock() operations with the assumption that the code will not
516 be preempted. This invalid assumption may be more likely to fail
517 with SWP emulation enabled, leading to deadlock of the user
518 application.
519
520 NOTE: when accessing uncached shared regions, LDXR/STXR rely
521 on an external transaction monitoring block called a global
522 monitor to maintain update atomicity. If your system does not
523 implement a global monitor, this option can cause programs that
524 perform SWP operations to uncached memory to deadlock.
525
526 If unsure, say Y
527
528 config CP15_BARRIER_EMULATION
529 bool "Emulate CP15 Barrier instructions"
530 help
531 The CP15 barrier instructions - CP15ISB, CP15DSB, and
532 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
533 strongly recommended to use the ISB, DSB, and DMB
534 instructions instead.
535
536 Say Y here to enable software emulation of these
537 instructions for AArch32 userspace code. When this option is
538 enabled, CP15 barrier usage is traced which can help
539 identify software that needs updating.
540
541 If unsure, say Y
542
543 config SETEND_EMULATION
544 bool "Emulate SETEND instruction"
545 help
546 The SETEND instruction alters the data-endianness of the
547 AArch32 EL0, and is deprecated in ARMv8.
548
549 Say Y here to enable software emulation of the instruction
550 for AArch32 userspace code.
551
552 Note: All the cpus on the system must have mixed endian support at EL0
553 for this feature to be enabled. If a new CPU - which doesn't support mixed
554 endian - is hotplugged in after this feature has been enabled, there could
555 be unexpected results in the applications.
556
557 If unsure, say Y
558 endif
559
560 endmenu
561
562 menu "Boot options"
563
564 config CMDLINE
565 string "Default kernel command string"
566 default ""
567 help
568 Provide a set of default command-line options at build time by
569 entering them here. As a minimum, you should specify the the
570 root device (e.g. root=/dev/nfs).
571
572 config CMDLINE_FORCE
573 bool "Always use the default kernel command string"
574 help
575 Always use the default kernel command string, even if the boot
576 loader passes other arguments to the kernel.
577 This is useful if you cannot or don't want to change the
578 command-line options your boot loader passes to the kernel.
579
580 config EFI_STUB
581 bool
582
583 config EFI
584 bool "UEFI runtime support"
585 depends on OF && !CPU_BIG_ENDIAN
586 select LIBFDT
587 select UCS2_STRING
588 select EFI_PARAMS_FROM_FDT
589 select EFI_RUNTIME_WRAPPERS
590 select EFI_STUB
591 select EFI_ARMSTUB
592 default y
593 help
594 This option provides support for runtime services provided
595 by UEFI firmware (such as non-volatile variables, realtime
596 clock, and platform reset). A UEFI stub is also provided to
597 allow the kernel to be booted as an EFI application. This
598 is only useful on systems that have UEFI firmware.
599
600 config DMI
601 bool "Enable support for SMBIOS (DMI) tables"
602 depends on EFI
603 default y
604 help
605 This enables SMBIOS/DMI feature for systems.
606
607 This option is only useful on systems that have UEFI firmware.
608 However, even with this option, the resultant kernel should
609 continue to boot on existing non-UEFI platforms.
610
611 endmenu
612
613 menu "Userspace binary formats"
614
615 source "fs/Kconfig.binfmt"
616
617 config COMPAT
618 bool "Kernel support for 32-bit EL0"
619 depends on !ARM64_64K_PAGES
620 select COMPAT_BINFMT_ELF
621 select HAVE_UID16
622 select OLD_SIGSUSPEND3
623 select COMPAT_OLD_SIGACTION
624 help
625 This option enables support for a 32-bit EL0 running under a 64-bit
626 kernel at EL1. AArch32-specific components such as system calls,
627 the user helper functions, VFP support and the ptrace interface are
628 handled appropriately by the kernel.
629
630 If you want to execute 32-bit userspace applications, say Y.
631
632 config SYSVIPC_COMPAT
633 def_bool y
634 depends on COMPAT && SYSVIPC
635
636 endmenu
637
638 menu "Power management options"
639
640 source "kernel/power/Kconfig"
641
642 config ARCH_SUSPEND_POSSIBLE
643 def_bool y
644
645 endmenu
646
647 menu "CPU Power Management"
648
649 source "drivers/cpuidle/Kconfig"
650
651 source "drivers/cpufreq/Kconfig"
652
653 endmenu
654
655 source "net/Kconfig"
656
657 source "drivers/Kconfig"
658
659 source "drivers/firmware/Kconfig"
660
661 source "fs/Kconfig"
662
663 source "arch/arm64/kvm/Kconfig"
664
665 source "arch/arm64/Kconfig.debug"
666
667 source "security/Kconfig"
668
669 source "crypto/Kconfig"
670 if CRYPTO
671 source "arch/arm64/crypto/Kconfig"
672 endif
673
674 source "lib/Kconfig"
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