2 * Device Tree Source for the r8a7795 SoC
4 * Copyright (C) 2015 Renesas Electronics Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "renesas,r8a7795";
22 /* 1 core only at this point */
24 compatible = "arm,cortex-a57", "arm,armv8";
31 compatible = "fixed-clock";
33 /* This value must be overridden by the board */
34 clock-frequency = <0>;
38 compatible = "fixed-clock";
40 /* This value must be overridden by the board */
41 clock-frequency = <0>;
45 compatible = "simple-bus";
46 interrupt-parent = <&gic>;
51 gic: interrupt-controller@0xf1010000 {
52 compatible = "arm,gic-400";
53 #interrupt-cells = <3>;
56 reg = <0x0 0xf1010000 0 0x1000>,
57 <0x0 0xf1020000 0 0x2000>;
58 interrupts = <GIC_PPI 9
59 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
63 compatible = "arm,armv8-timer";
64 interrupts = <GIC_PPI 13
65 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
67 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
69 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
71 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
74 cpg: clock-controller@e6150000 {
75 compatible = "renesas,r8a7795-cpg-mssr";
76 reg = <0 0xe6150000 0 0x1000>;
77 clocks = <&extal_clk>, <&extalr_clk>;
78 clock-names = "extal", "extalr";
80 #power-domain-cells = <0>;