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Merge remote-tracking branches 'asoc/topic/ux500' and 'asoc/topic/wm8962' into asoc...
[deliverable/linux.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi
1 /*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 / {
51 compatible = "rockchip,rk3368";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 aliases {
57 ethernet0 = &gmac;
58 i2c0 = &i2c0;
59 i2c1 = &i2c1;
60 i2c2 = &i2c2;
61 i2c3 = &i2c3;
62 i2c4 = &i2c4;
63 i2c5 = &i2c5;
64 serial0 = &uart0;
65 serial1 = &uart1;
66 serial2 = &uart2;
67 serial3 = &uart3;
68 serial4 = &uart4;
69 spi0 = &spi0;
70 spi1 = &spi1;
71 spi2 = &spi2;
72 };
73
74 cpus {
75 #address-cells = <0x2>;
76 #size-cells = <0x0>;
77
78 cpu-map {
79 cluster0 {
80 core0 {
81 cpu = <&cpu_b0>;
82 };
83 core1 {
84 cpu = <&cpu_b1>;
85 };
86 core2 {
87 cpu = <&cpu_b2>;
88 };
89 core3 {
90 cpu = <&cpu_b3>;
91 };
92 };
93
94 cluster1 {
95 core0 {
96 cpu = <&cpu_l0>;
97 };
98 core1 {
99 cpu = <&cpu_l1>;
100 };
101 core2 {
102 cpu = <&cpu_l2>;
103 };
104 core3 {
105 cpu = <&cpu_l3>;
106 };
107 };
108 };
109
110 idle-states {
111 entry-method = "psci";
112
113 cpu_sleep: cpu-sleep-0 {
114 compatible = "arm,idle-state";
115 arm,psci-suspend-param = <0x1010000>;
116 entry-latency-us = <0x3fffffff>;
117 exit-latency-us = <0x40000000>;
118 min-residency-us = <0xffffffff>;
119 };
120 };
121
122 cpu_l0: cpu@0 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a53", "arm,armv8";
125 reg = <0x0 0x0>;
126 cpu-idle-states = <&cpu_sleep>;
127 enable-method = "psci";
128
129 #cooling-cells = <2>; /* min followed by max */
130 };
131
132 cpu_l1: cpu@1 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a53", "arm,armv8";
135 reg = <0x0 0x1>;
136 cpu-idle-states = <&cpu_sleep>;
137 enable-method = "psci";
138 };
139
140 cpu_l2: cpu@2 {
141 device_type = "cpu";
142 compatible = "arm,cortex-a53", "arm,armv8";
143 reg = <0x0 0x2>;
144 cpu-idle-states = <&cpu_sleep>;
145 enable-method = "psci";
146 };
147
148 cpu_l3: cpu@3 {
149 device_type = "cpu";
150 compatible = "arm,cortex-a53", "arm,armv8";
151 reg = <0x0 0x3>;
152 cpu-idle-states = <&cpu_sleep>;
153 enable-method = "psci";
154 };
155
156 cpu_b0: cpu@100 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a53", "arm,armv8";
159 reg = <0x0 0x100>;
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
162
163 #cooling-cells = <2>; /* min followed by max */
164 };
165
166 cpu_b1: cpu@101 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a53", "arm,armv8";
169 reg = <0x0 0x101>;
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
172 };
173
174 cpu_b2: cpu@102 {
175 device_type = "cpu";
176 compatible = "arm,cortex-a53", "arm,armv8";
177 reg = <0x0 0x102>;
178 cpu-idle-states = <&cpu_sleep>;
179 enable-method = "psci";
180 };
181
182 cpu_b3: cpu@103 {
183 device_type = "cpu";
184 compatible = "arm,cortex-a53", "arm,armv8";
185 reg = <0x0 0x103>;
186 cpu-idle-states = <&cpu_sleep>;
187 enable-method = "psci";
188 };
189 };
190
191 arm-pmu {
192 compatible = "arm,armv8-pmuv3";
193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
203 <&cpu_b2>, <&cpu_b3>;
204 };
205
206 psci {
207 compatible = "arm,psci-0.2";
208 method = "smc";
209 };
210
211 timer {
212 compatible = "arm,armv8-timer";
213 interrupts = <GIC_PPI 13
214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
215 <GIC_PPI 14
216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
217 <GIC_PPI 11
218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 10
220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
221 };
222
223 xin24m: oscillator {
224 compatible = "fixed-clock";
225 clock-frequency = <24000000>;
226 clock-output-names = "xin24m";
227 #clock-cells = <0>;
228 };
229
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
232 reg = <0x0 0xff0c0000 0x0 0x4000>;
233 clock-freq-min-max = <400000 150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 status = "disabled";
240 };
241
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
244 reg = <0x0 0xff0d0000 0x0 0x4000>;
245 clock-freq-min-max = <400000 150000000>;
246 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
247 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
253
254 emmc: dwmmc@ff0f0000 {
255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
256 reg = <0x0 0xff0f0000 0x0 0x4000>;
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
263 status = "disabled";
264 };
265
266 saradc: saradc@ff100000 {
267 compatible = "rockchip,saradc";
268 reg = <0x0 0xff100000 0x0 0x100>;
269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
270 #io-channel-cells = <1>;
271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
272 clock-names = "saradc", "apb_pclk";
273 resets = <&cru SRST_SARADC>;
274 reset-names = "saradc-apb";
275 status = "disabled";
276 };
277
278 spi0: spi@ff110000 {
279 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
280 reg = <0x0 0xff110000 0x0 0x1000>;
281 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
282 clock-names = "spiclk", "apb_pclk";
283 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
290
291 spi1: spi@ff120000 {
292 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
293 reg = <0x0 0xff120000 0x0 0x1000>;
294 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
295 clock-names = "spiclk", "apb_pclk";
296 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
303
304 spi2: spi@ff130000 {
305 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
306 reg = <0x0 0xff130000 0x0 0x1000>;
307 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
308 clock-names = "spiclk", "apb_pclk";
309 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
316
317 i2c1: i2c@ff140000 {
318 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
319 reg = <0x0 0xff140000 0x0 0x1000>;
320 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 clock-names = "i2c";
324 clocks = <&cru PCLK_I2C1>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c1_xfer>;
327 status = "disabled";
328 };
329
330 i2c3: i2c@ff150000 {
331 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
332 reg = <0x0 0xff150000 0x0 0x1000>;
333 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clock-names = "i2c";
337 clocks = <&cru PCLK_I2C3>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c3_xfer>;
340 status = "disabled";
341 };
342
343 i2c4: i2c@ff160000 {
344 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
345 reg = <0x0 0xff160000 0x0 0x1000>;
346 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 clock-names = "i2c";
350 clocks = <&cru PCLK_I2C4>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c4_xfer>;
353 status = "disabled";
354 };
355
356 i2c5: i2c@ff170000 {
357 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
358 reg = <0x0 0xff170000 0x0 0x1000>;
359 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 clock-names = "i2c";
363 clocks = <&cru PCLK_I2C5>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c5_xfer>;
366 status = "disabled";
367 };
368
369 uart0: serial@ff180000 {
370 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
371 reg = <0x0 0xff180000 0x0 0x100>;
372 clock-frequency = <24000000>;
373 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
374 clock-names = "baudclk", "apb_pclk";
375 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 status = "disabled";
379 };
380
381 uart1: serial@ff190000 {
382 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
383 reg = <0x0 0xff190000 0x0 0x100>;
384 clock-frequency = <24000000>;
385 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
386 clock-names = "baudclk", "apb_pclk";
387 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
388 reg-shift = <2>;
389 reg-io-width = <4>;
390 status = "disabled";
391 };
392
393 uart3: serial@ff1b0000 {
394 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
395 reg = <0x0 0xff1b0000 0x0 0x100>;
396 clock-frequency = <24000000>;
397 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
398 clock-names = "baudclk", "apb_pclk";
399 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
400 reg-shift = <2>;
401 reg-io-width = <4>;
402 status = "disabled";
403 };
404
405 uart4: serial@ff1c0000 {
406 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
407 reg = <0x0 0xff1c0000 0x0 0x100>;
408 clock-frequency = <24000000>;
409 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
410 clock-names = "baudclk", "apb_pclk";
411 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
412 reg-shift = <2>;
413 reg-io-width = <4>;
414 status = "disabled";
415 };
416
417 thermal-zones {
418 cpu {
419 polling-delay-passive = <100>; /* milliseconds */
420 polling-delay = <5000>; /* milliseconds */
421
422 thermal-sensors = <&tsadc 0>;
423
424 trips {
425 cpu_alert0: cpu_alert0 {
426 temperature = <75000>; /* millicelsius */
427 hysteresis = <2000>; /* millicelsius */
428 type = "passive";
429 };
430 cpu_alert1: cpu_alert1 {
431 temperature = <80000>; /* millicelsius */
432 hysteresis = <2000>; /* millicelsius */
433 type = "passive";
434 };
435 cpu_crit: cpu_crit {
436 temperature = <95000>; /* millicelsius */
437 hysteresis = <2000>; /* millicelsius */
438 type = "critical";
439 };
440 };
441
442 cooling-maps {
443 map0 {
444 trip = <&cpu_alert0>;
445 cooling-device =
446 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
447 };
448 map1 {
449 trip = <&cpu_alert1>;
450 cooling-device =
451 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
452 };
453 };
454 };
455
456 gpu {
457 polling-delay-passive = <100>; /* milliseconds */
458 polling-delay = <5000>; /* milliseconds */
459
460 thermal-sensors = <&tsadc 1>;
461
462 trips {
463 gpu_alert0: gpu_alert0 {
464 temperature = <80000>; /* millicelsius */
465 hysteresis = <2000>; /* millicelsius */
466 type = "passive";
467 };
468 gpu_crit: gpu_crit {
469 temperature = <115000>; /* millicelsius */
470 hysteresis = <2000>; /* millicelsius */
471 type = "critical";
472 };
473 };
474
475 cooling-maps {
476 map0 {
477 trip = <&gpu_alert0>;
478 cooling-device =
479 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
480 };
481 };
482 };
483 };
484
485 tsadc: tsadc@ff280000 {
486 compatible = "rockchip,rk3368-tsadc";
487 reg = <0x0 0xff280000 0x0 0x100>;
488 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
490 clock-names = "tsadc", "apb_pclk";
491 resets = <&cru SRST_TSADC>;
492 reset-names = "tsadc-apb";
493 pinctrl-names = "init", "default", "sleep";
494 pinctrl-0 = <&otp_gpio>;
495 pinctrl-1 = <&otp_out>;
496 pinctrl-2 = <&otp_gpio>;
497 #thermal-sensor-cells = <1>;
498 rockchip,hw-tshut-temp = <95000>;
499 status = "disabled";
500 };
501
502 gmac: ethernet@ff290000 {
503 compatible = "rockchip,rk3368-gmac";
504 reg = <0x0 0xff290000 0x0 0x10000>;
505 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
506 interrupt-names = "macirq";
507 rockchip,grf = <&grf>;
508 clocks = <&cru SCLK_MAC>,
509 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
510 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
511 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
512 clock-names = "stmmaceth",
513 "mac_clk_rx", "mac_clk_tx",
514 "clk_mac_ref", "clk_mac_refout",
515 "aclk_mac", "pclk_mac";
516 status = "disabled";
517 };
518
519 usb_host0_ehci: usb@ff500000 {
520 compatible = "generic-ehci";
521 reg = <0x0 0xff500000 0x0 0x100>;
522 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cru HCLK_HOST0>;
524 clock-names = "usbhost";
525 status = "disabled";
526 };
527
528 usb_otg: usb@ff580000 {
529 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
530 "snps,dwc2";
531 reg = <0x0 0xff580000 0x0 0x40000>;
532 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru HCLK_OTG0>;
534 clock-names = "otg";
535 dr_mode = "otg";
536 g-np-tx-fifo-size = <16>;
537 g-rx-fifo-size = <275>;
538 g-tx-fifo-size = <256 128 128 64 64 32>;
539 g-use-dma;
540 status = "disabled";
541 };
542
543 i2c0: i2c@ff650000 {
544 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
545 reg = <0x0 0xff650000 0x0 0x1000>;
546 clocks = <&cru PCLK_I2C0>;
547 clock-names = "i2c";
548 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c0_xfer>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 status = "disabled";
554 };
555
556 i2c2: i2c@ff660000 {
557 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
558 reg = <0x0 0xff660000 0x0 0x1000>;
559 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 clock-names = "i2c";
563 clocks = <&cru PCLK_I2C2>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c2_xfer>;
566 status = "disabled";
567 };
568
569 pwm0: pwm@ff680000 {
570 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
571 reg = <0x0 0xff680000 0x0 0x10>;
572 #pwm-cells = <3>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&pwm0_pin>;
575 clocks = <&cru PCLK_PWM1>;
576 clock-names = "pwm";
577 status = "disabled";
578 };
579
580 pwm1: pwm@ff680010 {
581 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
582 reg = <0x0 0xff680010 0x0 0x10>;
583 #pwm-cells = <3>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pwm1_pin>;
586 clocks = <&cru PCLK_PWM1>;
587 clock-names = "pwm";
588 status = "disabled";
589 };
590
591 pwm2: pwm@ff680020 {
592 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
593 reg = <0x0 0xff680020 0x0 0x10>;
594 #pwm-cells = <3>;
595 clocks = <&cru PCLK_PWM1>;
596 clock-names = "pwm";
597 status = "disabled";
598 };
599
600 pwm3: pwm@ff680030 {
601 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
602 reg = <0x0 0xff680030 0x0 0x10>;
603 #pwm-cells = <3>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pwm3_pin>;
606 clocks = <&cru PCLK_PWM1>;
607 clock-names = "pwm";
608 status = "disabled";
609 };
610
611 uart2: serial@ff690000 {
612 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
613 reg = <0x0 0xff690000 0x0 0x100>;
614 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
615 clock-names = "baudclk", "apb_pclk";
616 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart2_xfer>;
619 reg-shift = <2>;
620 reg-io-width = <4>;
621 status = "disabled";
622 };
623
624 mbox: mbox@ff6b0000 {
625 compatible = "rockchip,rk3368-mailbox";
626 reg = <0x0 0xff6b0000 0x0 0x1000>;
627 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&cru PCLK_MAILBOX>;
632 clock-names = "pclk_mailbox";
633 #mbox-cells = <1>;
634 };
635
636 pmugrf: syscon@ff738000 {
637 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
638 reg = <0x0 0xff738000 0x0 0x1000>;
639
640 pmu_io_domains: io-domains {
641 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
642 status = "disabled";
643 };
644 };
645
646 cru: clock-controller@ff760000 {
647 compatible = "rockchip,rk3368-cru";
648 reg = <0x0 0xff760000 0x0 0x1000>;
649 rockchip,grf = <&grf>;
650 #clock-cells = <1>;
651 #reset-cells = <1>;
652 };
653
654 grf: syscon@ff770000 {
655 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
656 reg = <0x0 0xff770000 0x0 0x1000>;
657
658 io_domains: io-domains {
659 compatible = "rockchip,rk3368-io-voltage-domain";
660 status = "disabled";
661 };
662 };
663
664 wdt: watchdog@ff800000 {
665 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
666 reg = <0x0 0xff800000 0x0 0x100>;
667 clocks = <&cru PCLK_WDT>;
668 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
669 status = "disabled";
670 };
671
672 timer@ff810000 {
673 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
674 reg = <0x0 0xff810000 0x0 0x20>;
675 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
676 };
677
678 gic: interrupt-controller@ffb71000 {
679 compatible = "arm,gic-400";
680 interrupt-controller;
681 #interrupt-cells = <3>;
682 #address-cells = <0>;
683
684 reg = <0x0 0xffb71000 0x0 0x1000>,
685 <0x0 0xffb72000 0x0 0x2000>,
686 <0x0 0xffb74000 0x0 0x2000>,
687 <0x0 0xffb76000 0x0 0x2000>;
688 interrupts = <GIC_PPI 9
689 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
690 };
691
692 pinctrl: pinctrl {
693 compatible = "rockchip,rk3368-pinctrl";
694 rockchip,grf = <&grf>;
695 rockchip,pmu = <&pmugrf>;
696 #address-cells = <0x2>;
697 #size-cells = <0x2>;
698 ranges;
699
700 gpio0: gpio0@ff750000 {
701 compatible = "rockchip,gpio-bank";
702 reg = <0x0 0xff750000 0x0 0x100>;
703 clocks = <&cru PCLK_GPIO0>;
704 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
705
706 gpio-controller;
707 #gpio-cells = <0x2>;
708
709 interrupt-controller;
710 #interrupt-cells = <0x2>;
711 };
712
713 gpio1: gpio1@ff780000 {
714 compatible = "rockchip,gpio-bank";
715 reg = <0x0 0xff780000 0x0 0x100>;
716 clocks = <&cru PCLK_GPIO1>;
717 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
718
719 gpio-controller;
720 #gpio-cells = <0x2>;
721
722 interrupt-controller;
723 #interrupt-cells = <0x2>;
724 };
725
726 gpio2: gpio2@ff790000 {
727 compatible = "rockchip,gpio-bank";
728 reg = <0x0 0xff790000 0x0 0x100>;
729 clocks = <&cru PCLK_GPIO2>;
730 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
731
732 gpio-controller;
733 #gpio-cells = <0x2>;
734
735 interrupt-controller;
736 #interrupt-cells = <0x2>;
737 };
738
739 gpio3: gpio3@ff7a0000 {
740 compatible = "rockchip,gpio-bank";
741 reg = <0x0 0xff7a0000 0x0 0x100>;
742 clocks = <&cru PCLK_GPIO3>;
743 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
744
745 gpio-controller;
746 #gpio-cells = <0x2>;
747
748 interrupt-controller;
749 #interrupt-cells = <0x2>;
750 };
751
752 pcfg_pull_up: pcfg-pull-up {
753 bias-pull-up;
754 };
755
756 pcfg_pull_down: pcfg-pull-down {
757 bias-pull-down;
758 };
759
760 pcfg_pull_none: pcfg-pull-none {
761 bias-disable;
762 };
763
764 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
765 bias-disable;
766 drive-strength = <12>;
767 };
768
769 emmc {
770 emmc_clk: emmc-clk {
771 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
772 };
773
774 emmc_cmd: emmc-cmd {
775 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
776 };
777
778 emmc_pwr: emmc-pwr {
779 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
780 };
781
782 emmc_bus1: emmc-bus1 {
783 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
784 };
785
786 emmc_bus4: emmc-bus4 {
787 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
788 <1 19 RK_FUNC_2 &pcfg_pull_up>,
789 <1 20 RK_FUNC_2 &pcfg_pull_up>,
790 <1 21 RK_FUNC_2 &pcfg_pull_up>;
791 };
792
793 emmc_bus8: emmc-bus8 {
794 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
795 <1 19 RK_FUNC_2 &pcfg_pull_up>,
796 <1 20 RK_FUNC_2 &pcfg_pull_up>,
797 <1 21 RK_FUNC_2 &pcfg_pull_up>,
798 <1 22 RK_FUNC_2 &pcfg_pull_up>,
799 <1 23 RK_FUNC_2 &pcfg_pull_up>,
800 <1 24 RK_FUNC_2 &pcfg_pull_up>,
801 <1 25 RK_FUNC_2 &pcfg_pull_up>;
802 };
803 };
804
805 gmac {
806 rgmii_pins: rgmii-pins {
807 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
808 <3 24 RK_FUNC_1 &pcfg_pull_none>,
809 <3 19 RK_FUNC_1 &pcfg_pull_none>,
810 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
811 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
812 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
813 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
814 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
815 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
816 <3 15 RK_FUNC_1 &pcfg_pull_none>,
817 <3 16 RK_FUNC_1 &pcfg_pull_none>,
818 <3 17 RK_FUNC_1 &pcfg_pull_none>,
819 <3 18 RK_FUNC_1 &pcfg_pull_none>,
820 <3 25 RK_FUNC_1 &pcfg_pull_none>,
821 <3 20 RK_FUNC_1 &pcfg_pull_none>;
822 };
823
824 rmii_pins: rmii-pins {
825 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
826 <3 24 RK_FUNC_1 &pcfg_pull_none>,
827 <3 19 RK_FUNC_1 &pcfg_pull_none>,
828 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
829 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
830 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
831 <3 15 RK_FUNC_1 &pcfg_pull_none>,
832 <3 16 RK_FUNC_1 &pcfg_pull_none>,
833 <3 20 RK_FUNC_1 &pcfg_pull_none>,
834 <3 21 RK_FUNC_1 &pcfg_pull_none>;
835 };
836 };
837
838 i2c0 {
839 i2c0_xfer: i2c0-xfer {
840 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
841 <0 7 RK_FUNC_1 &pcfg_pull_none>;
842 };
843 };
844
845 i2c1 {
846 i2c1_xfer: i2c1-xfer {
847 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
848 <2 22 RK_FUNC_1 &pcfg_pull_none>;
849 };
850 };
851
852 i2c2 {
853 i2c2_xfer: i2c2-xfer {
854 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
855 <3 31 RK_FUNC_2 &pcfg_pull_none>;
856 };
857 };
858
859 i2c3 {
860 i2c3_xfer: i2c3-xfer {
861 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
862 <1 17 RK_FUNC_1 &pcfg_pull_none>;
863 };
864 };
865
866 i2c4 {
867 i2c4_xfer: i2c4-xfer {
868 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
869 <3 25 RK_FUNC_2 &pcfg_pull_none>;
870 };
871 };
872
873 i2c5 {
874 i2c5_xfer: i2c5-xfer {
875 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
876 <3 27 RK_FUNC_2 &pcfg_pull_none>;
877 };
878 };
879
880 pwm0 {
881 pwm0_pin: pwm0-pin {
882 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
883 };
884 };
885
886 pwm1 {
887 pwm1_pin: pwm1-pin {
888 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
889 };
890 };
891
892 pwm3 {
893 pwm3_pin: pwm3-pin {
894 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
895 };
896 };
897
898 sdio0 {
899 sdio0_bus1: sdio0-bus1 {
900 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
901 };
902
903 sdio0_bus4: sdio0-bus4 {
904 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
905 <2 29 RK_FUNC_1 &pcfg_pull_up>,
906 <2 30 RK_FUNC_1 &pcfg_pull_up>,
907 <2 31 RK_FUNC_1 &pcfg_pull_up>;
908 };
909
910 sdio0_cmd: sdio0-cmd {
911 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
912 };
913
914 sdio0_clk: sdio0-clk {
915 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
916 };
917
918 sdio0_cd: sdio0-cd {
919 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
920 };
921
922 sdio0_wp: sdio0-wp {
923 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
924 };
925
926 sdio0_pwr: sdio0-pwr {
927 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
928 };
929
930 sdio0_bkpwr: sdio0-bkpwr {
931 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
932 };
933
934 sdio0_int: sdio0-int {
935 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
936 };
937 };
938
939 sdmmc {
940 sdmmc_clk: sdmmc-clk {
941 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
942 };
943
944 sdmmc_cmd: sdmmc-cmd {
945 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
946 };
947
948 sdmmc_cd: sdmmc-cd {
949 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
950 };
951
952 sdmmc_bus1: sdmmc-bus1 {
953 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
954 };
955
956 sdmmc_bus4: sdmmc-bus4 {
957 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
958 <2 6 RK_FUNC_1 &pcfg_pull_up>,
959 <2 7 RK_FUNC_1 &pcfg_pull_up>,
960 <2 8 RK_FUNC_1 &pcfg_pull_up>;
961 };
962 };
963
964 spi0 {
965 spi0_clk: spi0-clk {
966 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
967 };
968 spi0_cs0: spi0-cs0 {
969 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
970 };
971 spi0_cs1: spi0-cs1 {
972 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
973 };
974 spi0_tx: spi0-tx {
975 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
976 };
977 spi0_rx: spi0-rx {
978 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
979 };
980 };
981
982 spi1 {
983 spi1_clk: spi1-clk {
984 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
985 };
986 spi1_cs0: spi1-cs0 {
987 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
988 };
989 spi1_cs1: spi1-cs1 {
990 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
991 };
992 spi1_rx: spi1-rx {
993 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
994 };
995 spi1_tx: spi1-tx {
996 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
997 };
998 };
999
1000 spi2 {
1001 spi2_clk: spi2-clk {
1002 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1003 };
1004 spi2_cs0: spi2-cs0 {
1005 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1006 };
1007 spi2_rx: spi2-rx {
1008 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1009 };
1010 spi2_tx: spi2-tx {
1011 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1012 };
1013 };
1014
1015 tsadc {
1016 otp_gpio: otp-gpio {
1017 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1018 };
1019
1020 otp_out: otp-out {
1021 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1022 };
1023 };
1024
1025 uart0 {
1026 uart0_xfer: uart0-xfer {
1027 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1028 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1029 };
1030
1031 uart0_cts: uart0-cts {
1032 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1033 };
1034
1035 uart0_rts: uart0-rts {
1036 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1037 };
1038 };
1039
1040 uart1 {
1041 uart1_xfer: uart1-xfer {
1042 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1043 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1044 };
1045
1046 uart1_cts: uart1-cts {
1047 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1048 };
1049
1050 uart1_rts: uart1-rts {
1051 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1052 };
1053 };
1054
1055 uart2 {
1056 uart2_xfer: uart2-xfer {
1057 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1058 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1059 };
1060 /* no rts / cts for uart2 */
1061 };
1062
1063 uart3 {
1064 uart3_xfer: uart3-xfer {
1065 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1066 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1067 };
1068
1069 uart3_cts: uart3-cts {
1070 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1071 };
1072
1073 uart3_rts: uart3-rts {
1074 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1075 };
1076 };
1077
1078 uart4 {
1079 uart4_xfer: uart4-xfer {
1080 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1081 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1082 };
1083
1084 uart4_cts: uart4-cts {
1085 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1086 };
1087
1088 uart4_rts: uart4-rts {
1089 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1090 };
1091 };
1092 };
1093 };
Linux kernel - Deliverables
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