2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
54 interrupt-parent = <&gic>;
107 compatible = "arm,cortex-a53", "arm,armv8";
109 enable-method = "psci";
110 #cooling-cells = <2>; /* min followed by max */
111 clocks = <&cru ARMCLKL>;
116 compatible = "arm,cortex-a53", "arm,armv8";
118 enable-method = "psci";
119 clocks = <&cru ARMCLKL>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 enable-method = "psci";
127 clocks = <&cru ARMCLKL>;
132 compatible = "arm,cortex-a53", "arm,armv8";
134 enable-method = "psci";
135 clocks = <&cru ARMCLKL>;
140 compatible = "arm,cortex-a72", "arm,armv8";
142 enable-method = "psci";
143 #cooling-cells = <2>; /* min followed by max */
144 clocks = <&cru ARMCLKB>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 enable-method = "psci";
152 clocks = <&cru ARMCLKB>;
157 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
162 compatible = "arm,cortex-a72-pmu";
163 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
167 compatible = "arm,psci-1.0";
172 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
174 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
175 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
176 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
180 compatible = "fixed-clock";
181 clock-frequency = <24000000>;
182 clock-output-names = "xin24m";
187 compatible = "simple-bus";
188 #address-cells = <2>;
192 dmac_bus: dma-controller@ff6d0000 {
193 compatible = "arm,pl330", "arm,primecell";
194 reg = <0x0 0xff6d0000 0x0 0x4000>;
195 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
196 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
198 clocks = <&cru ACLK_DMAC0_PERILP>;
199 clock-names = "apb_pclk";
202 dmac_peri: dma-controller@ff6e0000 {
203 compatible = "arm,pl330", "arm,primecell";
204 reg = <0x0 0xff6e0000 0x0 0x4000>;
205 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
206 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
208 clocks = <&cru ACLK_DMAC1_PERILP>;
209 clock-names = "apb_pclk";
213 gmac: ethernet@fe300000 {
214 compatible = "rockchip,rk3399-gmac";
215 reg = <0x0 0xfe300000 0x0 0x10000>;
216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
217 interrupt-names = "macirq";
218 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
219 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
220 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
222 clock-names = "stmmaceth", "mac_clk_rx",
223 "mac_clk_tx", "clk_mac_ref",
224 "clk_mac_refout", "aclk_mac",
226 power-domains = <&power RK3399_PD_GMAC>;
227 resets = <&cru SRST_A_GMAC>;
228 reset-names = "stmmaceth";
229 rockchip,grf = <&grf>;
233 sdio0: dwmmc@fe310000 {
234 compatible = "rockchip,rk3399-dw-mshc",
235 "rockchip,rk3288-dw-mshc";
236 reg = <0x0 0xfe310000 0x0 0x4000>;
237 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
238 clock-freq-min-max = <400000 150000000>;
239 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
240 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
246 sdmmc: dwmmc@fe320000 {
247 compatible = "rockchip,rk3399-dw-mshc",
248 "rockchip,rk3288-dw-mshc";
249 reg = <0x0 0xfe320000 0x0 0x4000>;
250 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
251 clock-freq-min-max = <400000 150000000>;
252 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
253 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
254 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
255 fifo-depth = <0x100>;
259 sdhci: sdhci@fe330000 {
260 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
261 reg = <0x0 0xfe330000 0x0 0x10000>;
262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
263 arasan,soc-ctl-syscon = <&grf>;
264 assigned-clocks = <&cru SCLK_EMMC>;
265 assigned-clock-rates = <200000000>;
266 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
267 clock-names = "clk_xin", "clk_ahb";
268 clock-output-names = "emmc_cardclock";
271 phy-names = "phy_arasan";
275 pcie0: pcie@f8000000 {
276 compatible = "rockchip,rk3399-pcie";
277 reg = <0x0 0xf8000000 0x0 0x2000000>,
278 <0x0 0xfd000000 0x0 0x1000000>;
279 reg-names = "axi-base", "apb-base";
280 #address-cells = <3>;
282 #interrupt-cells = <1>;
283 bus-range = <0x0 0x1>;
284 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
285 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
286 clock-names = "aclk", "aclk-perf",
288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
289 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
291 interrupt-names = "sys", "legacy", "client";
292 interrupt-map-mask = <0 0 0 7>;
293 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
294 <0 0 0 2 &pcie0_intc 1>,
295 <0 0 0 3 &pcie0_intc 2>,
296 <0 0 0 4 &pcie0_intc 3>;
297 msi-map = <0x0 &its 0x0 0x1000>;
299 phy-names = "pcie-phy";
300 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
301 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
302 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
303 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
304 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
307 pcie0_intc: interrupt-controller {
308 interrupt-controller;
309 #address-cells = <0>;
310 #interrupt-cells = <1>;
314 usb_host0_ehci: usb@fe380000 {
315 compatible = "generic-ehci";
316 reg = <0x0 0xfe380000 0x0 0x20000>;
317 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
318 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
319 clock-names = "hclk_host0", "hclk_host0_arb";
320 phys = <&u2phy0_host>;
325 usb_host0_ohci: usb@fe3a0000 {
326 compatible = "generic-ohci";
327 reg = <0x0 0xfe3a0000 0x0 0x20000>;
328 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
329 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
330 clock-names = "hclk_host0", "hclk_host0_arb";
334 usb_host1_ehci: usb@fe3c0000 {
335 compatible = "generic-ehci";
336 reg = <0x0 0xfe3c0000 0x0 0x20000>;
337 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
338 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
339 clock-names = "hclk_host1", "hclk_host1_arb";
340 phys = <&u2phy1_host>;
345 usb_host1_ohci: usb@fe3e0000 {
346 compatible = "generic-ohci";
347 reg = <0x0 0xfe3e0000 0x0 0x20000>;
348 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
349 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
350 clock-names = "hclk_host1", "hclk_host1_arb";
354 gic: interrupt-controller@fee00000 {
355 compatible = "arm,gic-v3";
356 #interrupt-cells = <4>;
357 #address-cells = <2>;
360 interrupt-controller;
362 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
363 <0x0 0xfef00000 0 0xc0000>, /* GICR */
364 <0x0 0xfff00000 0 0x10000>, /* GICC */
365 <0x0 0xfff10000 0 0x10000>, /* GICH */
366 <0x0 0xfff20000 0 0x10000>; /* GICV */
367 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
368 its: interrupt-controller@fee20000 {
369 compatible = "arm,gic-v3-its";
371 reg = <0x0 0xfee20000 0x0 0x20000>;
375 ppi_cluster0: interrupt-partition-0 {
376 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
379 ppi_cluster1: interrupt-partition-1 {
380 affinity = <&cpu_b0 &cpu_b1>;
385 saradc: saradc@ff100000 {
386 compatible = "rockchip,rk3399-saradc";
387 reg = <0x0 0xff100000 0x0 0x100>;
388 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
389 #io-channel-cells = <1>;
390 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
391 clock-names = "saradc", "apb_pclk";
392 resets = <&cru SRST_P_SARADC>;
393 reset-names = "saradc-apb";
398 compatible = "rockchip,rk3399-i2c";
399 reg = <0x0 0xff110000 0x0 0x1000>;
400 assigned-clocks = <&cru SCLK_I2C1>;
401 assigned-clock-rates = <200000000>;
402 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
403 clock-names = "i2c", "pclk";
404 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c1_xfer>;
407 #address-cells = <1>;
413 compatible = "rockchip,rk3399-i2c";
414 reg = <0x0 0xff120000 0x0 0x1000>;
415 assigned-clocks = <&cru SCLK_I2C2>;
416 assigned-clock-rates = <200000000>;
417 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
418 clock-names = "i2c", "pclk";
419 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c2_xfer>;
422 #address-cells = <1>;
428 compatible = "rockchip,rk3399-i2c";
429 reg = <0x0 0xff130000 0x0 0x1000>;
430 assigned-clocks = <&cru SCLK_I2C3>;
431 assigned-clock-rates = <200000000>;
432 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
433 clock-names = "i2c", "pclk";
434 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c3_xfer>;
437 #address-cells = <1>;
443 compatible = "rockchip,rk3399-i2c";
444 reg = <0x0 0xff140000 0x0 0x1000>;
445 assigned-clocks = <&cru SCLK_I2C5>;
446 assigned-clock-rates = <200000000>;
447 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
448 clock-names = "i2c", "pclk";
449 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&i2c5_xfer>;
452 #address-cells = <1>;
458 compatible = "rockchip,rk3399-i2c";
459 reg = <0x0 0xff150000 0x0 0x1000>;
460 assigned-clocks = <&cru SCLK_I2C6>;
461 assigned-clock-rates = <200000000>;
462 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
463 clock-names = "i2c", "pclk";
464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c6_xfer>;
467 #address-cells = <1>;
473 compatible = "rockchip,rk3399-i2c";
474 reg = <0x0 0xff160000 0x0 0x1000>;
475 assigned-clocks = <&cru SCLK_I2C7>;
476 assigned-clock-rates = <200000000>;
477 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
478 clock-names = "i2c", "pclk";
479 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&i2c7_xfer>;
482 #address-cells = <1>;
487 uart0: serial@ff180000 {
488 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
489 reg = <0x0 0xff180000 0x0 0x100>;
490 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
491 clock-names = "baudclk", "apb_pclk";
492 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&uart0_xfer>;
500 uart1: serial@ff190000 {
501 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
502 reg = <0x0 0xff190000 0x0 0x100>;
503 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_pclk";
505 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&uart1_xfer>;
513 uart2: serial@ff1a0000 {
514 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
515 reg = <0x0 0xff1a0000 0x0 0x100>;
516 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
517 clock-names = "baudclk", "apb_pclk";
518 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&uart2c_xfer>;
526 uart3: serial@ff1b0000 {
527 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
528 reg = <0x0 0xff1b0000 0x0 0x100>;
529 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
530 clock-names = "baudclk", "apb_pclk";
531 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&uart3_xfer>;
540 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
541 reg = <0x0 0xff1c0000 0x0 0x1000>;
542 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
543 clock-names = "spiclk", "apb_pclk";
544 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
547 #address-cells = <1>;
553 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
554 reg = <0x0 0xff1d0000 0x0 0x1000>;
555 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
556 clock-names = "spiclk", "apb_pclk";
557 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
560 #address-cells = <1>;
566 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
567 reg = <0x0 0xff1e0000 0x0 0x1000>;
568 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
569 clock-names = "spiclk", "apb_pclk";
570 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
573 #address-cells = <1>;
579 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
580 reg = <0x0 0xff1f0000 0x0 0x1000>;
581 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
582 clock-names = "spiclk", "apb_pclk";
583 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
586 #address-cells = <1>;
592 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
593 reg = <0x0 0xff200000 0x0 0x1000>;
594 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
595 clock-names = "spiclk", "apb_pclk";
596 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
599 #address-cells = <1>;
606 polling-delay-passive = <100>;
607 polling-delay = <1000>;
609 thermal-sensors = <&tsadc 0>;
612 cpu_alert0: cpu_alert0 {
613 temperature = <70000>;
617 cpu_alert1: cpu_alert1 {
618 temperature = <75000>;
623 temperature = <95000>;
631 trip = <&cpu_alert0>;
633 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
636 trip = <&cpu_alert1>;
638 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
639 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
645 polling-delay-passive = <100>;
646 polling-delay = <1000>;
648 thermal-sensors = <&tsadc 1>;
651 gpu_alert0: gpu_alert0 {
652 temperature = <75000>;
657 temperature = <95000>;
665 trip = <&gpu_alert0>;
667 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
673 tsadc: tsadc@ff260000 {
674 compatible = "rockchip,rk3399-tsadc";
675 reg = <0x0 0xff260000 0x0 0x100>;
676 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
677 assigned-clocks = <&cru SCLK_TSADC>;
678 assigned-clock-rates = <750000>;
679 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
680 clock-names = "tsadc", "apb_pclk";
681 resets = <&cru SRST_TSADC>;
682 reset-names = "tsadc-apb";
683 rockchip,grf = <&grf>;
684 rockchip,hw-tshut-temp = <95000>;
685 pinctrl-names = "init", "default", "sleep";
686 pinctrl-0 = <&otp_gpio>;
687 pinctrl-1 = <&otp_out>;
688 pinctrl-2 = <&otp_gpio>;
689 #thermal-sensor-cells = <1>;
693 qos_gmac: qos@ffa5c000 {
694 compatible = "syscon";
695 reg = <0x0 0xffa5c000 0x0 0x20>;
698 qos_hdcp: qos@ffa90000 {
699 compatible = "syscon";
700 reg = <0x0 0xffa90000 0x0 0x20>;
703 qos_iep: qos@ffa98000 {
704 compatible = "syscon";
705 reg = <0x0 0xffa98000 0x0 0x20>;
708 qos_isp0_m0: qos@ffaa0000 {
709 compatible = "syscon";
710 reg = <0x0 0xffaa0000 0x0 0x20>;
713 qos_isp0_m1: qos@ffaa0080 {
714 compatible = "syscon";
715 reg = <0x0 0xffaa0080 0x0 0x20>;
718 qos_isp1_m0: qos@ffaa8000 {
719 compatible = "syscon";
720 reg = <0x0 0xffaa8000 0x0 0x20>;
723 qos_isp1_m1: qos@ffaa8080 {
724 compatible = "syscon";
725 reg = <0x0 0xffaa8080 0x0 0x20>;
728 qos_rga_r: qos@ffab0000 {
729 compatible = "syscon";
730 reg = <0x0 0xffab0000 0x0 0x20>;
733 qos_rga_w: qos@ffab0080 {
734 compatible = "syscon";
735 reg = <0x0 0xffab0080 0x0 0x20>;
738 qos_video_m0: qos@ffab8000 {
739 compatible = "syscon";
740 reg = <0x0 0xffab8000 0x0 0x20>;
743 qos_video_m1_r: qos@ffac0000 {
744 compatible = "syscon";
745 reg = <0x0 0xffac0000 0x0 0x20>;
748 qos_video_m1_w: qos@ffac0080 {
749 compatible = "syscon";
750 reg = <0x0 0xffac0080 0x0 0x20>;
753 qos_vop_big_r: qos@ffac8000 {
754 compatible = "syscon";
755 reg = <0x0 0xffac8000 0x0 0x20>;
758 qos_vop_big_w: qos@ffac8080 {
759 compatible = "syscon";
760 reg = <0x0 0xffac8080 0x0 0x20>;
763 qos_vop_little: qos@ffad0000 {
764 compatible = "syscon";
765 reg = <0x0 0xffad0000 0x0 0x20>;
768 qos_gpu: qos@ffae0000 {
769 compatible = "syscon";
770 reg = <0x0 0xffae0000 0x0 0x20>;
773 pmu: power-management@ff310000 {
774 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
775 reg = <0x0 0xff310000 0x0 0x1000>;
778 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
779 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
780 * Some of the power domains are grouped together for every
782 * The detail contents as below.
784 power: power-controller {
785 compatible = "rockchip,rk3399-power-controller";
786 #power-domain-cells = <1>;
787 #address-cells = <1>;
790 /* These power domains are grouped by VD_CENTER */
791 pd_iep@RK3399_PD_IEP {
792 reg = <RK3399_PD_IEP>;
793 clocks = <&cru ACLK_IEP>,
797 pd_rga@RK3399_PD_RGA {
798 reg = <RK3399_PD_RGA>;
799 clocks = <&cru ACLK_RGA>,
801 pm_qos = <&qos_rga_r>,
804 pd_vcodec@RK3399_PD_VCODEC {
805 reg = <RK3399_PD_VCODEC>;
806 clocks = <&cru ACLK_VCODEC>,
808 pm_qos = <&qos_video_m0>;
810 pd_vdu@RK3399_PD_VDU {
811 reg = <RK3399_PD_VDU>;
812 clocks = <&cru ACLK_VDU>,
814 pm_qos = <&qos_video_m1_r>,
818 /* These power domains are grouped by VD_GPU */
819 pd_gpu@RK3399_PD_GPU {
820 reg = <RK3399_PD_GPU>;
821 clocks = <&cru ACLK_GPU>;
825 /* These power domains are grouped by VD_LOGIC */
826 pd_gmac@RK3399_PD_GMAC {
827 reg = <RK3399_PD_GMAC>;
828 clocks = <&cru ACLK_GMAC>;
829 pm_qos = <&qos_gmac>;
831 pd_vio@RK3399_PD_VIO {
832 reg = <RK3399_PD_VIO>;
833 #address-cells = <1>;
836 pd_hdcp@RK3399_PD_HDCP {
837 reg = <RK3399_PD_HDCP>;
838 clocks = <&cru ACLK_HDCP>,
841 pm_qos = <&qos_hdcp>;
843 pd_isp0@RK3399_PD_ISP0 {
844 reg = <RK3399_PD_ISP0>;
845 clocks = <&cru ACLK_ISP0>,
847 pm_qos = <&qos_isp0_m0>,
850 pd_isp1@RK3399_PD_ISP1 {
851 reg = <RK3399_PD_ISP1>;
852 clocks = <&cru ACLK_ISP1>,
854 pm_qos = <&qos_isp1_m0>,
857 pd_tcpc0@RK3399_PD_TCPC0 {
858 reg = <RK3399_PD_TCPD0>;
859 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
860 <&cru SCLK_UPHY0_TCPDPHY_REF>;
862 pd_tcpc1@RK3399_PD_TCPC1 {
863 reg = <RK3399_PD_TCPD1>;
864 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
865 <&cru SCLK_UPHY1_TCPDPHY_REF>;
868 reg = <RK3399_PD_VO>;
869 #address-cells = <1>;
872 pd_vopb@RK3399_PD_VOPB {
873 reg = <RK3399_PD_VOPB>;
874 clocks = <&cru ACLK_VOP0>,
876 pm_qos = <&qos_vop_big_r>,
879 pd_vopl@RK3399_PD_VOPL {
880 reg = <RK3399_PD_VOPL>;
881 clocks = <&cru ACLK_VOP1>,
883 pm_qos = <&qos_vop_little>;
890 pmugrf: syscon@ff320000 {
891 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
892 reg = <0x0 0xff320000 0x0 0x1000>;
893 #address-cells = <1>;
896 pmu_io_domains: io-domains {
897 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
903 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
904 reg = <0x0 0xff350000 0x0 0x1000>;
905 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
906 clock-names = "spiclk", "apb_pclk";
907 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
908 pinctrl-names = "default";
909 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
910 #address-cells = <1>;
915 uart4: serial@ff370000 {
916 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
917 reg = <0x0 0xff370000 0x0 0x100>;
918 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
919 clock-names = "baudclk", "apb_pclk";
920 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
923 pinctrl-names = "default";
924 pinctrl-0 = <&uart4_xfer>;
929 compatible = "rockchip,rk3399-i2c";
930 reg = <0x0 0xff3c0000 0x0 0x1000>;
931 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
932 assigned-clock-rates = <200000000>;
933 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
934 clock-names = "i2c", "pclk";
935 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&i2c0_xfer>;
938 #address-cells = <1>;
944 compatible = "rockchip,rk3399-i2c";
945 reg = <0x0 0xff3d0000 0x0 0x1000>;
946 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
947 assigned-clock-rates = <200000000>;
948 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
949 clock-names = "i2c", "pclk";
950 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&i2c4_xfer>;
953 #address-cells = <1>;
959 compatible = "rockchip,rk3399-i2c";
960 reg = <0x0 0xff3e0000 0x0 0x1000>;
961 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
962 assigned-clock-rates = <200000000>;
963 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
964 clock-names = "i2c", "pclk";
965 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
966 pinctrl-names = "default";
967 pinctrl-0 = <&i2c8_xfer>;
968 #address-cells = <1>;
974 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
975 reg = <0x0 0xff420000 0x0 0x10>;
977 pinctrl-names = "default";
978 pinctrl-0 = <&pwm0_pin>;
979 clocks = <&pmucru PCLK_RKPWM_PMU>;
985 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
986 reg = <0x0 0xff420010 0x0 0x10>;
988 pinctrl-names = "default";
989 pinctrl-0 = <&pwm1_pin>;
990 clocks = <&pmucru PCLK_RKPWM_PMU>;
996 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
997 reg = <0x0 0xff420020 0x0 0x10>;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&pwm2_pin>;
1001 clocks = <&pmucru PCLK_RKPWM_PMU>;
1002 clock-names = "pwm";
1003 status = "disabled";
1006 pwm3: pwm@ff420030 {
1007 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1008 reg = <0x0 0xff420030 0x0 0x10>;
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&pwm3a_pin>;
1012 clocks = <&pmucru PCLK_RKPWM_PMU>;
1013 clock-names = "pwm";
1014 status = "disabled";
1017 efuse0: efuse@ff690000 {
1018 compatible = "rockchip,rk3399-efuse";
1019 reg = <0x0 0xff690000 0x0 0x80>;
1020 #address-cells = <1>;
1022 clocks = <&cru PCLK_EFUSE1024NS>;
1023 clock-names = "pclk_efuse";
1026 cpub_leakage: cpu-leakage@17 {
1029 gpu_leakage: gpu-leakage@18 {
1032 center_leakage: center-leakage@19 {
1035 cpul_leakage: cpu-leakage@1a {
1038 logic_leakage: logic-leakage@1b {
1041 wafer_info: wafer-info@1c {
1046 pmucru: pmu-clock-controller@ff750000 {
1047 compatible = "rockchip,rk3399-pmucru";
1048 reg = <0x0 0xff750000 0x0 0x1000>;
1051 assigned-clocks = <&pmucru PLL_PPLL>;
1052 assigned-clock-rates = <676000000>;
1055 cru: clock-controller@ff760000 {
1056 compatible = "rockchip,rk3399-cru";
1057 reg = <0x0 0xff760000 0x0 0x1000>;
1061 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1063 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1065 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1066 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1067 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1068 assigned-clock-rates =
1069 <594000000>, <800000000>,
1071 <150000000>, <75000000>,
1073 <100000000>, <100000000>,
1074 <50000000>, <600000000>,
1075 <100000000>, <50000000>;
1078 grf: syscon@ff770000 {
1079 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1080 reg = <0x0 0xff770000 0x0 0x10000>;
1081 #address-cells = <1>;
1084 io_domains: io-domains {
1085 compatible = "rockchip,rk3399-io-voltage-domain";
1086 status = "disabled";
1089 u2phy0: usb2-phy@e450 {
1090 compatible = "rockchip,rk3399-usb2phy";
1091 reg = <0xe450 0x10>;
1092 clocks = <&cru SCLK_USB2PHY0_REF>;
1093 clock-names = "phyclk";
1095 clock-output-names = "clk_usbphy0_480m";
1096 status = "disabled";
1098 u2phy0_host: host-port {
1100 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1101 interrupt-names = "linestate";
1102 status = "disabled";
1106 u2phy1: usb2-phy@e460 {
1107 compatible = "rockchip,rk3399-usb2phy";
1108 reg = <0xe460 0x10>;
1109 clocks = <&cru SCLK_USB2PHY1_REF>;
1110 clock-names = "phyclk";
1112 clock-output-names = "clk_usbphy1_480m";
1113 status = "disabled";
1115 u2phy1_host: host-port {
1117 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1118 interrupt-names = "linestate";
1119 status = "disabled";
1123 emmc_phy: phy@f780 {
1124 compatible = "rockchip,rk3399-emmc-phy";
1125 reg = <0xf780 0x24>;
1127 clock-names = "emmcclk";
1129 status = "disabled";
1132 pcie_phy: pcie-phy {
1133 compatible = "rockchip,rk3399-pcie-phy";
1134 clocks = <&cru SCLK_PCIEPHY_REF>;
1135 clock-names = "refclk";
1137 resets = <&cru SRST_PCIEPHY>;
1138 reset-names = "phy";
1139 status = "disabled";
1143 tcphy0: phy@ff7c0000 {
1144 compatible = "rockchip,rk3399-typec-phy";
1145 reg = <0x0 0xff7c0000 0x0 0x40000>;
1146 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1147 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1148 clock-names = "tcpdcore", "tcpdphy-ref";
1149 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1150 assigned-clock-rates = <50000000>;
1151 resets = <&cru SRST_UPHY0>,
1152 <&cru SRST_UPHY0_PIPE_L00>,
1153 <&cru SRST_P_UPHY0_TCPHY>;
1154 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1155 rockchip,grf = <&grf>;
1156 rockchip,typec-conn-dir = <0xe580 0 16>;
1157 rockchip,usb3tousb2-en = <0xe580 3 19>;
1158 rockchip,external-psm = <0xe588 14 30>;
1159 rockchip,pipe-status = <0xe5c0 0 0>;
1160 status = "disabled";
1162 tcphy0_dp: dp-port {
1166 tcphy0_usb3: usb3-port {
1171 tcphy1: phy@ff800000 {
1172 compatible = "rockchip,rk3399-typec-phy";
1173 reg = <0x0 0xff800000 0x0 0x40000>;
1174 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1175 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1176 clock-names = "tcpdcore", "tcpdphy-ref";
1177 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1178 assigned-clock-rates = <50000000>;
1179 resets = <&cru SRST_UPHY1>,
1180 <&cru SRST_UPHY1_PIPE_L00>,
1181 <&cru SRST_P_UPHY1_TCPHY>;
1182 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1183 rockchip,grf = <&grf>;
1184 rockchip,typec-conn-dir = <0xe58c 0 16>;
1185 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1186 rockchip,external-psm = <0xe594 14 30>;
1187 rockchip,pipe-status = <0xe5c0 16 16>;
1188 status = "disabled";
1190 tcphy1_dp: dp-port {
1194 tcphy1_usb3: usb3-port {
1200 compatible = "snps,dw-wdt";
1201 reg = <0x0 0xff848000 0x0 0x100>;
1202 clocks = <&cru PCLK_WDT>;
1203 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1206 rktimer: rktimer@ff850000 {
1207 compatible = "rockchip,rk3399-timer";
1208 reg = <0x0 0xff850000 0x0 0x1000>;
1209 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1210 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1211 clock-names = "pclk", "timer";
1214 spdif: spdif@ff870000 {
1215 compatible = "rockchip,rk3399-spdif";
1216 reg = <0x0 0xff870000 0x0 0x1000>;
1217 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1218 dmas = <&dmac_bus 7>;
1220 clock-names = "mclk", "hclk";
1221 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&spdif_bus>;
1224 status = "disabled";
1227 i2s0: i2s@ff880000 {
1228 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1229 reg = <0x0 0xff880000 0x0 0x1000>;
1230 rockchip,grf = <&grf>;
1231 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1232 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1233 dma-names = "tx", "rx";
1234 clock-names = "i2s_clk", "i2s_hclk";
1235 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&i2s0_8ch_bus>;
1238 status = "disabled";
1241 i2s1: i2s@ff890000 {
1242 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1243 reg = <0x0 0xff890000 0x0 0x1000>;
1244 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1245 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1246 dma-names = "tx", "rx";
1247 clock-names = "i2s_clk", "i2s_hclk";
1248 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&i2s1_2ch_bus>;
1251 status = "disabled";
1254 i2s2: i2s@ff8a0000 {
1255 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1256 reg = <0x0 0xff8a0000 0x0 0x1000>;
1257 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1258 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1259 dma-names = "tx", "rx";
1260 clock-names = "i2s_clk", "i2s_hclk";
1261 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1262 status = "disabled";
1266 compatible = "rockchip,rk3399-pinctrl";
1267 rockchip,grf = <&grf>;
1268 rockchip,pmu = <&pmugrf>;
1269 #address-cells = <2>;
1273 gpio0: gpio0@ff720000 {
1274 compatible = "rockchip,gpio-bank";
1275 reg = <0x0 0xff720000 0x0 0x100>;
1276 clocks = <&pmucru PCLK_GPIO0_PMU>;
1277 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1280 #gpio-cells = <0x2>;
1282 interrupt-controller;
1283 #interrupt-cells = <0x2>;
1286 gpio1: gpio1@ff730000 {
1287 compatible = "rockchip,gpio-bank";
1288 reg = <0x0 0xff730000 0x0 0x100>;
1289 clocks = <&pmucru PCLK_GPIO1_PMU>;
1290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1293 #gpio-cells = <0x2>;
1295 interrupt-controller;
1296 #interrupt-cells = <0x2>;
1299 gpio2: gpio2@ff780000 {
1300 compatible = "rockchip,gpio-bank";
1301 reg = <0x0 0xff780000 0x0 0x100>;
1302 clocks = <&cru PCLK_GPIO2>;
1303 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1306 #gpio-cells = <0x2>;
1308 interrupt-controller;
1309 #interrupt-cells = <0x2>;
1312 gpio3: gpio3@ff788000 {
1313 compatible = "rockchip,gpio-bank";
1314 reg = <0x0 0xff788000 0x0 0x100>;
1315 clocks = <&cru PCLK_GPIO3>;
1316 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1319 #gpio-cells = <0x2>;
1321 interrupt-controller;
1322 #interrupt-cells = <0x2>;
1325 gpio4: gpio4@ff790000 {
1326 compatible = "rockchip,gpio-bank";
1327 reg = <0x0 0xff790000 0x0 0x100>;
1328 clocks = <&cru PCLK_GPIO4>;
1329 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1332 #gpio-cells = <0x2>;
1334 interrupt-controller;
1335 #interrupt-cells = <0x2>;
1338 pcfg_pull_up: pcfg-pull-up {
1342 pcfg_pull_down: pcfg-pull-down {
1346 pcfg_pull_none: pcfg-pull-none {
1350 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1352 drive-strength = <12>;
1355 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1357 drive-strength = <8>;
1360 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1362 drive-strength = <4>;
1365 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1367 drive-strength = <2>;
1370 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1372 drive-strength = <12>;
1375 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1377 drive-strength = <13>;
1382 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1387 rgmii_pins: rgmii-pins {
1390 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1392 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1394 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1396 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1398 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1400 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1402 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1404 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1406 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1408 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1410 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1412 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1414 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1416 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1418 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1421 rmii_pins: rmii-pins {
1424 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1426 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1428 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1430 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1432 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1434 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1436 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1438 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1440 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1442 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1447 i2c0_xfer: i2c0-xfer {
1449 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1450 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1455 i2c1_xfer: i2c1-xfer {
1457 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1458 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1463 i2c2_xfer: i2c2-xfer {
1465 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1466 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1471 i2c3_xfer: i2c3-xfer {
1473 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1474 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1479 i2c4_xfer: i2c4-xfer {
1481 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1482 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1487 i2c5_xfer: i2c5-xfer {
1489 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1490 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1495 i2c6_xfer: i2c6-xfer {
1497 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1498 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1503 i2c7_xfer: i2c7-xfer {
1505 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1506 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1511 i2c8_xfer: i2c8-xfer {
1513 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1514 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1519 i2s0_8ch_bus: i2s0-8ch-bus {
1521 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1522 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1523 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1524 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1525 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1526 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1527 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1528 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1529 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1534 i2s1_2ch_bus: i2s1-2ch-bus {
1536 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1537 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1538 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1539 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1540 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1545 ap_pwroff: ap-pwroff {
1546 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1549 ddrio_pwroff: ddrio-pwroff {
1550 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1555 spdif_bus: spdif-bus {
1557 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1562 spi0_clk: spi0-clk {
1564 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1566 spi0_cs0: spi0-cs0 {
1568 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1570 spi0_cs1: spi0-cs1 {
1572 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1576 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1580 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1585 spi1_clk: spi1-clk {
1587 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1589 spi1_cs0: spi1-cs0 {
1591 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1595 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1599 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1604 spi2_clk: spi2-clk {
1606 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1608 spi2_cs0: spi2-cs0 {
1610 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1614 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1618 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1623 spi3_clk: spi3-clk {
1625 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1627 spi3_cs0: spi3-cs0 {
1629 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1633 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1637 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1642 spi4_clk: spi4-clk {
1644 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1646 spi4_cs0: spi4-cs0 {
1648 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1652 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1656 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1661 spi5_clk: spi5-clk {
1663 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1665 spi5_cs0: spi5-cs0 {
1667 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1671 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1675 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1680 otp_gpio: otp-gpio {
1681 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1685 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1690 uart0_xfer: uart0-xfer {
1692 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1693 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1696 uart0_cts: uart0-cts {
1698 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1701 uart0_rts: uart0-rts {
1703 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1708 uart1_xfer: uart1-xfer {
1710 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1711 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1716 uart2a_xfer: uart2a-xfer {
1718 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1719 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1724 uart2b_xfer: uart2b-xfer {
1726 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1727 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1732 uart2c_xfer: uart2c-xfer {
1734 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1735 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1740 uart3_xfer: uart3-xfer {
1742 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1743 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1746 uart3_cts: uart3-cts {
1748 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1751 uart3_rts: uart3-rts {
1753 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1758 uart4_xfer: uart4-xfer {
1760 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1761 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1766 uarthdcp_xfer: uarthdcp-xfer {
1768 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1769 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1774 pwm0_pin: pwm0-pin {
1776 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1779 vop0_pwm_pin: vop0-pwm-pin {
1781 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1786 pwm1_pin: pwm1-pin {
1788 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1791 vop1_pwm_pin: vop1-pwm-pin {
1793 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1798 pwm2_pin: pwm2-pin {
1800 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1805 pwm3a_pin: pwm3a-pin {
1807 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1812 pwm3b_pin: pwm3b-pin {
1814 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1819 pcie_clkreqn: pci-clkreqn {
1821 <2 26 RK_FUNC_2 &pcfg_pull_none>;
1824 pcie_clkreqnb: pci-clkreqnb {
1826 <4 24 RK_FUNC_1 &pcfg_pull_none>;