2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
15 compatible = "xlnx,zynqmp";
24 compatible = "arm,cortex-a53", "arm,armv8";
26 enable-method = "psci";
31 compatible = "arm,cortex-a53", "arm,armv8";
33 enable-method = "psci";
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
45 compatible = "arm,cortex-a53", "arm,armv8";
47 enable-method = "psci";
53 compatible = "arm,armv8-pmuv3";
54 interrupts = <0 143 4>,
61 compatible = "arm,psci-0.2";
66 compatible = "arm,armv8-timer";
67 interrupt-parent = <&gic>;
68 interrupts = <1 13 0xf01>,
75 compatible = "simple-bus";
80 gic: interrupt-controller@f9010000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 reg = <0x0 0xf9010000 0x10000>,
84 <0x0 0xf902f000 0x2000>,
85 <0x0 0xf9040000 0x20000>,
86 <0x0 0xf906f000 0x2000>;
88 interrupt-parent = <&gic>;
89 interrupts = <1 9 0xf04>;
94 compatible = "simple-bus";
100 compatible = "xlnx,zynq-can-1.0";
102 clocks = <&misc_clk &misc_clk>;
103 clock-names = "can_clk", "pclk";
104 reg = <0x0 0xff060000 0x1000>;
105 interrupts = <0 23 4>;
106 interrupt-parent = <&gic>;
107 tx-fifo-depth = <0x40>;
108 rx-fifo-depth = <0x40>;
112 compatible = "xlnx,zynq-can-1.0";
114 clocks = <&misc_clk &misc_clk>;
115 clock-names = "can_clk", "pclk";
116 reg = <0x0 0xff070000 0x1000>;
117 interrupts = <0 24 4>;
118 interrupt-parent = <&gic>;
119 tx-fifo-depth = <0x40>;
120 rx-fifo-depth = <0x40>;
124 compatible = "fixed-clock";
126 clock-frequency = <25000000>;
129 gpio: gpio@ff0a0000 {
130 compatible = "xlnx,zynqmp-gpio-1.0";
133 clocks = <&misc_clk>;
134 interrupt-parent = <&gic>;
135 interrupts = <0 16 4>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 reg = <0x0 0xff0a0000 0x1000>;
141 gem0: ethernet@ff0b0000 {
142 compatible = "cdns,gem";
144 interrupt-parent = <&gic>;
145 interrupts = <0 57 4>, <0 57 4>;
146 reg = <0x0 0xff0b0000 0x1000>;
147 clock-names = "pclk", "hclk", "tx_clk";
148 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
149 #address-cells = <1>;
153 gem1: ethernet@ff0c0000 {
154 compatible = "cdns,gem";
156 interrupt-parent = <&gic>;
157 interrupts = <0 59 4>, <0 59 4>;
158 reg = <0x0 0xff0c0000 0x1000>;
159 clock-names = "pclk", "hclk", "tx_clk";
160 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
161 #address-cells = <1>;
165 gem2: ethernet@ff0d0000 {
166 compatible = "cdns,gem";
168 interrupt-parent = <&gic>;
169 interrupts = <0 61 4>, <0 61 4>;
170 reg = <0x0 0xff0d0000 0x1000>;
171 clock-names = "pclk", "hclk", "tx_clk";
172 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
173 #address-cells = <1>;
177 gem3: ethernet@ff0e0000 {
178 compatible = "cdns,gem";
180 interrupt-parent = <&gic>;
181 interrupts = <0 63 4>, <0 63 4>;
182 reg = <0x0 0xff0e0000 0x1000>;
183 clock-names = "pclk", "hclk", "tx_clk";
184 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
185 #address-cells = <1>;
190 compatible = "fixed-clock";
191 #clock-cells = <0x0>;
192 clock-frequency = <111111111>;
196 compatible = "cdns,i2c-r1p10";
198 interrupt-parent = <&gic>;
199 interrupts = <0 17 4>;
200 reg = <0x0 0xff020000 0x1000>;
202 #address-cells = <1>;
207 compatible = "cdns,i2c-r1p10";
209 interrupt-parent = <&gic>;
210 interrupts = <0 18 4>;
211 reg = <0x0 0xff030000 0x1000>;
213 #address-cells = <1>;
218 compatible = "fixed-clock";
220 clock-frequency = <75000000>;
223 sata: ahci@fd0c0000 {
224 compatible = "ceva,ahci-1v84";
226 reg = <0x0 0xfd0c0000 0x2000>;
227 interrupt-parent = <&gic>;
228 interrupts = <0 133 4>;
229 clocks = <&sata_clk>;
232 sdhci0: sdhci@ff160000 {
233 compatible = "arasan,sdhci-8.9a";
235 interrupt-parent = <&gic>;
236 interrupts = <0 48 4>;
237 reg = <0x0 0xff160000 0x1000>;
238 clock-names = "clk_xin", "clk_ahb";
239 clocks = <&misc_clk>, <&misc_clk>;
242 sdhci1: sdhci@ff170000 {
243 compatible = "arasan,sdhci-8.9a";
245 interrupt-parent = <&gic>;
246 interrupts = <0 49 4>;
247 reg = <0x0 0xff170000 0x1000>;
248 clock-names = "clk_xin", "clk_ahb";
249 clocks = <&misc_clk>, <&misc_clk>;
252 smmu: smmu@fd800000 {
253 compatible = "arm,mmu-500";
254 reg = <0x0 0xfd800000 0x20000>;
255 #global-interrupts = <1>;
256 interrupt-parent = <&gic>;
257 interrupts = <0 157 4>,
258 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
259 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
260 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
261 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
265 compatible = "cdns,spi-r1p6";
267 interrupt-parent = <&gic>;
268 interrupts = <0 19 4>;
269 reg = <0x0 0xff040000 0x1000>;
270 clock-names = "ref_clk", "pclk";
271 clocks = <&misc_clk &misc_clk>;
272 #address-cells = <1>;
277 compatible = "cdns,spi-r1p6";
279 interrupt-parent = <&gic>;
280 interrupts = <0 20 4>;
281 reg = <0x0 0xff050000 0x1000>;
282 clock-names = "ref_clk", "pclk";
283 clocks = <&misc_clk &misc_clk>;
284 #address-cells = <1>;
288 ttc0: timer@ff110000 {
289 compatible = "cdns,ttc";
291 interrupt-parent = <&gic>;
292 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
293 reg = <0x0 0xff110000 0x1000>;
294 clocks = <&misc_clk>;
298 ttc1: timer@ff120000 {
299 compatible = "cdns,ttc";
301 interrupt-parent = <&gic>;
302 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
303 reg = <0x0 0xff120000 0x1000>;
304 clocks = <&misc_clk>;
308 ttc2: timer@ff130000 {
309 compatible = "cdns,ttc";
311 interrupt-parent = <&gic>;
312 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
313 reg = <0x0 0xff130000 0x1000>;
314 clocks = <&misc_clk>;
318 ttc3: timer@ff140000 {
319 compatible = "cdns,ttc";
321 interrupt-parent = <&gic>;
322 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
323 reg = <0x0 0xff140000 0x1000>;
324 clocks = <&misc_clk>;
328 uart0: serial@ff000000 {
329 compatible = "cdns,uart-r1p8";
331 interrupt-parent = <&gic>;
332 interrupts = <0 21 4>;
333 reg = <0x0 0xff000000 0x1000>;
334 clock-names = "uart_clk", "pclk";
335 clocks = <&misc_clk &misc_clk>;
338 uart1: serial@ff010000 {
339 compatible = "cdns,uart-r1p8";
341 interrupt-parent = <&gic>;
342 interrupts = <0 22 4>;
343 reg = <0x0 0xff010000 0x1000>;
344 clock-names = "uart_clk", "pclk";
345 clocks = <&misc_clk &misc_clk>;
349 compatible = "snps,dwc3";
351 interrupt-parent = <&gic>;
352 interrupts = <0 65 4>;
353 reg = <0x0 0xfe200000 0x40000>;
354 clock-names = "clk_xin", "clk_ahb";
355 clocks = <&misc_clk>, <&misc_clk>;
359 compatible = "snps,dwc3";
361 interrupt-parent = <&gic>;
362 interrupts = <0 70 4>;
363 reg = <0x0 0xfe300000 0x40000>;
364 clock-names = "clk_xin", "clk_ahb";
365 clocks = <&misc_clk>, <&misc_clk>;
368 watchdog0: watchdog@fd4d0000 {
369 compatible = "cdns,wdt-r1p2";
372 interrupt-parent = <&gic>;
373 interrupts = <0 52 1>;
374 reg = <0x0 0xfd4d0000 0x1000>;