arch/arm64/include/asm/pgtable-hwdef.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_PGTABLE_HWDEF_H
  17 #define __ASM_PGTABLE_HWDEF_H
  18
  19 #if CONFIG_ARM64_PGTABLE_LEVELS == 2
  20 #include <asm/pgtable-2level-hwdef.h>
  21 #elif CONFIG_ARM64_PGTABLE_LEVELS == 3
  22 #include <asm/pgtable-3level-hwdef.h>
  23 #else
  24 #include <asm/pgtable-4level-hwdef.h>
  25 #endif
  26
  27 /*
  28  * Hardware page table definitions.
  29  *
  30  * Level 1 descriptor (PUD).
  31  */
  32 #define PUD_TYPE_TABLE          (_AT(pudval_t, 3) << 0)
  33 #define PUD_TABLE_BIT           (_AT(pgdval_t, 1) << 1)
  34 #define PUD_TYPE_MASK           (_AT(pgdval_t, 3) << 0)
  35 #define PUD_TYPE_SECT           (_AT(pgdval_t, 1) << 0)
  36
  37 /*
  38  * Level 2 descriptor (PMD).
  39  */
  40 #define PMD_TYPE_MASK           (_AT(pmdval_t, 3) << 0)
  41 #define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
  42 #define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
  43 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
  44 #define PMD_TABLE_BIT           (_AT(pmdval_t, 1) << 1)
  45
  46 /*
  47  * Section
  48  */
  49 #define PMD_SECT_VALID          (_AT(pmdval_t, 1) << 0)
  50 #define PMD_SECT_PROT_NONE      (_AT(pmdval_t, 1) << 58)
  51 #define PMD_SECT_USER           (_AT(pmdval_t, 1) << 6)         /* AP[1] */
  52 #define PMD_SECT_RDONLY         (_AT(pmdval_t, 1) << 7)         /* AP[2] */
  53 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
  54 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
  55 #define PMD_SECT_NG             (_AT(pmdval_t, 1) << 11)
  56 #define PMD_SECT_PXN            (_AT(pmdval_t, 1) << 53)
  57 #define PMD_SECT_UXN            (_AT(pmdval_t, 1) << 54)
  58
  59 /*
  60  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
  61  */
  62 #define PMD_ATTRINDX(t)         (_AT(pmdval_t, (t)) << 2)
  63 #define PMD_ATTRINDX_MASK       (_AT(pmdval_t, 7) << 2)
  64
  65 /*
  66  * Level 3 descriptor (PTE).
  67  */
  68 #define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
  69 #define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
  70 #define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
  71 #define PTE_TABLE_BIT           (_AT(pteval_t, 1) << 1)
  72 #define PTE_USER                (_AT(pteval_t, 1) << 6)         /* AP[1] */
  73 #define PTE_RDONLY              (_AT(pteval_t, 1) << 7)         /* AP[2] */
  74 #define PTE_SHARED              (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
  75 #define PTE_AF                  (_AT(pteval_t, 1) << 10)        /* Access Flag */
  76 #define PTE_NG                  (_AT(pteval_t, 1) << 11)        /* nG */
  77 #define PTE_PXN                 (_AT(pteval_t, 1) << 53)        /* Privileged XN */
  78 #define PTE_UXN                 (_AT(pteval_t, 1) << 54)        /* User XN */
  79
  80 /*
  81  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
  82  */
  83 #define PTE_ATTRINDX(t)         (_AT(pteval_t, (t)) << 2)
  84 #define PTE_ATTRINDX_MASK       (_AT(pteval_t, 7) << 2)
  85
  86 /*
  87  * 2nd stage PTE definitions
  88  */
  89 #define PTE_S2_RDONLY           (_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
  90 #define PTE_S2_RDWR             (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
  91
  92 #define PMD_S2_RDWR             (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
  93
  94 /*
  95  * Memory Attribute override for Stage-2 (MemAttr[3:0])
  96  */
  97 #define PTE_S2_MEMATTR(t)       (_AT(pteval_t, (t)) << 2)
  98 #define PTE_S2_MEMATTR_MASK     (_AT(pteval_t, 0xf) << 2)
  99
 100 /*
 101  * EL2/HYP PTE/PMD definitions
 102  */
 103 #define PMD_HYP                 PMD_SECT_USER
 104 #define PTE_HYP                 PTE_USER
 105
 106 /*
 107  * Highest possible physical address supported.
 108  */
 109 #define PHYS_MASK_SHIFT         (48)
 110 #define PHYS_MASK               ((UL(1) << PHYS_MASK_SHIFT) - 1)
 111
 112 /*
 113  * TCR flags.
 114  */
 115 #define TCR_TxSZ(x)             (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0))
 116 #define TCR_IRGN_NC             ((UL(0) << 8) | (UL(0) << 24))
 117 #define TCR_IRGN_WBWA           ((UL(1) << 8) | (UL(1) << 24))
 118 #define TCR_IRGN_WT             ((UL(2) << 8) | (UL(2) << 24))
 119 #define TCR_IRGN_WBnWA          ((UL(3) << 8) | (UL(3) << 24))
 120 #define TCR_IRGN_MASK           ((UL(3) << 8) | (UL(3) << 24))
 121 #define TCR_ORGN_NC             ((UL(0) << 10) | (UL(0) << 26))
 122 #define TCR_ORGN_WBWA           ((UL(1) << 10) | (UL(1) << 26))
 123 #define TCR_ORGN_WT             ((UL(2) << 10) | (UL(2) << 26))
 124 #define TCR_ORGN_WBnWA          ((UL(3) << 10) | (UL(3) << 26))
 125 #define TCR_ORGN_MASK           ((UL(3) << 10) | (UL(3) << 26))
 126 #define TCR_SHARED              ((UL(3) << 12) | (UL(3) << 28))
 127 #define TCR_TG0_4K              (UL(0) << 14)
 128 #define TCR_TG0_64K             (UL(1) << 14)
 129 #define TCR_TG0_16K             (UL(2) << 14)
 130 #define TCR_TG1_16K             (UL(1) << 30)
 131 #define TCR_TG1_4K              (UL(2) << 30)
 132 #define TCR_TG1_64K             (UL(3) << 30)
 133 #define TCR_ASID16              (UL(1) << 36)
 134 #define TCR_TBI0                (UL(1) << 37)
 135
 136 #endif