2 * Macros for accessing system registers with older binutils.
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
23 #include <linux/stringify.h>
25 #include <asm/opcodes.h>
28 * ARMv8 ARM reserves the following encoding for system registers:
29 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
30 * C5.2, version:ARM DDI 0487A.f)
37 #define sys_reg(op0, op1, crn, crm, op2) \
38 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
40 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
41 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
42 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
44 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
45 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
46 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
47 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
48 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
49 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
50 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
52 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
53 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
54 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
55 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
56 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
57 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
58 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
60 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
61 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
62 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
64 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
65 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
67 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
68 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
70 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
71 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
73 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
74 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
75 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
77 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
78 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
79 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
81 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
82 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
84 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
86 #define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\
89 /* Common SCTLR_ELx flags. */
90 #define SCTLR_ELx_EE (1 << 25)
91 #define SCTLR_ELx_I (1 << 12)
92 #define SCTLR_ELx_SA (1 << 3)
93 #define SCTLR_ELx_C (1 << 2)
94 #define SCTLR_ELx_A (1 << 1)
97 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
98 SCTLR_ELx_SA | SCTLR_ELx_I)
100 /* SCTLR_EL1 specific flags. */
101 #define SCTLR_EL1_UCI (1 << 26)
102 #define SCTLR_EL1_SPAN (1 << 23)
103 #define SCTLR_EL1_UCT (1 << 15)
104 #define SCTLR_EL1_SED (1 << 8)
105 #define SCTLR_EL1_CP15BEN (1 << 5)
108 #define ID_AA64ISAR0_RDM_SHIFT 28
109 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
110 #define ID_AA64ISAR0_CRC32_SHIFT 16
111 #define ID_AA64ISAR0_SHA2_SHIFT 12
112 #define ID_AA64ISAR0_SHA1_SHIFT 8
113 #define ID_AA64ISAR0_AES_SHIFT 4
116 #define ID_AA64PFR0_GIC_SHIFT 24
117 #define ID_AA64PFR0_ASIMD_SHIFT 20
118 #define ID_AA64PFR0_FP_SHIFT 16
119 #define ID_AA64PFR0_EL3_SHIFT 12
120 #define ID_AA64PFR0_EL2_SHIFT 8
121 #define ID_AA64PFR0_EL1_SHIFT 4
122 #define ID_AA64PFR0_EL0_SHIFT 0
124 #define ID_AA64PFR0_FP_NI 0xf
125 #define ID_AA64PFR0_FP_SUPPORTED 0x0
126 #define ID_AA64PFR0_ASIMD_NI 0xf
127 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
128 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
129 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
130 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
133 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
134 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
135 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
136 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
137 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
138 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
139 #define ID_AA64MMFR0_ASID_SHIFT 4
140 #define ID_AA64MMFR0_PARANGE_SHIFT 0
142 #define ID_AA64MMFR0_TGRAN4_NI 0xf
143 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
144 #define ID_AA64MMFR0_TGRAN64_NI 0xf
145 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
146 #define ID_AA64MMFR0_TGRAN16_NI 0x0
147 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
150 #define ID_AA64MMFR1_PAN_SHIFT 20
151 #define ID_AA64MMFR1_LOR_SHIFT 16
152 #define ID_AA64MMFR1_HPD_SHIFT 12
153 #define ID_AA64MMFR1_VHE_SHIFT 8
154 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
155 #define ID_AA64MMFR1_HADBS_SHIFT 0
157 #define ID_AA64MMFR1_VMIDBITS_8 0
158 #define ID_AA64MMFR1_VMIDBITS_16 2
161 #define ID_AA64MMFR2_LVA_SHIFT 16
162 #define ID_AA64MMFR2_IESB_SHIFT 12
163 #define ID_AA64MMFR2_LSM_SHIFT 8
164 #define ID_AA64MMFR2_UAO_SHIFT 4
165 #define ID_AA64MMFR2_CNP_SHIFT 0
168 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
169 #define ID_AA64DFR0_WRPS_SHIFT 20
170 #define ID_AA64DFR0_BRPS_SHIFT 12
171 #define ID_AA64DFR0_PMUVER_SHIFT 8
172 #define ID_AA64DFR0_TRACEVER_SHIFT 4
173 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
175 #define ID_ISAR5_RDM_SHIFT 24
176 #define ID_ISAR5_CRC32_SHIFT 16
177 #define ID_ISAR5_SHA2_SHIFT 12
178 #define ID_ISAR5_SHA1_SHIFT 8
179 #define ID_ISAR5_AES_SHIFT 4
180 #define ID_ISAR5_SEVL_SHIFT 0
182 #define MVFR0_FPROUND_SHIFT 28
183 #define MVFR0_FPSHVEC_SHIFT 24
184 #define MVFR0_FPSQRT_SHIFT 20
185 #define MVFR0_FPDIVIDE_SHIFT 16
186 #define MVFR0_FPTRAP_SHIFT 12
187 #define MVFR0_FPDP_SHIFT 8
188 #define MVFR0_FPSP_SHIFT 4
189 #define MVFR0_SIMD_SHIFT 0
191 #define MVFR1_SIMDFMAC_SHIFT 28
192 #define MVFR1_FPHP_SHIFT 24
193 #define MVFR1_SIMDHP_SHIFT 20
194 #define MVFR1_SIMDSP_SHIFT 16
195 #define MVFR1_SIMDINT_SHIFT 12
196 #define MVFR1_SIMDLS_SHIFT 8
197 #define MVFR1_FPDNAN_SHIFT 4
198 #define MVFR1_FPFTZ_SHIFT 0
201 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
202 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
203 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
205 #define ID_AA64MMFR0_TGRAN4_NI 0xf
206 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
207 #define ID_AA64MMFR0_TGRAN64_NI 0xf
208 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
209 #define ID_AA64MMFR0_TGRAN16_NI 0x0
210 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
212 #if defined(CONFIG_ARM64_4K_PAGES)
213 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
214 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
215 #elif defined(CONFIG_ARM64_16K_PAGES)
216 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
217 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
218 #elif defined(CONFIG_ARM64_64K_PAGES)
219 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
220 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
225 .irp num
,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
226 .equ
.L__reg_num_x
\num
, \num
228 .equ
.L__reg_num_xzr
, 31
230 .macro mrs_s
, rt
, sreg
231 .inst
0xd5200000|(\sreg
)|(.L__reg_num_
\rt
)
234 .macro msr_s
, sreg
, rt
235 .inst
0xd5000000|(\sreg
)|(.L__reg_num_
\rt
)
240 #include <linux/types.h>
243 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
244 " .equ .L__reg_num_x\\num, \\num\n"
246 " .equ .L__reg_num_xzr, 31\n"
248 " .macro mrs_s, rt, sreg\n"
249 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
252 " .macro msr_s, sreg, rt\n"
253 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
258 * Unlike read_cpuid, calls to read_sysreg are never expected to be
259 * optimized away or replaced with synthetic values.
261 #define read_sysreg(r) ({ \
263 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
268 * The "Z" constraint normally means a zero immediate, but when combined with
269 * the "%x0" template means XZR.
271 #define write_sysreg(v, r) do { \
272 u64 __val = (u64)v; \
273 asm volatile("msr " __stringify(r) ", %x0" \
278 * For registers without architectural names, or simply unsupported by
281 #define read_sysreg_s(r) ({ \
283 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
287 #define write_sysreg_s(v, r) do { \
288 u64 __val = (u64)v; \
289 asm volatile("msr_s " __stringify(r) ", %0" : : "rZ" (__val)); \
292 static inline void config_sctlr_el1(u32 clear
, u32 set
)
296 val
= read_sysreg(sctlr_el1
);
299 write_sysreg(val
, sctlr_el1
);
304 #endif /* __ASM_SYSREG_H */
This page took 0.050949 seconds and 6 git commands to generate.