arch/arm64/kernel/head.S

   1 /*
   2  * Low-level CPU initialisation
   3  * Based on arch/arm/kernel/head.S
   4  *
   5  * Copyright (C) 1994-2002 Russell King
   6  * Copyright (C) 2003-2012 ARM Ltd.
   7  * Authors:     Catalin Marinas <catalin.marinas@arm.com>
   8  *              Will Deacon <will.deacon@arm.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/linkage.h>
  24 #include <linux/init.h>
  25
  26 #include <asm/assembler.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/asm-offsets.h>
  29 #include <asm/cache.h>
  30 #include <asm/cputype.h>
  31 #include <asm/memory.h>
  32 #include <asm/thread_info.h>
  33 #include <asm/pgtable-hwdef.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/page.h>
  36 #include <asm/virt.h>
  37
  38 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
  39
  40 #if (TEXT_OFFSET & 0xf) != 0
  41 #error TEXT_OFFSET must be at least 16B aligned
  42 #elif (PAGE_OFFSET & 0xfffff) != 0
  43 #error PAGE_OFFSET must be at least 2MB aligned
  44 #elif TEXT_OFFSET > 0xfffff
  45 #error TEXT_OFFSET must be less than 2MB
  46 #endif
  47
  48         .macro  pgtbl, ttb0, ttb1, virt_to_phys
  49         ldr     \ttb1, =swapper_pg_dir
  50         ldr     \ttb0, =idmap_pg_dir
  51         add     \ttb1, \ttb1, \virt_to_phys
  52         add     \ttb0, \ttb0, \virt_to_phys
  53         .endm
  54
  55 #ifdef CONFIG_ARM64_64K_PAGES
  56 #define BLOCK_SHIFT     PAGE_SHIFT
  57 #define BLOCK_SIZE      PAGE_SIZE
  58 #else
  59 #define BLOCK_SHIFT     SECTION_SHIFT
  60 #define BLOCK_SIZE      SECTION_SIZE
  61 #endif
  62
  63 #define KERNEL_START    KERNEL_RAM_VADDR
  64 #define KERNEL_END      _end
  65
  66 /*
  67  * Initial memory map attributes.
  68  */
  69 #ifndef CONFIG_SMP
  70 #define PTE_FLAGS       PTE_TYPE_PAGE | PTE_AF
  71 #define PMD_FLAGS       PMD_TYPE_SECT | PMD_SECT_AF
  72 #else
  73 #define PTE_FLAGS       PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
  74 #define PMD_FLAGS       PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
  75 #endif
  76
  77 #ifdef CONFIG_ARM64_64K_PAGES
  78 #define MM_MMUFLAGS     PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
  79 #else
  80 #define MM_MMUFLAGS     PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
  81 #endif
  82
  83 /*
  84  * Kernel startup entry point.
  85  * ---------------------------
  86  *
  87  * The requirements are:
  88  *   MMU = off, D-cache = off, I-cache = on or off,
  89  *   x0 = physical address to the FDT blob.
  90  *
  91  * This code is mostly position independent so you call this at
  92  * __pa(PAGE_OFFSET + TEXT_OFFSET).
  93  *
  94  * Note that the callee-saved registers are used for storing variables
  95  * that are useful before the MMU is enabled. The allocations are described
  96  * in the entry routines.
  97  */
  98         __HEAD
  99
 100         /*
 101          * DO NOT MODIFY. Image header expected by Linux boot-loaders.
 102          */
 103 #ifdef CONFIG_EFI
 104 efi_head:
 105         /*
 106          * This add instruction has no meaningful effect except that
 107          * its opcode forms the magic "MZ" signature required by UEFI.
 108          */
 109         add     x13, x18, #0x16
 110         b       stext
 111 #else
 112         b       stext                           // branch to kernel start, magic
 113         .long   0                               // reserved
 114 #endif
 115         .quad   _kernel_offset_le               // Image load offset from start of RAM, little-endian
 116         .quad   _kernel_size_le                 // Effective size of kernel image, little-endian
 117         .quad   _kernel_flags_le                // Informative flags, little-endian
 118         .quad   0                               // reserved
 119         .quad   0                               // reserved
 120         .quad   0                               // reserved
 121         .byte   0x41                            // Magic number, "ARM\x64"
 122         .byte   0x52
 123         .byte   0x4d
 124         .byte   0x64
 125 #ifdef CONFIG_EFI
 126         .long   pe_header - efi_head            // Offset to the PE header.
 127 #else
 128         .word   0                               // reserved
 129 #endif
 130
 131 #ifdef CONFIG_EFI
 132         .align 3
 133 pe_header:
 134         .ascii  "PE"
 135         .short  0
 136 coff_header:
 137         .short  0xaa64                          // AArch64
 138         .short  2                               // nr_sections
 139         .long   0                               // TimeDateStamp
 140         .long   0                               // PointerToSymbolTable
 141         .long   1                               // NumberOfSymbols
 142         .short  section_table - optional_header // SizeOfOptionalHeader
 143         .short  0x206                           // Characteristics.
 144                                                 // IMAGE_FILE_DEBUG_STRIPPED |
 145                                                 // IMAGE_FILE_EXECUTABLE_IMAGE |
 146                                                 // IMAGE_FILE_LINE_NUMS_STRIPPED
 147 optional_header:
 148         .short  0x20b                           // PE32+ format
 149         .byte   0x02                            // MajorLinkerVersion
 150         .byte   0x14                            // MinorLinkerVersion
 151         .long   _edata - stext                  // SizeOfCode
 152         .long   0                               // SizeOfInitializedData
 153         .long   0                               // SizeOfUninitializedData
 154         .long   efi_stub_entry - efi_head       // AddressOfEntryPoint
 155         .long   stext - efi_head                // BaseOfCode
 156
 157 extra_header_fields:
 158         .quad   0                               // ImageBase
 159         .long   0x20                            // SectionAlignment
 160         .long   0x8                             // FileAlignment
 161         .short  0                               // MajorOperatingSystemVersion
 162         .short  0                               // MinorOperatingSystemVersion
 163         .short  0                               // MajorImageVersion
 164         .short  0                               // MinorImageVersion
 165         .short  0                               // MajorSubsystemVersion
 166         .short  0                               // MinorSubsystemVersion
 167         .long   0                               // Win32VersionValue
 168
 169         .long   _edata - efi_head               // SizeOfImage
 170
 171         // Everything before the kernel image is considered part of the header
 172         .long   stext - efi_head                // SizeOfHeaders
 173         .long   0                               // CheckSum
 174         .short  0xa                             // Subsystem (EFI application)
 175         .short  0                               // DllCharacteristics
 176         .quad   0                               // SizeOfStackReserve
 177         .quad   0                               // SizeOfStackCommit
 178         .quad   0                               // SizeOfHeapReserve
 179         .quad   0                               // SizeOfHeapCommit
 180         .long   0                               // LoaderFlags
 181         .long   0x6                             // NumberOfRvaAndSizes
 182
 183         .quad   0                               // ExportTable
 184         .quad   0                               // ImportTable
 185         .quad   0                               // ResourceTable
 186         .quad   0                               // ExceptionTable
 187         .quad   0                               // CertificationTable
 188         .quad   0                               // BaseRelocationTable
 189
 190         // Section table
 191 section_table:
 192
 193         /*
 194          * The EFI application loader requires a relocation section
 195          * because EFI applications must be relocatable.  This is a
 196          * dummy section as far as we are concerned.
 197          */
 198         .ascii  ".reloc"
 199         .byte   0
 200         .byte   0                       // end of 0 padding of section name
 201         .long   0
 202         .long   0
 203         .long   0                       // SizeOfRawData
 204         .long   0                       // PointerToRawData
 205         .long   0                       // PointerToRelocations
 206         .long   0                       // PointerToLineNumbers
 207         .short  0                       // NumberOfRelocations
 208         .short  0                       // NumberOfLineNumbers
 209         .long   0x42100040              // Characteristics (section flags)
 210
 211
 212         .ascii  ".text"
 213         .byte   0
 214         .byte   0
 215         .byte   0                       // end of 0 padding of section name
 216         .long   _edata - stext          // VirtualSize
 217         .long   stext - efi_head        // VirtualAddress
 218         .long   _edata - stext          // SizeOfRawData
 219         .long   stext - efi_head        // PointerToRawData
 220
 221         .long   0               // PointerToRelocations (0 for executables)
 222         .long   0               // PointerToLineNumbers (0 for executables)
 223         .short  0               // NumberOfRelocations  (0 for executables)
 224         .short  0               // NumberOfLineNumbers  (0 for executables)
 225         .long   0xe0500020      // Characteristics (section flags)
 226         .align 5
 227 #endif
 228
 229 ENTRY(stext)
 230         mov     x21, x0                         // x21=FDT
 231         bl      el2_setup                       // Drop to EL1, w20=cpu_boot_mode
 232         bl      __calc_phys_offset              // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
 233         bl      set_cpu_boot_mode_flag
 234         mrs     x22, midr_el1                   // x22=cpuid
 235         mov     x0, x22
 236         bl      lookup_processor_type
 237         mov     x23, x0                         // x23=current cpu_table
 238         cbz     x23, __error_p                  // invalid processor (x23=0)?
 239         bl      __vet_fdt
 240         bl      __create_page_tables            // x25=TTBR0, x26=TTBR1
 241         /*
 242          * The following calls CPU specific code in a position independent
 243          * manner. See arch/arm64/mm/proc.S for details. x23 = base of
 244          * cpu_info structure selected by lookup_processor_type above.
 245          * On return, the CPU will be ready for the MMU to be turned on and
 246          * the TCR will have been set.
 247          */
 248         ldr     x27, __switch_data              // address to jump to after
 249                                                 // MMU has been enabled
 250         adr     lr, __enable_mmu                // return (PIC) address
 251         ldr     x12, [x23, #CPU_INFO_SETUP]
 252         add     x12, x12, x28                   // __virt_to_phys
 253         br      x12                             // initialise processor
 254 ENDPROC(stext)
 255
 256 /*
 257  * If we're fortunate enough to boot at EL2, ensure that the world is
 258  * sane before dropping to EL1.
 259  *
 260  * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
 261  * booted in EL1 or EL2 respectively.
 262  */
 263 ENTRY(el2_setup)
 264         mrs     x0, CurrentEL
 265         cmp     x0, #CurrentEL_EL2
 266         b.ne    1f
 267         mrs     x0, sctlr_el2
 268 CPU_BE( orr     x0, x0, #(1 << 25)      )       // Set the EE bit for EL2
 269 CPU_LE( bic     x0, x0, #(1 << 25)      )       // Clear the EE bit for EL2
 270         msr     sctlr_el2, x0
 271         b       2f
 272 1:      mrs     x0, sctlr_el1
 273 CPU_BE( orr     x0, x0, #(3 << 24)      )       // Set the EE and E0E bits for EL1
 274 CPU_LE( bic     x0, x0, #(3 << 24)      )       // Clear the EE and E0E bits for EL1
 275         msr     sctlr_el1, x0
 276         mov     w20, #BOOT_CPU_MODE_EL1         // This cpu booted in EL1
 277         isb
 278         ret
 279
 280         /* Hyp configuration. */
 281 2:      mov     x0, #(1 << 31)                  // 64-bit EL1
 282         msr     hcr_el2, x0
 283
 284         /* Generic timers. */
 285         mrs     x0, cnthctl_el2
 286         orr     x0, x0, #3                      // Enable EL1 physical timers
 287         msr     cnthctl_el2, x0
 288         msr     cntvoff_el2, xzr                // Clear virtual offset
 289
 290         /* Populate ID registers. */
 291         mrs     x0, midr_el1
 292         mrs     x1, mpidr_el1
 293         msr     vpidr_el2, x0
 294         msr     vmpidr_el2, x1
 295
 296         /* sctlr_el1 */
 297         mov     x0, #0x0800                     // Set/clear RES{1,0} bits
 298 CPU_BE( movk    x0, #0x33d0, lsl #16    )       // Set EE and E0E on BE systems
 299 CPU_LE( movk    x0, #0x30d0, lsl #16    )       // Clear EE and E0E on LE systems
 300         msr     sctlr_el1, x0
 301
 302         /* Coprocessor traps. */
 303         mov     x0, #0x33ff
 304         msr     cptr_el2, x0                    // Disable copro. traps to EL2
 305
 306 #ifdef CONFIG_COMPAT
 307         msr     hstr_el2, xzr                   // Disable CP15 traps to EL2
 308 #endif
 309
 310         /* Stage-2 translation */
 311         msr     vttbr_el2, xzr
 312
 313         /* Hypervisor stub */
 314         adr     x0, __hyp_stub_vectors
 315         msr     vbar_el2, x0
 316
 317         /* spsr */
 318         mov     x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
 319                       PSR_MODE_EL1h)
 320         msr     spsr_el2, x0
 321         msr     elr_el2, lr
 322         mov     w20, #BOOT_CPU_MODE_EL2         // This CPU booted in EL2
 323         eret
 324 ENDPROC(el2_setup)
 325
 326 /*
 327  * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
 328  * in x20. See arch/arm64/include/asm/virt.h for more info.
 329  */
 330 ENTRY(set_cpu_boot_mode_flag)
 331         ldr     x1, =__boot_cpu_mode            // Compute __boot_cpu_mode
 332         add     x1, x1, x28
 333         cmp     w20, #BOOT_CPU_MODE_EL2
 334         b.ne    1f
 335         add     x1, x1, #4
 336 1:      str     w20, [x1]                       // This CPU has booted in EL1
 337         dmb     sy
 338         dc      ivac, x1                        // Invalidate potentially stale cache line
 339         ret
 340 ENDPROC(set_cpu_boot_mode_flag)
 341
 342 /*
 343  * We need to find out the CPU boot mode long after boot, so we need to
 344  * store it in a writable variable.
 345  *
 346  * This is not in .bss, because we set it sufficiently early that the boot-time
 347  * zeroing of .bss would clobber it.
 348  */
 349         .pushsection    .data..cacheline_aligned
 350 ENTRY(__boot_cpu_mode)
 351         .align  L1_CACHE_SHIFT
 352         .long   BOOT_CPU_MODE_EL2
 353         .long   0
 354         .popsection
 355
 356         .align  3
 357 2:      .quad   .
 358         .quad   PAGE_OFFSET
 359
 360 #ifdef CONFIG_SMP
 361         .align  3
 362 1:      .quad   .
 363         .quad   secondary_holding_pen_release
 364
 365         /*
 366          * This provides a "holding pen" for platforms to hold all secondary
 367          * cores are held until we're ready for them to initialise.
 368          */
 369 ENTRY(secondary_holding_pen)
 370         bl      el2_setup                       // Drop to EL1, w20=cpu_boot_mode
 371         bl      __calc_phys_offset              // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
 372         bl      set_cpu_boot_mode_flag
 373         mrs     x0, mpidr_el1
 374         ldr     x1, =MPIDR_HWID_BITMASK
 375         and     x0, x0, x1
 376         adr     x1, 1b
 377         ldp     x2, x3, [x1]
 378         sub     x1, x1, x2
 379         add     x3, x3, x1
 380 pen:    ldr     x4, [x3]
 381         cmp     x4, x0
 382         b.eq    secondary_startup
 383         wfe
 384         b       pen
 385 ENDPROC(secondary_holding_pen)
 386
 387         /*
 388          * Secondary entry point that jumps straight into the kernel. Only to
 389          * be used where CPUs are brought online dynamically by the kernel.
 390          */
 391 ENTRY(secondary_entry)
 392         bl      el2_setup                       // Drop to EL1
 393         bl      __calc_phys_offset              // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
 394         bl      set_cpu_boot_mode_flag
 395         b       secondary_startup
 396 ENDPROC(secondary_entry)
 397
 398 ENTRY(secondary_startup)
 399         /*
 400          * Common entry point for secondary CPUs.
 401          */
 402         mrs     x22, midr_el1                   // x22=cpuid
 403         mov     x0, x22
 404         bl      lookup_processor_type
 405         mov     x23, x0                         // x23=current cpu_table
 406         cbz     x23, __error_p                  // invalid processor (x23=0)?
 407
 408         pgtbl   x25, x26, x28                   // x25=TTBR0, x26=TTBR1
 409         ldr     x12, [x23, #CPU_INFO_SETUP]
 410         add     x12, x12, x28                   // __virt_to_phys
 411         blr     x12                             // initialise processor
 412
 413         ldr     x21, =secondary_data
 414         ldr     x27, =__secondary_switched      // address to jump to after enabling the MMU
 415         b       __enable_mmu
 416 ENDPROC(secondary_startup)
 417
 418 ENTRY(__secondary_switched)
 419         ldr     x0, [x21]                       // get secondary_data.stack
 420         mov     sp, x0
 421         mov     x29, #0
 422         b       secondary_start_kernel
 423 ENDPROC(__secondary_switched)
 424 #endif  /* CONFIG_SMP */
 425
 426 /*
 427  * Setup common bits before finally enabling the MMU. Essentially this is just
 428  * loading the page table pointer and vector base registers.
 429  *
 430  * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
 431  * the MMU.
 432  */
 433 __enable_mmu:
 434         ldr     x5, =vectors
 435         msr     vbar_el1, x5
 436         msr     ttbr0_el1, x25                  // load TTBR0
 437         msr     ttbr1_el1, x26                  // load TTBR1
 438         isb
 439         b       __turn_mmu_on
 440 ENDPROC(__enable_mmu)
 441
 442 /*
 443  * Enable the MMU. This completely changes the structure of the visible memory
 444  * space. You will not be able to trace execution through this.
 445  *
 446  *  x0  = system control register
 447  *  x27 = *virtual* address to jump to upon completion
 448  *
 449  * other registers depend on the function called upon completion
 450  *
 451  * We align the entire function to the smallest power of two larger than it to
 452  * ensure it fits within a single block map entry. Otherwise were PHYS_OFFSET
 453  * close to the end of a 512MB or 1GB block we might require an additional
 454  * table to map the entire function.
 455  */
 456         .align  4
 457 __turn_mmu_on:
 458         msr     sctlr_el1, x0
 459         isb
 460         br      x27
 461 ENDPROC(__turn_mmu_on)
 462
 463 /*
 464  * Calculate the start of physical memory.
 465  */
 466 __calc_phys_offset:
 467         adr     x0, 1f
 468         ldp     x1, x2, [x0]
 469         sub     x28, x0, x1                     // x28 = PHYS_OFFSET - PAGE_OFFSET
 470         add     x24, x2, x28                    // x24 = PHYS_OFFSET
 471         ret
 472 ENDPROC(__calc_phys_offset)
 473
 474         .align 3
 475 1:      .quad   .
 476         .quad   PAGE_OFFSET
 477
 478 /*
 479  * Macro to populate the PGD for the corresponding block entry in the next
 480  * level (tbl) for the given virtual address.
 481  *
 482  * Preserves:   pgd, tbl, virt
 483  * Corrupts:    tmp1, tmp2
 484  */
 485         .macro  create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
 486         lsr     \tmp1, \virt, #PGDIR_SHIFT
 487         and     \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
 488         orr     \tmp2, \tbl, #3                 // PGD entry table type
 489         str     \tmp2, [\pgd, \tmp1, lsl #3]
 490         .endm
 491
 492 /*
 493  * Macro to populate block entries in the page table for the start..end
 494  * virtual range (inclusive).
 495  *
 496  * Preserves:   tbl, flags
 497  * Corrupts:    phys, start, end, pstate
 498  */
 499         .macro  create_block_map, tbl, flags, phys, start, end
 500         lsr     \phys, \phys, #BLOCK_SHIFT
 501         lsr     \start, \start, #BLOCK_SHIFT
 502         and     \start, \start, #PTRS_PER_PTE - 1       // table index
 503         orr     \phys, \flags, \phys, lsl #BLOCK_SHIFT  // table entry
 504         lsr     \end, \end, #BLOCK_SHIFT
 505         and     \end, \end, #PTRS_PER_PTE - 1           // table end index
 506 9999:   str     \phys, [\tbl, \start, lsl #3]           // store the entry
 507         add     \start, \start, #1                      // next entry
 508         add     \phys, \phys, #BLOCK_SIZE               // next block
 509         cmp     \start, \end
 510         b.ls    9999b
 511         .endm
 512
 513 /*
 514  * Setup the initial page tables. We only setup the barest amount which is
 515  * required to get the kernel running. The following sections are required:
 516  *   - identity mapping to enable the MMU (low address, TTBR0)
 517  *   - first few MB of the kernel linear mapping to jump to once the MMU has
 518  *     been enabled, including the FDT blob (TTBR1)
 519  *   - pgd entry for fixed mappings (TTBR1)
 520  */
 521 __create_page_tables:
 522         pgtbl   x25, x26, x28                   // idmap_pg_dir and swapper_pg_dir addresses
 523         mov     x27, lr
 524
 525         /*
 526          * Invalidate the idmap and swapper page tables to avoid potential
 527          * dirty cache lines being evicted.
 528          */
 529         mov     x0, x25
 530         add     x1, x26, #SWAPPER_DIR_SIZE
 531         bl      __inval_cache_range
 532
 533         /*
 534          * Clear the idmap and swapper page tables.
 535          */
 536         mov     x0, x25
 537         add     x6, x26, #SWAPPER_DIR_SIZE
 538 1:      stp     xzr, xzr, [x0], #16
 539         stp     xzr, xzr, [x0], #16
 540         stp     xzr, xzr, [x0], #16
 541         stp     xzr, xzr, [x0], #16
 542         cmp     x0, x6
 543         b.lo    1b
 544
 545         ldr     x7, =MM_MMUFLAGS
 546
 547         /*
 548          * Create the identity mapping.
 549          */
 550         add     x0, x25, #PAGE_SIZE             // section table address
 551         ldr     x3, =KERNEL_START
 552         add     x3, x3, x28                     // __pa(KERNEL_START)
 553         create_pgd_entry x25, x0, x3, x5, x6
 554         ldr     x6, =KERNEL_END
 555         mov     x5, x3                          // __pa(KERNEL_START)
 556         add     x6, x6, x28                     // __pa(KERNEL_END)
 557         create_block_map x0, x7, x3, x5, x6
 558
 559         /*
 560          * Map the kernel image (starting with PHYS_OFFSET).
 561          */
 562         add     x0, x26, #PAGE_SIZE             // section table address
 563         mov     x5, #PAGE_OFFSET
 564         create_pgd_entry x26, x0, x5, x3, x6
 565         ldr     x6, =KERNEL_END
 566         mov     x3, x24                         // phys offset
 567         create_block_map x0, x7, x3, x5, x6
 568
 569         /*
 570          * Map the FDT blob (maximum 2MB; must be within 512MB of
 571          * PHYS_OFFSET).
 572          */
 573         mov     x3, x21                         // FDT phys address
 574         and     x3, x3, #~((1 << 21) - 1)       // 2MB aligned
 575         mov     x6, #PAGE_OFFSET
 576         sub     x5, x3, x24                     // subtract PHYS_OFFSET
 577         tst     x5, #~((1 << 29) - 1)           // within 512MB?
 578         csel    x21, xzr, x21, ne               // zero the FDT pointer
 579         b.ne    1f
 580         add     x5, x5, x6                      // __va(FDT blob)
 581         add     x6, x5, #1 << 21                // 2MB for the FDT blob
 582         sub     x6, x6, #1                      // inclusive range
 583         create_block_map x0, x7, x3, x5, x6
 584 1:
 585         /*
 586          * Create the pgd entry for the fixed mappings.
 587          */
 588         ldr     x5, =FIXADDR_TOP                // Fixed mapping virtual address
 589         add     x0, x26, #2 * PAGE_SIZE         // section table address
 590         create_pgd_entry x26, x0, x5, x6, x7
 591
 592         /*
 593          * Since the page tables have been populated with non-cacheable
 594          * accesses (MMU disabled), invalidate the idmap and swapper page
 595          * tables again to remove any speculatively loaded cache lines.
 596          */
 597         mov     x0, x25
 598         add     x1, x26, #SWAPPER_DIR_SIZE
 599         bl      __inval_cache_range
 600
 601         mov     lr, x27
 602         ret
 603 ENDPROC(__create_page_tables)
 604         .ltorg
 605
 606         .align  3
 607         .type   __switch_data, %object
 608 __switch_data:
 609         .quad   __mmap_switched
 610         .quad   __bss_start                     // x6
 611         .quad   __bss_stop                      // x7
 612         .quad   processor_id                    // x4
 613         .quad   __fdt_pointer                   // x5
 614         .quad   memstart_addr                   // x6
 615         .quad   init_thread_union + THREAD_START_SP // sp
 616
 617 /*
 618  * The following fragment of code is executed with the MMU on in MMU mode, and
 619  * uses absolute addresses; this is not position independent.
 620  */
 621 __mmap_switched:
 622         adr     x3, __switch_data + 8
 623
 624         ldp     x6, x7, [x3], #16
 625 1:      cmp     x6, x7
 626         b.hs    2f
 627         str     xzr, [x6], #8                   // Clear BSS
 628         b       1b
 629 2:
 630         ldp     x4, x5, [x3], #16
 631         ldr     x6, [x3], #8
 632         ldr     x16, [x3]
 633         mov     sp, x16
 634         str     x22, [x4]                       // Save processor ID
 635         str     x21, [x5]                       // Save FDT pointer
 636         str     x24, [x6]                       // Save PHYS_OFFSET
 637         mov     x29, #0
 638         b       start_kernel
 639 ENDPROC(__mmap_switched)
 640
 641 /*
 642  * Exception handling. Something went wrong and we can't proceed. We ought to
 643  * tell the user, but since we don't have any guarantee that we're even
 644  * running on the right architecture, we do virtually nothing.
 645  */
 646 __error_p:
 647 ENDPROC(__error_p)
 648
 649 __error:
 650 1:      nop
 651         b       1b
 652 ENDPROC(__error)
 653
 654 /*
 655  * This function gets the processor ID in w0 and searches the cpu_table[] for
 656  * a match. It returns a pointer to the struct cpu_info it found. The
 657  * cpu_table[] must end with an empty (all zeros) structure.
 658  *
 659  * This routine can be called via C code and it needs to work with the MMU
 660  * both disabled and enabled (the offset is calculated automatically).
 661  */
 662 ENTRY(lookup_processor_type)
 663         adr     x1, __lookup_processor_type_data
 664         ldp     x2, x3, [x1]
 665         sub     x1, x1, x2                      // get offset between VA and PA
 666         add     x3, x3, x1                      // convert VA to PA
 667 1:
 668         ldp     w5, w6, [x3]                    // load cpu_id_val and cpu_id_mask
 669         cbz     w5, 2f                          // end of list?
 670         and     w6, w6, w0
 671         cmp     w5, w6
 672         b.eq    3f
 673         add     x3, x3, #CPU_INFO_SZ
 674         b       1b
 675 2:
 676         mov     x3, #0                          // unknown processor
 677 3:
 678         mov     x0, x3
 679         ret
 680 ENDPROC(lookup_processor_type)
 681
 682         .align  3
 683         .type   __lookup_processor_type_data, %object
 684 __lookup_processor_type_data:
 685         .quad   .
 686         .quad   cpu_table
 687         .size   __lookup_processor_type_data, . - __lookup_processor_type_data
 688
 689 /*
 690  * Determine validity of the x21 FDT pointer.
 691  * The dtb must be 8-byte aligned and live in the first 512M of memory.
 692  */
 693 __vet_fdt:
 694         tst     x21, #0x7
 695         b.ne    1f
 696         cmp     x21, x24
 697         b.lt    1f
 698         mov     x0, #(1 << 29)
 699         add     x0, x0, x24
 700         cmp     x21, x0
 701         b.ge    1f
 702         ret
 703 1:
 704         mov     x21, #0
 705         ret
 706 ENDPROC(__vet_fdt)