2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <linux/kvm_host.h>
25 #include <linux/uaccess.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_host.h>
28 #include <asm/kvm_emulate.h>
29 #include <asm/kvm_coproc.h>
30 #include <asm/cacheflush.h>
31 #include <asm/cputype.h>
32 #include <trace/events/kvm.h>
37 * All of this file is extremly similar to the ARM coproc.c, but the
38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
47 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
48 static u32 cache_levels
;
50 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
53 /* Which cache CCSIDR represents depends on CSSELR value. */
54 static u32
get_ccsidr(u32 csselr
)
58 /* Make sure noone else changes CSSELR during this! */
60 /* Put value into CSSELR */
61 asm volatile("msr csselr_el1, %x0" : : "r" (csselr
));
63 /* Read result out of CCSIDR */
64 asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr
));
70 static void do_dc_cisw(u32 val
)
72 asm volatile("dc cisw, %x0" : : "r" (val
));
76 static void do_dc_csw(u32 val
)
78 asm volatile("dc csw, %x0" : : "r" (val
));
82 /* See note at ARM ARM B1.14.4 */
83 static bool access_dcsw(struct kvm_vcpu
*vcpu
,
84 const struct sys_reg_params
*p
,
85 const struct sys_reg_desc
*r
)
91 return read_from_write_only(vcpu
, p
);
95 cpumask_setall(&vcpu
->arch
.require_dcache_flush
);
96 cpumask_clear_cpu(cpu
, &vcpu
->arch
.require_dcache_flush
);
98 /* If we were already preempted, take the long way around */
99 if (cpu
!= vcpu
->arch
.last_pcpu
) {
104 val
= *vcpu_reg(vcpu
, p
->Rt
);
107 case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
108 case 14: /* DCCISW */
124 * Generic accessor for VM registers. Only called as long as HCR_TVM
127 static bool access_vm_reg(struct kvm_vcpu
*vcpu
,
128 const struct sys_reg_params
*p
,
129 const struct sys_reg_desc
*r
)
133 BUG_ON(!p
->is_write
);
135 val
= *vcpu_reg(vcpu
, p
->Rt
);
136 if (!p
->is_aarch32
) {
137 vcpu_sys_reg(vcpu
, r
->reg
) = val
;
139 vcpu_cp15(vcpu
, r
->reg
) = val
& 0xffffffffUL
;
141 vcpu_cp15(vcpu
, r
->reg
+ 1) = val
>> 32;
147 * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set. If the
148 * guest enables the MMU, we stop trapping the VM sys_regs and leave
149 * it in complete control of the caches.
151 static bool access_sctlr(struct kvm_vcpu
*vcpu
,
152 const struct sys_reg_params
*p
,
153 const struct sys_reg_desc
*r
)
155 access_vm_reg(vcpu
, p
, r
);
157 if (vcpu_has_cache_enabled(vcpu
)) /* MMU+Caches enabled? */
158 vcpu
->arch
.hcr_el2
&= ~HCR_TVM
;
164 * We could trap ID_DFR0 and tell the guest we don't support performance
165 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
166 * NAKed, so it will read the PMCR anyway.
168 * Therefore we tell the guest we have 0 counters. Unfortunately, we
169 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
170 * all PM registers, which doesn't crash the guest kernel at least.
172 static bool pm_fake(struct kvm_vcpu
*vcpu
,
173 const struct sys_reg_params
*p
,
174 const struct sys_reg_desc
*r
)
177 return ignore_write(vcpu
, p
);
179 return read_zero(vcpu
, p
);
182 static void reset_amair_el1(struct kvm_vcpu
*vcpu
, const struct sys_reg_desc
*r
)
186 asm volatile("mrs %0, amair_el1\n" : "=r" (amair
));
187 vcpu_sys_reg(vcpu
, AMAIR_EL1
) = amair
;
190 static void reset_mpidr(struct kvm_vcpu
*vcpu
, const struct sys_reg_desc
*r
)
193 * Simply map the vcpu_id into the Aff0 field of the MPIDR.
195 vcpu_sys_reg(vcpu
, MPIDR_EL1
) = (1UL << 31) | (vcpu
->vcpu_id
& 0xff);
199 * Architected system registers.
200 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
202 static const struct sys_reg_desc sys_reg_descs
[] = {
204 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
207 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
210 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
214 { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
215 NULL
, reset_val
, TEECR32_EL1
, 0 },
217 { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
218 NULL
, reset_val
, TEEHBR32_EL1
, 0 },
220 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
221 NULL
, reset_val
, DBGVCR32_EL2
, 0 },
224 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
225 NULL
, reset_mpidr
, MPIDR_EL1
},
227 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
228 access_sctlr
, reset_val
, SCTLR_EL1
, 0x00C50078 },
230 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
231 NULL
, reset_val
, CPACR_EL1
, 0 },
233 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
234 access_vm_reg
, reset_unknown
, TTBR0_EL1
},
236 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
237 access_vm_reg
, reset_unknown
, TTBR1_EL1
},
239 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
240 access_vm_reg
, reset_val
, TCR_EL1
, 0 },
243 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
244 access_vm_reg
, reset_unknown
, AFSR0_EL1
},
246 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
247 access_vm_reg
, reset_unknown
, AFSR1_EL1
},
249 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
250 access_vm_reg
, reset_unknown
, ESR_EL1
},
252 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
253 access_vm_reg
, reset_unknown
, FAR_EL1
},
255 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
256 NULL
, reset_unknown
, PAR_EL1
},
259 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
262 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
266 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
267 access_vm_reg
, reset_unknown
, MAIR_EL1
},
269 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
270 access_vm_reg
, reset_amair_el1
, AMAIR_EL1
},
273 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
274 NULL
, reset_val
, VBAR_EL1
, 0 },
276 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
277 access_vm_reg
, reset_val
, CONTEXTIDR_EL1
, 0 },
279 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
280 NULL
, reset_unknown
, TPIDR_EL1
},
283 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
284 NULL
, reset_val
, CNTKCTL_EL1
, 0},
287 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
288 NULL
, reset_unknown
, CSSELR_EL1
},
291 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
294 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
297 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
300 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
303 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
306 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
309 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
312 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
315 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
318 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
321 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
324 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
327 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
331 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
332 NULL
, reset_unknown
, TPIDR_EL0
},
334 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
335 NULL
, reset_unknown
, TPIDRRO_EL0
},
338 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
339 NULL
, reset_unknown
, DACR32_EL2
},
341 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
342 NULL
, reset_unknown
, IFSR32_EL2
},
344 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
345 NULL
, reset_val
, FPEXC32_EL2
, 0x70 },
349 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
350 * depending on the way they are accessed (as a 32bit or a 64bit
353 static const struct sys_reg_desc cp15_regs
[] = {
354 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg
, NULL
, c2_TTBR0
},
355 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr
, NULL
, c1_SCTLR
},
356 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg
, NULL
, c2_TTBR0
},
357 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg
, NULL
, c2_TTBR1
},
358 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg
, NULL
, c2_TTBCR
},
359 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg
, NULL
, c3_DACR
},
360 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg
, NULL
, c5_DFSR
},
361 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg
, NULL
, c5_IFSR
},
362 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg
, NULL
, c5_ADFSR
},
363 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg
, NULL
, c5_AIFSR
},
364 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg
, NULL
, c6_DFAR
},
365 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg
, NULL
, c6_IFAR
},
368 * DC{C,I,CI}SW operations:
370 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw
},
371 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw
},
372 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw
},
374 { Op1( 0), CRn( 9), CRm(12), Op2( 0), pm_fake
},
375 { Op1( 0), CRn( 9), CRm(12), Op2( 1), pm_fake
},
376 { Op1( 0), CRn( 9), CRm(12), Op2( 2), pm_fake
},
377 { Op1( 0), CRn( 9), CRm(12), Op2( 3), pm_fake
},
378 { Op1( 0), CRn( 9), CRm(12), Op2( 5), pm_fake
},
379 { Op1( 0), CRn( 9), CRm(12), Op2( 6), pm_fake
},
380 { Op1( 0), CRn( 9), CRm(12), Op2( 7), pm_fake
},
381 { Op1( 0), CRn( 9), CRm(13), Op2( 0), pm_fake
},
382 { Op1( 0), CRn( 9), CRm(13), Op2( 1), pm_fake
},
383 { Op1( 0), CRn( 9), CRm(13), Op2( 2), pm_fake
},
384 { Op1( 0), CRn( 9), CRm(14), Op2( 0), pm_fake
},
385 { Op1( 0), CRn( 9), CRm(14), Op2( 1), pm_fake
},
386 { Op1( 0), CRn( 9), CRm(14), Op2( 2), pm_fake
},
388 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg
, NULL
, c10_PRRR
},
389 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg
, NULL
, c10_NMRR
},
390 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg
, NULL
, c10_AMAIR0
},
391 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg
, NULL
, c10_AMAIR1
},
392 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg
, NULL
, c13_CID
},
394 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg
, NULL
, c2_TTBR1
},
397 /* Target specific emulation tables */
398 static struct kvm_sys_reg_target_table
*target_tables
[KVM_ARM_NUM_TARGETS
];
400 void kvm_register_target_sys_reg_table(unsigned int target
,
401 struct kvm_sys_reg_target_table
*table
)
403 target_tables
[target
] = table
;
406 /* Get specific register table for this target. */
407 static const struct sys_reg_desc
*get_target_table(unsigned target
,
411 struct kvm_sys_reg_target_table
*table
;
413 table
= target_tables
[target
];
415 *num
= table
->table64
.num
;
416 return table
->table64
.table
;
418 *num
= table
->table32
.num
;
419 return table
->table32
.table
;
423 static const struct sys_reg_desc
*find_reg(const struct sys_reg_params
*params
,
424 const struct sys_reg_desc table
[],
429 for (i
= 0; i
< num
; i
++) {
430 const struct sys_reg_desc
*r
= &table
[i
];
432 if (params
->Op0
!= r
->Op0
)
434 if (params
->Op1
!= r
->Op1
)
436 if (params
->CRn
!= r
->CRn
)
438 if (params
->CRm
!= r
->CRm
)
440 if (params
->Op2
!= r
->Op2
)
448 int kvm_handle_cp14_load_store(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
450 kvm_inject_undefined(vcpu
);
454 int kvm_handle_cp14_access(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
456 kvm_inject_undefined(vcpu
);
460 static void emulate_cp15(struct kvm_vcpu
*vcpu
,
461 const struct sys_reg_params
*params
)
464 const struct sys_reg_desc
*table
, *r
;
466 table
= get_target_table(vcpu
->arch
.target
, false, &num
);
468 /* Search target-specific then generic table. */
469 r
= find_reg(params
, table
, num
);
471 r
= find_reg(params
, cp15_regs
, ARRAY_SIZE(cp15_regs
));
475 * Not having an accessor means that we have
476 * configured a trap that we don't know how to
477 * handle. This certainly qualifies as a gross bug
478 * that should be fixed right away.
482 if (likely(r
->access(vcpu
, params
, r
))) {
483 /* Skip instruction, since it was emulated */
484 kvm_skip_instr(vcpu
, kvm_vcpu_trap_il_is32bit(vcpu
));
487 /* If access function fails, it should complain. */
490 kvm_err("Unsupported guest CP15 access at: %08lx\n", *vcpu_pc(vcpu
));
491 print_sys_reg_instr(params
);
492 kvm_inject_undefined(vcpu
);
496 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
497 * @vcpu: The VCPU pointer
498 * @run: The kvm_run struct
500 int kvm_handle_cp15_64(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
502 struct sys_reg_params params
;
503 u32 hsr
= kvm_vcpu_get_hsr(vcpu
);
504 int Rt2
= (hsr
>> 10) & 0xf;
506 params
.is_aarch32
= true;
507 params
.is_32bit
= false;
508 params
.CRm
= (hsr
>> 1) & 0xf;
509 params
.Rt
= (hsr
>> 5) & 0xf;
510 params
.is_write
= ((hsr
& 1) == 0);
513 params
.Op1
= (hsr
>> 16) & 0xf;
518 * Massive hack here. Store Rt2 in the top 32bits so we only
519 * have one register to deal with. As we use the same trap
520 * backends between AArch32 and AArch64, we get away with it.
522 if (params
.is_write
) {
523 u64 val
= *vcpu_reg(vcpu
, params
.Rt
);
525 val
|= *vcpu_reg(vcpu
, Rt2
) << 32;
526 *vcpu_reg(vcpu
, params
.Rt
) = val
;
529 emulate_cp15(vcpu
, ¶ms
);
531 /* Do the opposite hack for the read side */
532 if (!params
.is_write
) {
533 u64 val
= *vcpu_reg(vcpu
, params
.Rt
);
535 *vcpu_reg(vcpu
, Rt2
) = val
;
542 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
543 * @vcpu: The VCPU pointer
544 * @run: The kvm_run struct
546 int kvm_handle_cp15_32(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
548 struct sys_reg_params params
;
549 u32 hsr
= kvm_vcpu_get_hsr(vcpu
);
551 params
.is_aarch32
= true;
552 params
.is_32bit
= true;
553 params
.CRm
= (hsr
>> 1) & 0xf;
554 params
.Rt
= (hsr
>> 5) & 0xf;
555 params
.is_write
= ((hsr
& 1) == 0);
556 params
.CRn
= (hsr
>> 10) & 0xf;
558 params
.Op1
= (hsr
>> 14) & 0x7;
559 params
.Op2
= (hsr
>> 17) & 0x7;
561 emulate_cp15(vcpu
, ¶ms
);
565 static int emulate_sys_reg(struct kvm_vcpu
*vcpu
,
566 const struct sys_reg_params
*params
)
569 const struct sys_reg_desc
*table
, *r
;
571 table
= get_target_table(vcpu
->arch
.target
, true, &num
);
573 /* Search target-specific then generic table. */
574 r
= find_reg(params
, table
, num
);
576 r
= find_reg(params
, sys_reg_descs
, ARRAY_SIZE(sys_reg_descs
));
580 * Not having an accessor means that we have
581 * configured a trap that we don't know how to
582 * handle. This certainly qualifies as a gross bug
583 * that should be fixed right away.
587 if (likely(r
->access(vcpu
, params
, r
))) {
588 /* Skip instruction, since it was emulated */
589 kvm_skip_instr(vcpu
, kvm_vcpu_trap_il_is32bit(vcpu
));
592 /* If access function fails, it should complain. */
594 kvm_err("Unsupported guest sys_reg access at: %lx\n",
596 print_sys_reg_instr(params
);
598 kvm_inject_undefined(vcpu
);
602 static void reset_sys_reg_descs(struct kvm_vcpu
*vcpu
,
603 const struct sys_reg_desc
*table
, size_t num
)
607 for (i
= 0; i
< num
; i
++)
609 table
[i
].reset(vcpu
, &table
[i
]);
613 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
614 * @vcpu: The VCPU pointer
615 * @run: The kvm_run struct
617 int kvm_handle_sys_reg(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
619 struct sys_reg_params params
;
620 unsigned long esr
= kvm_vcpu_get_hsr(vcpu
);
622 params
.is_aarch32
= false;
623 params
.is_32bit
= false;
624 params
.Op0
= (esr
>> 20) & 3;
625 params
.Op1
= (esr
>> 14) & 0x7;
626 params
.CRn
= (esr
>> 10) & 0xf;
627 params
.CRm
= (esr
>> 1) & 0xf;
628 params
.Op2
= (esr
>> 17) & 0x7;
629 params
.Rt
= (esr
>> 5) & 0x1f;
630 params
.is_write
= !(esr
& 1);
632 return emulate_sys_reg(vcpu
, ¶ms
);
635 /******************************************************************************
637 *****************************************************************************/
639 static bool index_to_params(u64 id
, struct sys_reg_params
*params
)
641 switch (id
& KVM_REG_SIZE_MASK
) {
642 case KVM_REG_SIZE_U64
:
643 /* Any unused index bits means it's not valid. */
644 if (id
& ~(KVM_REG_ARCH_MASK
| KVM_REG_SIZE_MASK
645 | KVM_REG_ARM_COPROC_MASK
646 | KVM_REG_ARM64_SYSREG_OP0_MASK
647 | KVM_REG_ARM64_SYSREG_OP1_MASK
648 | KVM_REG_ARM64_SYSREG_CRN_MASK
649 | KVM_REG_ARM64_SYSREG_CRM_MASK
650 | KVM_REG_ARM64_SYSREG_OP2_MASK
))
652 params
->Op0
= ((id
& KVM_REG_ARM64_SYSREG_OP0_MASK
)
653 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT
);
654 params
->Op1
= ((id
& KVM_REG_ARM64_SYSREG_OP1_MASK
)
655 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT
);
656 params
->CRn
= ((id
& KVM_REG_ARM64_SYSREG_CRN_MASK
)
657 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT
);
658 params
->CRm
= ((id
& KVM_REG_ARM64_SYSREG_CRM_MASK
)
659 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT
);
660 params
->Op2
= ((id
& KVM_REG_ARM64_SYSREG_OP2_MASK
)
661 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT
);
668 /* Decode an index value, and find the sys_reg_desc entry. */
669 static const struct sys_reg_desc
*index_to_sys_reg_desc(struct kvm_vcpu
*vcpu
,
673 const struct sys_reg_desc
*table
, *r
;
674 struct sys_reg_params params
;
676 /* We only do sys_reg for now. */
677 if ((id
& KVM_REG_ARM_COPROC_MASK
) != KVM_REG_ARM64_SYSREG
)
680 if (!index_to_params(id
, ¶ms
))
683 table
= get_target_table(vcpu
->arch
.target
, true, &num
);
684 r
= find_reg(¶ms
, table
, num
);
686 r
= find_reg(¶ms
, sys_reg_descs
, ARRAY_SIZE(sys_reg_descs
));
688 /* Not saved in the sys_reg array? */
696 * These are the invariant sys_reg registers: we let the guest see the
697 * host versions of these, so they're part of the guest state.
699 * A future CPU may provide a mechanism to present different values to
700 * the guest, or a future kvm may trap them.
703 #define FUNCTION_INVARIANT(reg) \
704 static void get_##reg(struct kvm_vcpu *v, \
705 const struct sys_reg_desc *r) \
709 asm volatile("mrs %0, " __stringify(reg) "\n" \
711 ((struct sys_reg_desc *)r)->val = val; \
714 FUNCTION_INVARIANT(midr_el1
)
715 FUNCTION_INVARIANT(ctr_el0
)
716 FUNCTION_INVARIANT(revidr_el1
)
717 FUNCTION_INVARIANT(id_pfr0_el1
)
718 FUNCTION_INVARIANT(id_pfr1_el1
)
719 FUNCTION_INVARIANT(id_dfr0_el1
)
720 FUNCTION_INVARIANT(id_afr0_el1
)
721 FUNCTION_INVARIANT(id_mmfr0_el1
)
722 FUNCTION_INVARIANT(id_mmfr1_el1
)
723 FUNCTION_INVARIANT(id_mmfr2_el1
)
724 FUNCTION_INVARIANT(id_mmfr3_el1
)
725 FUNCTION_INVARIANT(id_isar0_el1
)
726 FUNCTION_INVARIANT(id_isar1_el1
)
727 FUNCTION_INVARIANT(id_isar2_el1
)
728 FUNCTION_INVARIANT(id_isar3_el1
)
729 FUNCTION_INVARIANT(id_isar4_el1
)
730 FUNCTION_INVARIANT(id_isar5_el1
)
731 FUNCTION_INVARIANT(clidr_el1
)
732 FUNCTION_INVARIANT(aidr_el1
)
734 /* ->val is filled in by kvm_sys_reg_table_init() */
735 static struct sys_reg_desc invariant_sys_regs
[] = {
736 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
737 NULL
, get_midr_el1
},
738 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
739 NULL
, get_revidr_el1
},
740 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
741 NULL
, get_id_pfr0_el1
},
742 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
743 NULL
, get_id_pfr1_el1
},
744 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
745 NULL
, get_id_dfr0_el1
},
746 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
747 NULL
, get_id_afr0_el1
},
748 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
749 NULL
, get_id_mmfr0_el1
},
750 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
751 NULL
, get_id_mmfr1_el1
},
752 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
753 NULL
, get_id_mmfr2_el1
},
754 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
755 NULL
, get_id_mmfr3_el1
},
756 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
757 NULL
, get_id_isar0_el1
},
758 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
759 NULL
, get_id_isar1_el1
},
760 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
761 NULL
, get_id_isar2_el1
},
762 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
763 NULL
, get_id_isar3_el1
},
764 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
765 NULL
, get_id_isar4_el1
},
766 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
767 NULL
, get_id_isar5_el1
},
768 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
769 NULL
, get_clidr_el1
},
770 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
771 NULL
, get_aidr_el1
},
772 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
776 static int reg_from_user(void *val
, const void __user
*uaddr
, u64 id
)
778 /* This Just Works because we are little endian. */
779 if (copy_from_user(val
, uaddr
, KVM_REG_SIZE(id
)) != 0)
784 static int reg_to_user(void __user
*uaddr
, const void *val
, u64 id
)
786 /* This Just Works because we are little endian. */
787 if (copy_to_user(uaddr
, val
, KVM_REG_SIZE(id
)) != 0)
792 static int get_invariant_sys_reg(u64 id
, void __user
*uaddr
)
794 struct sys_reg_params params
;
795 const struct sys_reg_desc
*r
;
797 if (!index_to_params(id
, ¶ms
))
800 r
= find_reg(¶ms
, invariant_sys_regs
, ARRAY_SIZE(invariant_sys_regs
));
804 return reg_to_user(uaddr
, &r
->val
, id
);
807 static int set_invariant_sys_reg(u64 id
, void __user
*uaddr
)
809 struct sys_reg_params params
;
810 const struct sys_reg_desc
*r
;
812 u64 val
= 0; /* Make sure high bits are 0 for 32-bit regs */
814 if (!index_to_params(id
, ¶ms
))
816 r
= find_reg(¶ms
, invariant_sys_regs
, ARRAY_SIZE(invariant_sys_regs
));
820 err
= reg_from_user(&val
, uaddr
, id
);
824 /* This is what we mean by invariant: you can't change it. */
831 static bool is_valid_cache(u32 val
)
835 if (val
>= CSSELR_MAX
)
838 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
840 ctype
= (cache_levels
>> (level
* 3)) & 7;
843 case 0: /* No cache */
845 case 1: /* Instruction cache only */
847 case 2: /* Data cache only */
848 case 4: /* Unified cache */
850 case 3: /* Separate instruction and data caches */
852 default: /* Reserved: we can't know instruction or data. */
857 static int demux_c15_get(u64 id
, void __user
*uaddr
)
860 u32 __user
*uval
= uaddr
;
862 /* Fail if we have unknown bits set. */
863 if (id
& ~(KVM_REG_ARCH_MASK
|KVM_REG_SIZE_MASK
|KVM_REG_ARM_COPROC_MASK
864 | ((1 << KVM_REG_ARM_COPROC_SHIFT
)-1)))
867 switch (id
& KVM_REG_ARM_DEMUX_ID_MASK
) {
868 case KVM_REG_ARM_DEMUX_ID_CCSIDR
:
869 if (KVM_REG_SIZE(id
) != 4)
871 val
= (id
& KVM_REG_ARM_DEMUX_VAL_MASK
)
872 >> KVM_REG_ARM_DEMUX_VAL_SHIFT
;
873 if (!is_valid_cache(val
))
876 return put_user(get_ccsidr(val
), uval
);
882 static int demux_c15_set(u64 id
, void __user
*uaddr
)
885 u32 __user
*uval
= uaddr
;
887 /* Fail if we have unknown bits set. */
888 if (id
& ~(KVM_REG_ARCH_MASK
|KVM_REG_SIZE_MASK
|KVM_REG_ARM_COPROC_MASK
889 | ((1 << KVM_REG_ARM_COPROC_SHIFT
)-1)))
892 switch (id
& KVM_REG_ARM_DEMUX_ID_MASK
) {
893 case KVM_REG_ARM_DEMUX_ID_CCSIDR
:
894 if (KVM_REG_SIZE(id
) != 4)
896 val
= (id
& KVM_REG_ARM_DEMUX_VAL_MASK
)
897 >> KVM_REG_ARM_DEMUX_VAL_SHIFT
;
898 if (!is_valid_cache(val
))
901 if (get_user(newval
, uval
))
904 /* This is also invariant: you can't change it. */
905 if (newval
!= get_ccsidr(val
))
913 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu
*vcpu
, const struct kvm_one_reg
*reg
)
915 const struct sys_reg_desc
*r
;
916 void __user
*uaddr
= (void __user
*)(unsigned long)reg
->addr
;
918 if ((reg
->id
& KVM_REG_ARM_COPROC_MASK
) == KVM_REG_ARM_DEMUX
)
919 return demux_c15_get(reg
->id
, uaddr
);
921 if (KVM_REG_SIZE(reg
->id
) != sizeof(__u64
))
924 r
= index_to_sys_reg_desc(vcpu
, reg
->id
);
926 return get_invariant_sys_reg(reg
->id
, uaddr
);
928 return reg_to_user(uaddr
, &vcpu_sys_reg(vcpu
, r
->reg
), reg
->id
);
931 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu
*vcpu
, const struct kvm_one_reg
*reg
)
933 const struct sys_reg_desc
*r
;
934 void __user
*uaddr
= (void __user
*)(unsigned long)reg
->addr
;
936 if ((reg
->id
& KVM_REG_ARM_COPROC_MASK
) == KVM_REG_ARM_DEMUX
)
937 return demux_c15_set(reg
->id
, uaddr
);
939 if (KVM_REG_SIZE(reg
->id
) != sizeof(__u64
))
942 r
= index_to_sys_reg_desc(vcpu
, reg
->id
);
944 return set_invariant_sys_reg(reg
->id
, uaddr
);
946 return reg_from_user(&vcpu_sys_reg(vcpu
, r
->reg
), uaddr
, reg
->id
);
949 static unsigned int num_demux_regs(void)
951 unsigned int i
, count
= 0;
953 for (i
= 0; i
< CSSELR_MAX
; i
++)
954 if (is_valid_cache(i
))
960 static int write_demux_regids(u64 __user
*uindices
)
962 u64 val
= KVM_REG_ARM
| KVM_REG_SIZE_U32
| KVM_REG_ARM_DEMUX
;
965 val
|= KVM_REG_ARM_DEMUX_ID_CCSIDR
;
966 for (i
= 0; i
< CSSELR_MAX
; i
++) {
967 if (!is_valid_cache(i
))
969 if (put_user(val
| i
, uindices
))
976 static u64
sys_reg_to_index(const struct sys_reg_desc
*reg
)
978 return (KVM_REG_ARM64
| KVM_REG_SIZE_U64
|
979 KVM_REG_ARM64_SYSREG
|
980 (reg
->Op0
<< KVM_REG_ARM64_SYSREG_OP0_SHIFT
) |
981 (reg
->Op1
<< KVM_REG_ARM64_SYSREG_OP1_SHIFT
) |
982 (reg
->CRn
<< KVM_REG_ARM64_SYSREG_CRN_SHIFT
) |
983 (reg
->CRm
<< KVM_REG_ARM64_SYSREG_CRM_SHIFT
) |
984 (reg
->Op2
<< KVM_REG_ARM64_SYSREG_OP2_SHIFT
));
987 static bool copy_reg_to_user(const struct sys_reg_desc
*reg
, u64 __user
**uind
)
992 if (put_user(sys_reg_to_index(reg
), *uind
))
999 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1000 static int walk_sys_regs(struct kvm_vcpu
*vcpu
, u64 __user
*uind
)
1002 const struct sys_reg_desc
*i1
, *i2
, *end1
, *end2
;
1003 unsigned int total
= 0;
1006 /* We check for duplicates here, to allow arch-specific overrides. */
1007 i1
= get_target_table(vcpu
->arch
.target
, true, &num
);
1010 end2
= sys_reg_descs
+ ARRAY_SIZE(sys_reg_descs
);
1012 BUG_ON(i1
== end1
|| i2
== end2
);
1014 /* Walk carefully, as both tables may refer to the same register. */
1016 int cmp
= cmp_sys_reg(i1
, i2
);
1017 /* target-specific overrides generic entry. */
1019 /* Ignore registers we trap but don't save. */
1021 if (!copy_reg_to_user(i1
, &uind
))
1026 /* Ignore registers we trap but don't save. */
1028 if (!copy_reg_to_user(i2
, &uind
))
1034 if (cmp
<= 0 && ++i1
== end1
)
1036 if (cmp
>= 0 && ++i2
== end2
)
1042 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu
*vcpu
)
1044 return ARRAY_SIZE(invariant_sys_regs
)
1046 + walk_sys_regs(vcpu
, (u64 __user
*)NULL
);
1049 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu
*vcpu
, u64 __user
*uindices
)
1054 /* Then give them all the invariant registers' indices. */
1055 for (i
= 0; i
< ARRAY_SIZE(invariant_sys_regs
); i
++) {
1056 if (put_user(sys_reg_to_index(&invariant_sys_regs
[i
]), uindices
))
1061 err
= walk_sys_regs(vcpu
, uindices
);
1066 return write_demux_regids(uindices
);
1069 void kvm_sys_reg_table_init(void)
1072 struct sys_reg_desc clidr
;
1074 /* Make sure tables are unique and in order. */
1075 for (i
= 1; i
< ARRAY_SIZE(sys_reg_descs
); i
++)
1076 BUG_ON(cmp_sys_reg(&sys_reg_descs
[i
-1], &sys_reg_descs
[i
]) >= 0);
1078 /* We abuse the reset function to overwrite the table itself. */
1079 for (i
= 0; i
< ARRAY_SIZE(invariant_sys_regs
); i
++)
1080 invariant_sys_regs
[i
].reset(NULL
, &invariant_sys_regs
[i
]);
1083 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1085 * If software reads the Cache Type fields from Ctype1
1086 * upwards, once it has seen a value of 0b000, no caches
1087 * exist at further-out levels of the hierarchy. So, for
1088 * example, if Ctype3 is the first Cache Type field with a
1089 * value of 0b000, the values of Ctype4 to Ctype7 must be
1092 get_clidr_el1(NULL
, &clidr
); /* Ugly... */
1093 cache_levels
= clidr
.val
;
1094 for (i
= 0; i
< 7; i
++)
1095 if (((cache_levels
>> (i
*3)) & 7) == 0)
1097 /* Clear all higher bits. */
1098 cache_levels
&= (1 << (i
*3))-1;
1102 * kvm_reset_sys_regs - sets system registers to reset value
1103 * @vcpu: The VCPU pointer
1105 * This function finds the right table above and sets the registers on the
1106 * virtual CPU struct to their architecturally defined reset values.
1108 void kvm_reset_sys_regs(struct kvm_vcpu
*vcpu
)
1111 const struct sys_reg_desc
*table
;
1113 /* Catch someone adding a register without putting in reset entry. */
1114 memset(&vcpu
->arch
.ctxt
.sys_regs
, 0x42, sizeof(vcpu
->arch
.ctxt
.sys_regs
));
1116 /* Generic chip reset first (so target could override). */
1117 reset_sys_reg_descs(vcpu
, sys_reg_descs
, ARRAY_SIZE(sys_reg_descs
));
1119 table
= get_target_table(vcpu
->arch
.target
, true, &num
);
1120 reset_sys_reg_descs(vcpu
, table
, num
);
1122 for (num
= 1; num
< NR_SYS_REGS
; num
++)
1123 if (vcpu_sys_reg(vcpu
, num
) == 0x4242424242424242)
1124 panic("Didn't reset vcpu_sys_reg(%zi)", num
);