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Merge branch 'linus' into cpus4096
[deliverable/linux.git] / arch / avr32 / mach-at32ap / at32ap700x.c
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
18
19 #include <asm/atmel-mci.h>
20 #include <asm/io.h>
21 #include <asm/irq.h>
22
23 #include <asm/arch/at32ap700x.h>
24 #include <asm/arch/board.h>
25 #include <asm/arch/portmux.h>
26 #include <asm/arch/sram.h>
27
28 #include <video/atmel_lcdc.h>
29
30 #include "clock.h"
31 #include "hmatrix.h"
32 #include "pio.h"
33 #include "pm.h"
34
35
36 #define PBMEM(base) \
37 { \
38 .start = base, \
39 .end = base + 0x3ff, \
40 .flags = IORESOURCE_MEM, \
41 }
42 #define IRQ(num) \
43 { \
44 .start = num, \
45 .end = num, \
46 .flags = IORESOURCE_IRQ, \
47 }
48 #define NAMED_IRQ(num, _name) \
49 { \
50 .start = num, \
51 .end = num, \
52 .name = _name, \
53 .flags = IORESOURCE_IRQ, \
54 }
55
56 /* REVISIT these assume *every* device supports DMA, but several
57 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
58 */
59 #define DEFINE_DEV(_name, _id) \
60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
61 static struct platform_device _name##_id##_device = { \
62 .name = #_name, \
63 .id = _id, \
64 .dev = { \
65 .dma_mask = &_name##_id##_dma_mask, \
66 .coherent_dma_mask = DMA_32BIT_MASK, \
67 }, \
68 .resource = _name##_id##_resource, \
69 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
70 }
71 #define DEFINE_DEV_DATA(_name, _id) \
72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
73 static struct platform_device _name##_id##_device = { \
74 .name = #_name, \
75 .id = _id, \
76 .dev = { \
77 .dma_mask = &_name##_id##_dma_mask, \
78 .platform_data = &_name##_id##_data, \
79 .coherent_dma_mask = DMA_32BIT_MASK, \
80 }, \
81 .resource = _name##_id##_resource, \
82 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
83 }
84
85 #define select_peripheral(pin, periph, flags) \
86 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
87
88 #define DEV_CLK(_name, devname, bus, _index) \
89 static struct clk devname##_##_name = { \
90 .name = #_name, \
91 .dev = &devname##_device.dev, \
92 .parent = &bus##_clk, \
93 .mode = bus##_clk_mode, \
94 .get_rate = bus##_clk_get_rate, \
95 .index = _index, \
96 }
97
98 static DEFINE_SPINLOCK(pm_lock);
99
100 static struct clk osc0;
101 static struct clk osc1;
102
103 static unsigned long osc_get_rate(struct clk *clk)
104 {
105 return at32_board_osc_rates[clk->index];
106 }
107
108 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
109 {
110 unsigned long div, mul, rate;
111
112 div = PM_BFEXT(PLLDIV, control) + 1;
113 mul = PM_BFEXT(PLLMUL, control) + 1;
114
115 rate = clk->parent->get_rate(clk->parent);
116 rate = (rate + div / 2) / div;
117 rate *= mul;
118
119 return rate;
120 }
121
122 static long pll_set_rate(struct clk *clk, unsigned long rate,
123 u32 *pll_ctrl)
124 {
125 unsigned long mul;
126 unsigned long mul_best_fit = 0;
127 unsigned long div;
128 unsigned long div_min;
129 unsigned long div_max;
130 unsigned long div_best_fit = 0;
131 unsigned long base;
132 unsigned long pll_in;
133 unsigned long actual = 0;
134 unsigned long rate_error;
135 unsigned long rate_error_prev = ~0UL;
136 u32 ctrl;
137
138 /* Rate must be between 80 MHz and 200 Mhz. */
139 if (rate < 80000000UL || rate > 200000000UL)
140 return -EINVAL;
141
142 ctrl = PM_BF(PLLOPT, 4);
143 base = clk->parent->get_rate(clk->parent);
144
145 /* PLL input frequency must be between 6 MHz and 32 MHz. */
146 div_min = DIV_ROUND_UP(base, 32000000UL);
147 div_max = base / 6000000UL;
148
149 if (div_max < div_min)
150 return -EINVAL;
151
152 for (div = div_min; div <= div_max; div++) {
153 pll_in = (base + div / 2) / div;
154 mul = (rate + pll_in / 2) / pll_in;
155
156 if (mul == 0)
157 continue;
158
159 actual = pll_in * mul;
160 rate_error = abs(actual - rate);
161
162 if (rate_error < rate_error_prev) {
163 mul_best_fit = mul;
164 div_best_fit = div;
165 rate_error_prev = rate_error;
166 }
167
168 if (rate_error == 0)
169 break;
170 }
171
172 if (div_best_fit == 0)
173 return -EINVAL;
174
175 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
176 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
177 ctrl |= PM_BF(PLLCOUNT, 16);
178
179 if (clk->parent == &osc1)
180 ctrl |= PM_BIT(PLLOSC);
181
182 *pll_ctrl = ctrl;
183
184 return actual;
185 }
186
187 static unsigned long pll0_get_rate(struct clk *clk)
188 {
189 u32 control;
190
191 control = pm_readl(PLL0);
192
193 return pll_get_rate(clk, control);
194 }
195
196 static void pll1_mode(struct clk *clk, int enabled)
197 {
198 unsigned long timeout;
199 u32 status;
200 u32 ctrl;
201
202 ctrl = pm_readl(PLL1);
203
204 if (enabled) {
205 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
206 pr_debug("clk %s: failed to enable, rate not set\n",
207 clk->name);
208 return;
209 }
210
211 ctrl |= PM_BIT(PLLEN);
212 pm_writel(PLL1, ctrl);
213
214 /* Wait for PLL lock. */
215 for (timeout = 10000; timeout; timeout--) {
216 status = pm_readl(ISR);
217 if (status & PM_BIT(LOCK1))
218 break;
219 udelay(10);
220 }
221
222 if (!(status & PM_BIT(LOCK1)))
223 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
224 clk->name);
225 } else {
226 ctrl &= ~PM_BIT(PLLEN);
227 pm_writel(PLL1, ctrl);
228 }
229 }
230
231 static unsigned long pll1_get_rate(struct clk *clk)
232 {
233 u32 control;
234
235 control = pm_readl(PLL1);
236
237 return pll_get_rate(clk, control);
238 }
239
240 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
241 {
242 u32 ctrl = 0;
243 unsigned long actual_rate;
244
245 actual_rate = pll_set_rate(clk, rate, &ctrl);
246
247 if (apply) {
248 if (actual_rate != rate)
249 return -EINVAL;
250 if (clk->users > 0)
251 return -EBUSY;
252 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
253 clk->name, rate, actual_rate);
254 pm_writel(PLL1, ctrl);
255 }
256
257 return actual_rate;
258 }
259
260 static int pll1_set_parent(struct clk *clk, struct clk *parent)
261 {
262 u32 ctrl;
263
264 if (clk->users > 0)
265 return -EBUSY;
266
267 ctrl = pm_readl(PLL1);
268 WARN_ON(ctrl & PM_BIT(PLLEN));
269
270 if (parent == &osc0)
271 ctrl &= ~PM_BIT(PLLOSC);
272 else if (parent == &osc1)
273 ctrl |= PM_BIT(PLLOSC);
274 else
275 return -EINVAL;
276
277 pm_writel(PLL1, ctrl);
278 clk->parent = parent;
279
280 return 0;
281 }
282
283 /*
284 * The AT32AP7000 has five primary clock sources: One 32kHz
285 * oscillator, two crystal oscillators and two PLLs.
286 */
287 static struct clk osc32k = {
288 .name = "osc32k",
289 .get_rate = osc_get_rate,
290 .users = 1,
291 .index = 0,
292 };
293 static struct clk osc0 = {
294 .name = "osc0",
295 .get_rate = osc_get_rate,
296 .users = 1,
297 .index = 1,
298 };
299 static struct clk osc1 = {
300 .name = "osc1",
301 .get_rate = osc_get_rate,
302 .index = 2,
303 };
304 static struct clk pll0 = {
305 .name = "pll0",
306 .get_rate = pll0_get_rate,
307 .parent = &osc0,
308 };
309 static struct clk pll1 = {
310 .name = "pll1",
311 .mode = pll1_mode,
312 .get_rate = pll1_get_rate,
313 .set_rate = pll1_set_rate,
314 .set_parent = pll1_set_parent,
315 .parent = &osc0,
316 };
317
318 /*
319 * The main clock can be either osc0 or pll0. The boot loader may
320 * have chosen one for us, so we don't really know which one until we
321 * have a look at the SM.
322 */
323 static struct clk *main_clock;
324
325 /*
326 * Synchronous clocks are generated from the main clock. The clocks
327 * must satisfy the constraint
328 * fCPU >= fHSB >= fPB
329 * i.e. each clock must not be faster than its parent.
330 */
331 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
332 {
333 return main_clock->get_rate(main_clock) >> shift;
334 };
335
336 static void cpu_clk_mode(struct clk *clk, int enabled)
337 {
338 unsigned long flags;
339 u32 mask;
340
341 spin_lock_irqsave(&pm_lock, flags);
342 mask = pm_readl(CPU_MASK);
343 if (enabled)
344 mask |= 1 << clk->index;
345 else
346 mask &= ~(1 << clk->index);
347 pm_writel(CPU_MASK, mask);
348 spin_unlock_irqrestore(&pm_lock, flags);
349 }
350
351 static unsigned long cpu_clk_get_rate(struct clk *clk)
352 {
353 unsigned long cksel, shift = 0;
354
355 cksel = pm_readl(CKSEL);
356 if (cksel & PM_BIT(CPUDIV))
357 shift = PM_BFEXT(CPUSEL, cksel) + 1;
358
359 return bus_clk_get_rate(clk, shift);
360 }
361
362 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
363 {
364 u32 control;
365 unsigned long parent_rate, child_div, actual_rate, div;
366
367 parent_rate = clk->parent->get_rate(clk->parent);
368 control = pm_readl(CKSEL);
369
370 if (control & PM_BIT(HSBDIV))
371 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
372 else
373 child_div = 1;
374
375 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
376 actual_rate = parent_rate;
377 control &= ~PM_BIT(CPUDIV);
378 } else {
379 unsigned int cpusel;
380 div = (parent_rate + rate / 2) / rate;
381 if (div > child_div)
382 div = child_div;
383 cpusel = (div > 1) ? (fls(div) - 2) : 0;
384 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
385 actual_rate = parent_rate / (1 << (cpusel + 1));
386 }
387
388 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
389 clk->name, rate, actual_rate);
390
391 if (apply)
392 pm_writel(CKSEL, control);
393
394 return actual_rate;
395 }
396
397 static void hsb_clk_mode(struct clk *clk, int enabled)
398 {
399 unsigned long flags;
400 u32 mask;
401
402 spin_lock_irqsave(&pm_lock, flags);
403 mask = pm_readl(HSB_MASK);
404 if (enabled)
405 mask |= 1 << clk->index;
406 else
407 mask &= ~(1 << clk->index);
408 pm_writel(HSB_MASK, mask);
409 spin_unlock_irqrestore(&pm_lock, flags);
410 }
411
412 static unsigned long hsb_clk_get_rate(struct clk *clk)
413 {
414 unsigned long cksel, shift = 0;
415
416 cksel = pm_readl(CKSEL);
417 if (cksel & PM_BIT(HSBDIV))
418 shift = PM_BFEXT(HSBSEL, cksel) + 1;
419
420 return bus_clk_get_rate(clk, shift);
421 }
422
423 static void pba_clk_mode(struct clk *clk, int enabled)
424 {
425 unsigned long flags;
426 u32 mask;
427
428 spin_lock_irqsave(&pm_lock, flags);
429 mask = pm_readl(PBA_MASK);
430 if (enabled)
431 mask |= 1 << clk->index;
432 else
433 mask &= ~(1 << clk->index);
434 pm_writel(PBA_MASK, mask);
435 spin_unlock_irqrestore(&pm_lock, flags);
436 }
437
438 static unsigned long pba_clk_get_rate(struct clk *clk)
439 {
440 unsigned long cksel, shift = 0;
441
442 cksel = pm_readl(CKSEL);
443 if (cksel & PM_BIT(PBADIV))
444 shift = PM_BFEXT(PBASEL, cksel) + 1;
445
446 return bus_clk_get_rate(clk, shift);
447 }
448
449 static void pbb_clk_mode(struct clk *clk, int enabled)
450 {
451 unsigned long flags;
452 u32 mask;
453
454 spin_lock_irqsave(&pm_lock, flags);
455 mask = pm_readl(PBB_MASK);
456 if (enabled)
457 mask |= 1 << clk->index;
458 else
459 mask &= ~(1 << clk->index);
460 pm_writel(PBB_MASK, mask);
461 spin_unlock_irqrestore(&pm_lock, flags);
462 }
463
464 static unsigned long pbb_clk_get_rate(struct clk *clk)
465 {
466 unsigned long cksel, shift = 0;
467
468 cksel = pm_readl(CKSEL);
469 if (cksel & PM_BIT(PBBDIV))
470 shift = PM_BFEXT(PBBSEL, cksel) + 1;
471
472 return bus_clk_get_rate(clk, shift);
473 }
474
475 static struct clk cpu_clk = {
476 .name = "cpu",
477 .get_rate = cpu_clk_get_rate,
478 .set_rate = cpu_clk_set_rate,
479 .users = 1,
480 };
481 static struct clk hsb_clk = {
482 .name = "hsb",
483 .parent = &cpu_clk,
484 .get_rate = hsb_clk_get_rate,
485 };
486 static struct clk pba_clk = {
487 .name = "pba",
488 .parent = &hsb_clk,
489 .mode = hsb_clk_mode,
490 .get_rate = pba_clk_get_rate,
491 .index = 1,
492 };
493 static struct clk pbb_clk = {
494 .name = "pbb",
495 .parent = &hsb_clk,
496 .mode = hsb_clk_mode,
497 .get_rate = pbb_clk_get_rate,
498 .users = 1,
499 .index = 2,
500 };
501
502 /* --------------------------------------------------------------------
503 * Generic Clock operations
504 * -------------------------------------------------------------------- */
505
506 static void genclk_mode(struct clk *clk, int enabled)
507 {
508 u32 control;
509
510 control = pm_readl(GCCTRL(clk->index));
511 if (enabled)
512 control |= PM_BIT(CEN);
513 else
514 control &= ~PM_BIT(CEN);
515 pm_writel(GCCTRL(clk->index), control);
516 }
517
518 static unsigned long genclk_get_rate(struct clk *clk)
519 {
520 u32 control;
521 unsigned long div = 1;
522
523 control = pm_readl(GCCTRL(clk->index));
524 if (control & PM_BIT(DIVEN))
525 div = 2 * (PM_BFEXT(DIV, control) + 1);
526
527 return clk->parent->get_rate(clk->parent) / div;
528 }
529
530 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
531 {
532 u32 control;
533 unsigned long parent_rate, actual_rate, div;
534
535 parent_rate = clk->parent->get_rate(clk->parent);
536 control = pm_readl(GCCTRL(clk->index));
537
538 if (rate > 3 * parent_rate / 4) {
539 actual_rate = parent_rate;
540 control &= ~PM_BIT(DIVEN);
541 } else {
542 div = (parent_rate + rate) / (2 * rate) - 1;
543 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
544 actual_rate = parent_rate / (2 * (div + 1));
545 }
546
547 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
548 clk->name, rate, actual_rate);
549
550 if (apply)
551 pm_writel(GCCTRL(clk->index), control);
552
553 return actual_rate;
554 }
555
556 int genclk_set_parent(struct clk *clk, struct clk *parent)
557 {
558 u32 control;
559
560 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
561 clk->name, parent->name, clk->parent->name);
562
563 control = pm_readl(GCCTRL(clk->index));
564
565 if (parent == &osc1 || parent == &pll1)
566 control |= PM_BIT(OSCSEL);
567 else if (parent == &osc0 || parent == &pll0)
568 control &= ~PM_BIT(OSCSEL);
569 else
570 return -EINVAL;
571
572 if (parent == &pll0 || parent == &pll1)
573 control |= PM_BIT(PLLSEL);
574 else
575 control &= ~PM_BIT(PLLSEL);
576
577 pm_writel(GCCTRL(clk->index), control);
578 clk->parent = parent;
579
580 return 0;
581 }
582
583 static void __init genclk_init_parent(struct clk *clk)
584 {
585 u32 control;
586 struct clk *parent;
587
588 BUG_ON(clk->index > 7);
589
590 control = pm_readl(GCCTRL(clk->index));
591 if (control & PM_BIT(OSCSEL))
592 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
593 else
594 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
595
596 clk->parent = parent;
597 }
598
599 static struct dw_dma_platform_data dw_dmac0_data = {
600 .nr_channels = 3,
601 };
602
603 static struct resource dw_dmac0_resource[] = {
604 PBMEM(0xff200000),
605 IRQ(2),
606 };
607 DEFINE_DEV_DATA(dw_dmac, 0);
608 DEV_CLK(hclk, dw_dmac0, hsb, 10);
609
610 /* --------------------------------------------------------------------
611 * System peripherals
612 * -------------------------------------------------------------------- */
613 static struct resource at32_pm0_resource[] = {
614 {
615 .start = 0xfff00000,
616 .end = 0xfff0007f,
617 .flags = IORESOURCE_MEM,
618 },
619 IRQ(20),
620 };
621
622 static struct resource at32ap700x_rtc0_resource[] = {
623 {
624 .start = 0xfff00080,
625 .end = 0xfff000af,
626 .flags = IORESOURCE_MEM,
627 },
628 IRQ(21),
629 };
630
631 static struct resource at32_wdt0_resource[] = {
632 {
633 .start = 0xfff000b0,
634 .end = 0xfff000cf,
635 .flags = IORESOURCE_MEM,
636 },
637 };
638
639 static struct resource at32_eic0_resource[] = {
640 {
641 .start = 0xfff00100,
642 .end = 0xfff0013f,
643 .flags = IORESOURCE_MEM,
644 },
645 IRQ(19),
646 };
647
648 DEFINE_DEV(at32_pm, 0);
649 DEFINE_DEV(at32ap700x_rtc, 0);
650 DEFINE_DEV(at32_wdt, 0);
651 DEFINE_DEV(at32_eic, 0);
652
653 /*
654 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
655 * is always running.
656 */
657 static struct clk at32_pm_pclk = {
658 .name = "pclk",
659 .dev = &at32_pm0_device.dev,
660 .parent = &pbb_clk,
661 .mode = pbb_clk_mode,
662 .get_rate = pbb_clk_get_rate,
663 .users = 1,
664 .index = 0,
665 };
666
667 static struct resource intc0_resource[] = {
668 PBMEM(0xfff00400),
669 };
670 struct platform_device at32_intc0_device = {
671 .name = "intc",
672 .id = 0,
673 .resource = intc0_resource,
674 .num_resources = ARRAY_SIZE(intc0_resource),
675 };
676 DEV_CLK(pclk, at32_intc0, pbb, 1);
677
678 static struct clk ebi_clk = {
679 .name = "ebi",
680 .parent = &hsb_clk,
681 .mode = hsb_clk_mode,
682 .get_rate = hsb_clk_get_rate,
683 .users = 1,
684 };
685 static struct clk hramc_clk = {
686 .name = "hramc",
687 .parent = &hsb_clk,
688 .mode = hsb_clk_mode,
689 .get_rate = hsb_clk_get_rate,
690 .users = 1,
691 .index = 3,
692 };
693 static struct clk sdramc_clk = {
694 .name = "sdramc_clk",
695 .parent = &pbb_clk,
696 .mode = pbb_clk_mode,
697 .get_rate = pbb_clk_get_rate,
698 .users = 1,
699 .index = 14,
700 };
701
702 static struct resource smc0_resource[] = {
703 PBMEM(0xfff03400),
704 };
705 DEFINE_DEV(smc, 0);
706 DEV_CLK(pclk, smc0, pbb, 13);
707 DEV_CLK(mck, smc0, hsb, 0);
708
709 static struct platform_device pdc_device = {
710 .name = "pdc",
711 .id = 0,
712 };
713 DEV_CLK(hclk, pdc, hsb, 4);
714 DEV_CLK(pclk, pdc, pba, 16);
715
716 static struct clk pico_clk = {
717 .name = "pico",
718 .parent = &cpu_clk,
719 .mode = cpu_clk_mode,
720 .get_rate = cpu_clk_get_rate,
721 .users = 1,
722 };
723
724 /* --------------------------------------------------------------------
725 * HMATRIX
726 * -------------------------------------------------------------------- */
727
728 static struct clk hmatrix_clk = {
729 .name = "hmatrix_clk",
730 .parent = &pbb_clk,
731 .mode = pbb_clk_mode,
732 .get_rate = pbb_clk_get_rate,
733 .index = 2,
734 .users = 1,
735 };
736 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
737
738 #define hmatrix_readl(reg) \
739 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
740 #define hmatrix_writel(reg,value) \
741 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
742
743 /*
744 * Set bits in the HMATRIX Special Function Register (SFR) used by the
745 * External Bus Interface (EBI). This can be used to enable special
746 * features like CompactFlash support, NAND Flash support, etc. on
747 * certain chipselects.
748 */
749 static inline void set_ebi_sfr_bits(u32 mask)
750 {
751 u32 sfr;
752
753 clk_enable(&hmatrix_clk);
754 sfr = hmatrix_readl(SFR4);
755 sfr |= mask;
756 hmatrix_writel(SFR4, sfr);
757 clk_disable(&hmatrix_clk);
758 }
759
760 /* --------------------------------------------------------------------
761 * Timer/Counter (TC)
762 * -------------------------------------------------------------------- */
763
764 static struct resource at32_tcb0_resource[] = {
765 PBMEM(0xfff00c00),
766 IRQ(22),
767 };
768 static struct platform_device at32_tcb0_device = {
769 .name = "atmel_tcb",
770 .id = 0,
771 .resource = at32_tcb0_resource,
772 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
773 };
774 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
775
776 static struct resource at32_tcb1_resource[] = {
777 PBMEM(0xfff01000),
778 IRQ(23),
779 };
780 static struct platform_device at32_tcb1_device = {
781 .name = "atmel_tcb",
782 .id = 1,
783 .resource = at32_tcb1_resource,
784 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
785 };
786 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
787
788 /* --------------------------------------------------------------------
789 * PIO
790 * -------------------------------------------------------------------- */
791
792 static struct resource pio0_resource[] = {
793 PBMEM(0xffe02800),
794 IRQ(13),
795 };
796 DEFINE_DEV(pio, 0);
797 DEV_CLK(mck, pio0, pba, 10);
798
799 static struct resource pio1_resource[] = {
800 PBMEM(0xffe02c00),
801 IRQ(14),
802 };
803 DEFINE_DEV(pio, 1);
804 DEV_CLK(mck, pio1, pba, 11);
805
806 static struct resource pio2_resource[] = {
807 PBMEM(0xffe03000),
808 IRQ(15),
809 };
810 DEFINE_DEV(pio, 2);
811 DEV_CLK(mck, pio2, pba, 12);
812
813 static struct resource pio3_resource[] = {
814 PBMEM(0xffe03400),
815 IRQ(16),
816 };
817 DEFINE_DEV(pio, 3);
818 DEV_CLK(mck, pio3, pba, 13);
819
820 static struct resource pio4_resource[] = {
821 PBMEM(0xffe03800),
822 IRQ(17),
823 };
824 DEFINE_DEV(pio, 4);
825 DEV_CLK(mck, pio4, pba, 14);
826
827 void __init at32_add_system_devices(void)
828 {
829 platform_device_register(&at32_pm0_device);
830 platform_device_register(&at32_intc0_device);
831 platform_device_register(&at32ap700x_rtc0_device);
832 platform_device_register(&at32_wdt0_device);
833 platform_device_register(&at32_eic0_device);
834 platform_device_register(&smc0_device);
835 platform_device_register(&pdc_device);
836 platform_device_register(&dw_dmac0_device);
837
838 platform_device_register(&at32_tcb0_device);
839 platform_device_register(&at32_tcb1_device);
840
841 platform_device_register(&pio0_device);
842 platform_device_register(&pio1_device);
843 platform_device_register(&pio2_device);
844 platform_device_register(&pio3_device);
845 platform_device_register(&pio4_device);
846 }
847
848 /* --------------------------------------------------------------------
849 * PSIF
850 * -------------------------------------------------------------------- */
851 static struct resource atmel_psif0_resource[] __initdata = {
852 {
853 .start = 0xffe03c00,
854 .end = 0xffe03cff,
855 .flags = IORESOURCE_MEM,
856 },
857 IRQ(18),
858 };
859 static struct clk atmel_psif0_pclk = {
860 .name = "pclk",
861 .parent = &pba_clk,
862 .mode = pba_clk_mode,
863 .get_rate = pba_clk_get_rate,
864 .index = 15,
865 };
866
867 static struct resource atmel_psif1_resource[] __initdata = {
868 {
869 .start = 0xffe03d00,
870 .end = 0xffe03dff,
871 .flags = IORESOURCE_MEM,
872 },
873 IRQ(18),
874 };
875 static struct clk atmel_psif1_pclk = {
876 .name = "pclk",
877 .parent = &pba_clk,
878 .mode = pba_clk_mode,
879 .get_rate = pba_clk_get_rate,
880 .index = 15,
881 };
882
883 struct platform_device *__init at32_add_device_psif(unsigned int id)
884 {
885 struct platform_device *pdev;
886
887 if (!(id == 0 || id == 1))
888 return NULL;
889
890 pdev = platform_device_alloc("atmel_psif", id);
891 if (!pdev)
892 return NULL;
893
894 switch (id) {
895 case 0:
896 if (platform_device_add_resources(pdev, atmel_psif0_resource,
897 ARRAY_SIZE(atmel_psif0_resource)))
898 goto err_add_resources;
899 atmel_psif0_pclk.dev = &pdev->dev;
900 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
901 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
902 break;
903 case 1:
904 if (platform_device_add_resources(pdev, atmel_psif1_resource,
905 ARRAY_SIZE(atmel_psif1_resource)))
906 goto err_add_resources;
907 atmel_psif1_pclk.dev = &pdev->dev;
908 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
909 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
910 break;
911 default:
912 return NULL;
913 }
914
915 platform_device_add(pdev);
916 return pdev;
917
918 err_add_resources:
919 platform_device_put(pdev);
920 return NULL;
921 }
922
923 /* --------------------------------------------------------------------
924 * USART
925 * -------------------------------------------------------------------- */
926
927 static struct atmel_uart_data atmel_usart0_data = {
928 .use_dma_tx = 1,
929 .use_dma_rx = 1,
930 };
931 static struct resource atmel_usart0_resource[] = {
932 PBMEM(0xffe00c00),
933 IRQ(6),
934 };
935 DEFINE_DEV_DATA(atmel_usart, 0);
936 DEV_CLK(usart, atmel_usart0, pba, 3);
937
938 static struct atmel_uart_data atmel_usart1_data = {
939 .use_dma_tx = 1,
940 .use_dma_rx = 1,
941 };
942 static struct resource atmel_usart1_resource[] = {
943 PBMEM(0xffe01000),
944 IRQ(7),
945 };
946 DEFINE_DEV_DATA(atmel_usart, 1);
947 DEV_CLK(usart, atmel_usart1, pba, 4);
948
949 static struct atmel_uart_data atmel_usart2_data = {
950 .use_dma_tx = 1,
951 .use_dma_rx = 1,
952 };
953 static struct resource atmel_usart2_resource[] = {
954 PBMEM(0xffe01400),
955 IRQ(8),
956 };
957 DEFINE_DEV_DATA(atmel_usart, 2);
958 DEV_CLK(usart, atmel_usart2, pba, 5);
959
960 static struct atmel_uart_data atmel_usart3_data = {
961 .use_dma_tx = 1,
962 .use_dma_rx = 1,
963 };
964 static struct resource atmel_usart3_resource[] = {
965 PBMEM(0xffe01800),
966 IRQ(9),
967 };
968 DEFINE_DEV_DATA(atmel_usart, 3);
969 DEV_CLK(usart, atmel_usart3, pba, 6);
970
971 static inline void configure_usart0_pins(void)
972 {
973 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
974 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
975 }
976
977 static inline void configure_usart1_pins(void)
978 {
979 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
980 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
981 }
982
983 static inline void configure_usart2_pins(void)
984 {
985 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
986 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
987 }
988
989 static inline void configure_usart3_pins(void)
990 {
991 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
992 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
993 }
994
995 static struct platform_device *__initdata at32_usarts[4];
996
997 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
998 {
999 struct platform_device *pdev;
1000
1001 switch (hw_id) {
1002 case 0:
1003 pdev = &atmel_usart0_device;
1004 configure_usart0_pins();
1005 break;
1006 case 1:
1007 pdev = &atmel_usart1_device;
1008 configure_usart1_pins();
1009 break;
1010 case 2:
1011 pdev = &atmel_usart2_device;
1012 configure_usart2_pins();
1013 break;
1014 case 3:
1015 pdev = &atmel_usart3_device;
1016 configure_usart3_pins();
1017 break;
1018 default:
1019 return;
1020 }
1021
1022 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1023 /* Addresses in the P4 segment are permanently mapped 1:1 */
1024 struct atmel_uart_data *data = pdev->dev.platform_data;
1025 data->regs = (void __iomem *)pdev->resource[0].start;
1026 }
1027
1028 pdev->id = line;
1029 at32_usarts[line] = pdev;
1030 }
1031
1032 struct platform_device *__init at32_add_device_usart(unsigned int id)
1033 {
1034 platform_device_register(at32_usarts[id]);
1035 return at32_usarts[id];
1036 }
1037
1038 struct platform_device *atmel_default_console_device;
1039
1040 void __init at32_setup_serial_console(unsigned int usart_id)
1041 {
1042 atmel_default_console_device = at32_usarts[usart_id];
1043 }
1044
1045 /* --------------------------------------------------------------------
1046 * Ethernet
1047 * -------------------------------------------------------------------- */
1048
1049 #ifdef CONFIG_CPU_AT32AP7000
1050 static struct eth_platform_data macb0_data;
1051 static struct resource macb0_resource[] = {
1052 PBMEM(0xfff01800),
1053 IRQ(25),
1054 };
1055 DEFINE_DEV_DATA(macb, 0);
1056 DEV_CLK(hclk, macb0, hsb, 8);
1057 DEV_CLK(pclk, macb0, pbb, 6);
1058
1059 static struct eth_platform_data macb1_data;
1060 static struct resource macb1_resource[] = {
1061 PBMEM(0xfff01c00),
1062 IRQ(26),
1063 };
1064 DEFINE_DEV_DATA(macb, 1);
1065 DEV_CLK(hclk, macb1, hsb, 9);
1066 DEV_CLK(pclk, macb1, pbb, 7);
1067
1068 struct platform_device *__init
1069 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1070 {
1071 struct platform_device *pdev;
1072
1073 switch (id) {
1074 case 0:
1075 pdev = &macb0_device;
1076
1077 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
1078 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
1079 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
1080 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
1081 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
1082 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1083 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1084 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1085 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
1086 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1087
1088 if (!data->is_rmii) {
1089 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
1090 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
1091 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
1092 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
1093 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
1094 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1095 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1096 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1097 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
1098 }
1099 break;
1100
1101 case 1:
1102 pdev = &macb1_device;
1103
1104 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
1105 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
1106 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
1107 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
1108 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
1109 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
1110 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
1111 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
1112 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
1113 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
1114
1115 if (!data->is_rmii) {
1116 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
1117 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
1118 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1119 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1120 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1121 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1122 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1123 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1124 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
1125 }
1126 break;
1127
1128 default:
1129 return NULL;
1130 }
1131
1132 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1133 platform_device_register(pdev);
1134
1135 return pdev;
1136 }
1137 #endif
1138
1139 /* --------------------------------------------------------------------
1140 * SPI
1141 * -------------------------------------------------------------------- */
1142 static struct resource atmel_spi0_resource[] = {
1143 PBMEM(0xffe00000),
1144 IRQ(3),
1145 };
1146 DEFINE_DEV(atmel_spi, 0);
1147 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1148
1149 static struct resource atmel_spi1_resource[] = {
1150 PBMEM(0xffe00400),
1151 IRQ(4),
1152 };
1153 DEFINE_DEV(atmel_spi, 1);
1154 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1155
1156 static void __init
1157 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1158 unsigned int n, const u8 *pins)
1159 {
1160 unsigned int pin, mode;
1161
1162 for (; n; n--, b++) {
1163 b->bus_num = bus_num;
1164 if (b->chip_select >= 4)
1165 continue;
1166 pin = (unsigned)b->controller_data;
1167 if (!pin) {
1168 pin = pins[b->chip_select];
1169 b->controller_data = (void *)pin;
1170 }
1171 mode = AT32_GPIOF_OUTPUT;
1172 if (!(b->mode & SPI_CS_HIGH))
1173 mode |= AT32_GPIOF_HIGH;
1174 at32_select_gpio(pin, mode);
1175 }
1176 }
1177
1178 struct platform_device *__init
1179 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1180 {
1181 /*
1182 * Manage the chipselects as GPIOs, normally using the same pins
1183 * the SPI controller expects; but boards can use other pins.
1184 */
1185 static u8 __initdata spi0_pins[] =
1186 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1187 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1188 static u8 __initdata spi1_pins[] =
1189 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1190 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1191 struct platform_device *pdev;
1192
1193 switch (id) {
1194 case 0:
1195 pdev = &atmel_spi0_device;
1196 /* pullup MISO so a level is always defined */
1197 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1198 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1199 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1200 at32_spi_setup_slaves(0, b, n, spi0_pins);
1201 break;
1202
1203 case 1:
1204 pdev = &atmel_spi1_device;
1205 /* pullup MISO so a level is always defined */
1206 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1207 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1208 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1209 at32_spi_setup_slaves(1, b, n, spi1_pins);
1210 break;
1211
1212 default:
1213 return NULL;
1214 }
1215
1216 spi_register_board_info(b, n);
1217 platform_device_register(pdev);
1218 return pdev;
1219 }
1220
1221 /* --------------------------------------------------------------------
1222 * TWI
1223 * -------------------------------------------------------------------- */
1224 static struct resource atmel_twi0_resource[] __initdata = {
1225 PBMEM(0xffe00800),
1226 IRQ(5),
1227 };
1228 static struct clk atmel_twi0_pclk = {
1229 .name = "twi_pclk",
1230 .parent = &pba_clk,
1231 .mode = pba_clk_mode,
1232 .get_rate = pba_clk_get_rate,
1233 .index = 2,
1234 };
1235
1236 struct platform_device *__init at32_add_device_twi(unsigned int id,
1237 struct i2c_board_info *b,
1238 unsigned int n)
1239 {
1240 struct platform_device *pdev;
1241
1242 if (id != 0)
1243 return NULL;
1244
1245 pdev = platform_device_alloc("atmel_twi", id);
1246 if (!pdev)
1247 return NULL;
1248
1249 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1250 ARRAY_SIZE(atmel_twi0_resource)))
1251 goto err_add_resources;
1252
1253 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1254 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1255
1256 atmel_twi0_pclk.dev = &pdev->dev;
1257
1258 if (b)
1259 i2c_register_board_info(id, b, n);
1260
1261 platform_device_add(pdev);
1262 return pdev;
1263
1264 err_add_resources:
1265 platform_device_put(pdev);
1266 return NULL;
1267 }
1268
1269 /* --------------------------------------------------------------------
1270 * MMC
1271 * -------------------------------------------------------------------- */
1272 static struct resource atmel_mci0_resource[] __initdata = {
1273 PBMEM(0xfff02400),
1274 IRQ(28),
1275 };
1276 static struct clk atmel_mci0_pclk = {
1277 .name = "mci_clk",
1278 .parent = &pbb_clk,
1279 .mode = pbb_clk_mode,
1280 .get_rate = pbb_clk_get_rate,
1281 .index = 9,
1282 };
1283
1284 struct platform_device *__init
1285 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1286 {
1287 struct mci_platform_data _data;
1288 struct platform_device *pdev;
1289
1290 if (id != 0)
1291 return NULL;
1292
1293 pdev = platform_device_alloc("atmel_mci", id);
1294 if (!pdev)
1295 goto fail;
1296
1297 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1298 ARRAY_SIZE(atmel_mci0_resource)))
1299 goto fail;
1300
1301 if (!data) {
1302 data = &_data;
1303 memset(data, -1, sizeof(struct mci_platform_data));
1304 data->detect_pin = GPIO_PIN_NONE;
1305 data->wp_pin = GPIO_PIN_NONE;
1306 }
1307
1308 if (platform_device_add_data(pdev, data,
1309 sizeof(struct mci_platform_data)))
1310 goto fail;
1311
1312 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1313 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1314 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1315 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1316 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1317 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1318
1319 if (gpio_is_valid(data->detect_pin))
1320 at32_select_gpio(data->detect_pin, 0);
1321 if (gpio_is_valid(data->wp_pin))
1322 at32_select_gpio(data->wp_pin, 0);
1323
1324 atmel_mci0_pclk.dev = &pdev->dev;
1325
1326 platform_device_add(pdev);
1327 return pdev;
1328
1329 fail:
1330 platform_device_put(pdev);
1331 return NULL;
1332 }
1333
1334 /* --------------------------------------------------------------------
1335 * LCDC
1336 * -------------------------------------------------------------------- */
1337 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1338 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1339 static struct resource atmel_lcdfb0_resource[] = {
1340 {
1341 .start = 0xff000000,
1342 .end = 0xff000fff,
1343 .flags = IORESOURCE_MEM,
1344 },
1345 IRQ(1),
1346 {
1347 /* Placeholder for pre-allocated fb memory */
1348 .start = 0x00000000,
1349 .end = 0x00000000,
1350 .flags = 0,
1351 },
1352 };
1353 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1354 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1355 static struct clk atmel_lcdfb0_pixclk = {
1356 .name = "lcdc_clk",
1357 .dev = &atmel_lcdfb0_device.dev,
1358 .mode = genclk_mode,
1359 .get_rate = genclk_get_rate,
1360 .set_rate = genclk_set_rate,
1361 .set_parent = genclk_set_parent,
1362 .index = 7,
1363 };
1364
1365 struct platform_device *__init
1366 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1367 unsigned long fbmem_start, unsigned long fbmem_len,
1368 unsigned int pin_config)
1369 {
1370 struct platform_device *pdev;
1371 struct atmel_lcdfb_info *info;
1372 struct fb_monspecs *monspecs;
1373 struct fb_videomode *modedb;
1374 unsigned int modedb_size;
1375
1376 /*
1377 * Do a deep copy of the fb data, monspecs and modedb. Make
1378 * sure all allocations are done before setting up the
1379 * portmux.
1380 */
1381 monspecs = kmemdup(data->default_monspecs,
1382 sizeof(struct fb_monspecs), GFP_KERNEL);
1383 if (!monspecs)
1384 return NULL;
1385
1386 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1387 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1388 if (!modedb)
1389 goto err_dup_modedb;
1390 monspecs->modedb = modedb;
1391
1392 switch (id) {
1393 case 0:
1394 pdev = &atmel_lcdfb0_device;
1395
1396 switch (pin_config) {
1397 case 0:
1398 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1399 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1400 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1401 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1402 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1403 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1404 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1405 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1406 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1407 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1408 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1409 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1410 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1411 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1412 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1413 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1414 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1415 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1416 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1417 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1418 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1419 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1420 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1421 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1422 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1423 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1424 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1425 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1426 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1427 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1428 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1429 break;
1430 case 1:
1431 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1432 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1433 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1434 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1435 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1436 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1437 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1438 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1439 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1440 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1441 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1442 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1443 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1444 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1445 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1446 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1447 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1448 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1449 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1450 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1451 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1452 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1453 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1454 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1455 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1456 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1457 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1458 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1459 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1460 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1461 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1462 break;
1463 default:
1464 goto err_invalid_id;
1465 }
1466
1467 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1468 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1469 break;
1470
1471 default:
1472 goto err_invalid_id;
1473 }
1474
1475 if (fbmem_len) {
1476 pdev->resource[2].start = fbmem_start;
1477 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1478 pdev->resource[2].flags = IORESOURCE_MEM;
1479 }
1480
1481 info = pdev->dev.platform_data;
1482 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1483 info->default_monspecs = monspecs;
1484
1485 platform_device_register(pdev);
1486 return pdev;
1487
1488 err_invalid_id:
1489 kfree(modedb);
1490 err_dup_modedb:
1491 kfree(monspecs);
1492 return NULL;
1493 }
1494 #endif
1495
1496 /* --------------------------------------------------------------------
1497 * PWM
1498 * -------------------------------------------------------------------- */
1499 static struct resource atmel_pwm0_resource[] __initdata = {
1500 PBMEM(0xfff01400),
1501 IRQ(24),
1502 };
1503 static struct clk atmel_pwm0_mck = {
1504 .name = "pwm_clk",
1505 .parent = &pbb_clk,
1506 .mode = pbb_clk_mode,
1507 .get_rate = pbb_clk_get_rate,
1508 .index = 5,
1509 };
1510
1511 struct platform_device *__init at32_add_device_pwm(u32 mask)
1512 {
1513 struct platform_device *pdev;
1514
1515 if (!mask)
1516 return NULL;
1517
1518 pdev = platform_device_alloc("atmel_pwm", 0);
1519 if (!pdev)
1520 return NULL;
1521
1522 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1523 ARRAY_SIZE(atmel_pwm0_resource)))
1524 goto out_free_pdev;
1525
1526 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1527 goto out_free_pdev;
1528
1529 if (mask & (1 << 0))
1530 select_peripheral(PA(28), PERIPH_A, 0);
1531 if (mask & (1 << 1))
1532 select_peripheral(PA(29), PERIPH_A, 0);
1533 if (mask & (1 << 2))
1534 select_peripheral(PA(21), PERIPH_B, 0);
1535 if (mask & (1 << 3))
1536 select_peripheral(PA(22), PERIPH_B, 0);
1537
1538 atmel_pwm0_mck.dev = &pdev->dev;
1539
1540 platform_device_add(pdev);
1541
1542 return pdev;
1543
1544 out_free_pdev:
1545 platform_device_put(pdev);
1546 return NULL;
1547 }
1548
1549 /* --------------------------------------------------------------------
1550 * SSC
1551 * -------------------------------------------------------------------- */
1552 static struct resource ssc0_resource[] = {
1553 PBMEM(0xffe01c00),
1554 IRQ(10),
1555 };
1556 DEFINE_DEV(ssc, 0);
1557 DEV_CLK(pclk, ssc0, pba, 7);
1558
1559 static struct resource ssc1_resource[] = {
1560 PBMEM(0xffe02000),
1561 IRQ(11),
1562 };
1563 DEFINE_DEV(ssc, 1);
1564 DEV_CLK(pclk, ssc1, pba, 8);
1565
1566 static struct resource ssc2_resource[] = {
1567 PBMEM(0xffe02400),
1568 IRQ(12),
1569 };
1570 DEFINE_DEV(ssc, 2);
1571 DEV_CLK(pclk, ssc2, pba, 9);
1572
1573 struct platform_device *__init
1574 at32_add_device_ssc(unsigned int id, unsigned int flags)
1575 {
1576 struct platform_device *pdev;
1577
1578 switch (id) {
1579 case 0:
1580 pdev = &ssc0_device;
1581 if (flags & ATMEL_SSC_RF)
1582 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1583 if (flags & ATMEL_SSC_RK)
1584 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1585 if (flags & ATMEL_SSC_TK)
1586 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1587 if (flags & ATMEL_SSC_TF)
1588 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1589 if (flags & ATMEL_SSC_TD)
1590 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1591 if (flags & ATMEL_SSC_RD)
1592 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1593 break;
1594 case 1:
1595 pdev = &ssc1_device;
1596 if (flags & ATMEL_SSC_RF)
1597 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1598 if (flags & ATMEL_SSC_RK)
1599 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1600 if (flags & ATMEL_SSC_TK)
1601 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1602 if (flags & ATMEL_SSC_TF)
1603 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1604 if (flags & ATMEL_SSC_TD)
1605 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1606 if (flags & ATMEL_SSC_RD)
1607 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1608 break;
1609 case 2:
1610 pdev = &ssc2_device;
1611 if (flags & ATMEL_SSC_TD)
1612 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1613 if (flags & ATMEL_SSC_RD)
1614 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1615 if (flags & ATMEL_SSC_TK)
1616 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1617 if (flags & ATMEL_SSC_TF)
1618 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1619 if (flags & ATMEL_SSC_RF)
1620 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1621 if (flags & ATMEL_SSC_RK)
1622 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1623 break;
1624 default:
1625 return NULL;
1626 }
1627
1628 platform_device_register(pdev);
1629 return pdev;
1630 }
1631
1632 /* --------------------------------------------------------------------
1633 * USB Device Controller
1634 * -------------------------------------------------------------------- */
1635 static struct resource usba0_resource[] __initdata = {
1636 {
1637 .start = 0xff300000,
1638 .end = 0xff3fffff,
1639 .flags = IORESOURCE_MEM,
1640 }, {
1641 .start = 0xfff03000,
1642 .end = 0xfff033ff,
1643 .flags = IORESOURCE_MEM,
1644 },
1645 IRQ(31),
1646 };
1647 static struct clk usba0_pclk = {
1648 .name = "pclk",
1649 .parent = &pbb_clk,
1650 .mode = pbb_clk_mode,
1651 .get_rate = pbb_clk_get_rate,
1652 .index = 12,
1653 };
1654 static struct clk usba0_hclk = {
1655 .name = "hclk",
1656 .parent = &hsb_clk,
1657 .mode = hsb_clk_mode,
1658 .get_rate = hsb_clk_get_rate,
1659 .index = 6,
1660 };
1661
1662 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1663 [idx] = { \
1664 .name = nam, \
1665 .index = idx, \
1666 .fifo_size = maxpkt, \
1667 .nr_banks = maxbk, \
1668 .can_dma = dma, \
1669 .can_isoc = isoc, \
1670 }
1671
1672 static struct usba_ep_data at32_usba_ep[] __initdata = {
1673 EP("ep0", 0, 64, 1, 0, 0),
1674 EP("ep1", 1, 512, 2, 1, 1),
1675 EP("ep2", 2, 512, 2, 1, 1),
1676 EP("ep3-int", 3, 64, 3, 1, 0),
1677 EP("ep4-int", 4, 64, 3, 1, 0),
1678 EP("ep5", 5, 1024, 3, 1, 1),
1679 EP("ep6", 6, 1024, 3, 1, 1),
1680 };
1681
1682 #undef EP
1683
1684 struct platform_device *__init
1685 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1686 {
1687 /*
1688 * pdata doesn't have room for any endpoints, so we need to
1689 * append room for the ones we need right after it.
1690 */
1691 struct {
1692 struct usba_platform_data pdata;
1693 struct usba_ep_data ep[7];
1694 } usba_data;
1695 struct platform_device *pdev;
1696
1697 if (id != 0)
1698 return NULL;
1699
1700 pdev = platform_device_alloc("atmel_usba_udc", 0);
1701 if (!pdev)
1702 return NULL;
1703
1704 if (platform_device_add_resources(pdev, usba0_resource,
1705 ARRAY_SIZE(usba0_resource)))
1706 goto out_free_pdev;
1707
1708 if (data)
1709 usba_data.pdata.vbus_pin = data->vbus_pin;
1710 else
1711 usba_data.pdata.vbus_pin = -EINVAL;
1712
1713 data = &usba_data.pdata;
1714 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1715 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1716
1717 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1718 goto out_free_pdev;
1719
1720 if (data->vbus_pin >= 0)
1721 at32_select_gpio(data->vbus_pin, 0);
1722
1723 usba0_pclk.dev = &pdev->dev;
1724 usba0_hclk.dev = &pdev->dev;
1725
1726 platform_device_add(pdev);
1727
1728 return pdev;
1729
1730 out_free_pdev:
1731 platform_device_put(pdev);
1732 return NULL;
1733 }
1734
1735 /* --------------------------------------------------------------------
1736 * IDE / CompactFlash
1737 * -------------------------------------------------------------------- */
1738 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1739 static struct resource at32_smc_cs4_resource[] __initdata = {
1740 {
1741 .start = 0x04000000,
1742 .end = 0x07ffffff,
1743 .flags = IORESOURCE_MEM,
1744 },
1745 IRQ(~0UL), /* Magic IRQ will be overridden */
1746 };
1747 static struct resource at32_smc_cs5_resource[] __initdata = {
1748 {
1749 .start = 0x20000000,
1750 .end = 0x23ffffff,
1751 .flags = IORESOURCE_MEM,
1752 },
1753 IRQ(~0UL), /* Magic IRQ will be overridden */
1754 };
1755
1756 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1757 unsigned int cs, unsigned int extint)
1758 {
1759 static unsigned int extint_pin_map[4] __initdata = {
1760 GPIO_PIN_PB(25),
1761 GPIO_PIN_PB(26),
1762 GPIO_PIN_PB(27),
1763 GPIO_PIN_PB(28),
1764 };
1765 static bool common_pins_initialized __initdata = false;
1766 unsigned int extint_pin;
1767 int ret;
1768
1769 if (extint >= ARRAY_SIZE(extint_pin_map))
1770 return -EINVAL;
1771 extint_pin = extint_pin_map[extint];
1772
1773 switch (cs) {
1774 case 4:
1775 ret = platform_device_add_resources(pdev,
1776 at32_smc_cs4_resource,
1777 ARRAY_SIZE(at32_smc_cs4_resource));
1778 if (ret)
1779 return ret;
1780
1781 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1782 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1783 break;
1784 case 5:
1785 ret = platform_device_add_resources(pdev,
1786 at32_smc_cs5_resource,
1787 ARRAY_SIZE(at32_smc_cs5_resource));
1788 if (ret)
1789 return ret;
1790
1791 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1792 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1793 break;
1794 default:
1795 return -EINVAL;
1796 }
1797
1798 if (!common_pins_initialized) {
1799 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1800 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1801 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1802 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1803 common_pins_initialized = true;
1804 }
1805
1806 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1807
1808 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1809 pdev->resource[1].end = pdev->resource[1].start;
1810
1811 return 0;
1812 }
1813
1814 struct platform_device *__init
1815 at32_add_device_ide(unsigned int id, unsigned int extint,
1816 struct ide_platform_data *data)
1817 {
1818 struct platform_device *pdev;
1819
1820 pdev = platform_device_alloc("at32_ide", id);
1821 if (!pdev)
1822 goto fail;
1823
1824 if (platform_device_add_data(pdev, data,
1825 sizeof(struct ide_platform_data)))
1826 goto fail;
1827
1828 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1829 goto fail;
1830
1831 platform_device_add(pdev);
1832 return pdev;
1833
1834 fail:
1835 platform_device_put(pdev);
1836 return NULL;
1837 }
1838
1839 struct platform_device *__init
1840 at32_add_device_cf(unsigned int id, unsigned int extint,
1841 struct cf_platform_data *data)
1842 {
1843 struct platform_device *pdev;
1844
1845 pdev = platform_device_alloc("at32_cf", id);
1846 if (!pdev)
1847 goto fail;
1848
1849 if (platform_device_add_data(pdev, data,
1850 sizeof(struct cf_platform_data)))
1851 goto fail;
1852
1853 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1854 goto fail;
1855
1856 if (gpio_is_valid(data->detect_pin))
1857 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1858 if (gpio_is_valid(data->reset_pin))
1859 at32_select_gpio(data->reset_pin, 0);
1860 if (gpio_is_valid(data->vcc_pin))
1861 at32_select_gpio(data->vcc_pin, 0);
1862 /* READY is used as extint, so we can't select it as gpio */
1863
1864 platform_device_add(pdev);
1865 return pdev;
1866
1867 fail:
1868 platform_device_put(pdev);
1869 return NULL;
1870 }
1871 #endif
1872
1873 /* --------------------------------------------------------------------
1874 * NAND Flash / SmartMedia
1875 * -------------------------------------------------------------------- */
1876 static struct resource smc_cs3_resource[] __initdata = {
1877 {
1878 .start = 0x0c000000,
1879 .end = 0x0fffffff,
1880 .flags = IORESOURCE_MEM,
1881 }, {
1882 .start = 0xfff03c00,
1883 .end = 0xfff03fff,
1884 .flags = IORESOURCE_MEM,
1885 },
1886 };
1887
1888 struct platform_device *__init
1889 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1890 {
1891 struct platform_device *pdev;
1892
1893 if (id != 0 || !data)
1894 return NULL;
1895
1896 pdev = platform_device_alloc("atmel_nand", id);
1897 if (!pdev)
1898 goto fail;
1899
1900 if (platform_device_add_resources(pdev, smc_cs3_resource,
1901 ARRAY_SIZE(smc_cs3_resource)))
1902 goto fail;
1903
1904 if (platform_device_add_data(pdev, data,
1905 sizeof(struct atmel_nand_data)))
1906 goto fail;
1907
1908 set_ebi_sfr_bits(HMATRIX_BIT(CS3A));
1909 if (data->enable_pin)
1910 at32_select_gpio(data->enable_pin,
1911 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1912 if (data->rdy_pin)
1913 at32_select_gpio(data->rdy_pin, 0);
1914 if (data->det_pin)
1915 at32_select_gpio(data->det_pin, 0);
1916
1917 platform_device_add(pdev);
1918 return pdev;
1919
1920 fail:
1921 platform_device_put(pdev);
1922 return NULL;
1923 }
1924
1925 /* --------------------------------------------------------------------
1926 * AC97C
1927 * -------------------------------------------------------------------- */
1928 static struct resource atmel_ac97c0_resource[] __initdata = {
1929 PBMEM(0xfff02800),
1930 IRQ(29),
1931 };
1932 static struct clk atmel_ac97c0_pclk = {
1933 .name = "pclk",
1934 .parent = &pbb_clk,
1935 .mode = pbb_clk_mode,
1936 .get_rate = pbb_clk_get_rate,
1937 .index = 10,
1938 };
1939
1940 struct platform_device *__init
1941 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1942 {
1943 struct platform_device *pdev;
1944 struct ac97c_platform_data _data;
1945
1946 if (id != 0)
1947 return NULL;
1948
1949 pdev = platform_device_alloc("atmel_ac97c", id);
1950 if (!pdev)
1951 return NULL;
1952
1953 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1954 ARRAY_SIZE(atmel_ac97c0_resource)))
1955 goto fail;
1956
1957 if (!data) {
1958 data = &_data;
1959 memset(data, 0, sizeof(struct ac97c_platform_data));
1960 data->reset_pin = GPIO_PIN_NONE;
1961 }
1962
1963 data->dma_rx_periph_id = 3;
1964 data->dma_tx_periph_id = 4;
1965 data->dma_controller_id = 0;
1966
1967 if (platform_device_add_data(pdev, data,
1968 sizeof(struct ac97c_platform_data)))
1969 goto fail;
1970
1971 select_peripheral(PB(20), PERIPH_B, 0); /* SDO */
1972 select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */
1973 select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */
1974 select_peripheral(PB(23), PERIPH_B, 0); /* SDI */
1975
1976 /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
1977 if (data->reset_pin != GPIO_PIN_NONE)
1978 at32_select_gpio(data->reset_pin, 0);
1979
1980 atmel_ac97c0_pclk.dev = &pdev->dev;
1981
1982 platform_device_add(pdev);
1983 return pdev;
1984
1985 fail:
1986 platform_device_put(pdev);
1987 return NULL;
1988 }
1989
1990 /* --------------------------------------------------------------------
1991 * ABDAC
1992 * -------------------------------------------------------------------- */
1993 static struct resource abdac0_resource[] __initdata = {
1994 PBMEM(0xfff02000),
1995 IRQ(27),
1996 };
1997 static struct clk abdac0_pclk = {
1998 .name = "pclk",
1999 .parent = &pbb_clk,
2000 .mode = pbb_clk_mode,
2001 .get_rate = pbb_clk_get_rate,
2002 .index = 8,
2003 };
2004 static struct clk abdac0_sample_clk = {
2005 .name = "sample_clk",
2006 .mode = genclk_mode,
2007 .get_rate = genclk_get_rate,
2008 .set_rate = genclk_set_rate,
2009 .set_parent = genclk_set_parent,
2010 .index = 6,
2011 };
2012
2013 struct platform_device *__init at32_add_device_abdac(unsigned int id)
2014 {
2015 struct platform_device *pdev;
2016
2017 if (id != 0)
2018 return NULL;
2019
2020 pdev = platform_device_alloc("abdac", id);
2021 if (!pdev)
2022 return NULL;
2023
2024 if (platform_device_add_resources(pdev, abdac0_resource,
2025 ARRAY_SIZE(abdac0_resource)))
2026 goto err_add_resources;
2027
2028 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
2029 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
2030 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
2031 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
2032
2033 abdac0_pclk.dev = &pdev->dev;
2034 abdac0_sample_clk.dev = &pdev->dev;
2035
2036 platform_device_add(pdev);
2037 return pdev;
2038
2039 err_add_resources:
2040 platform_device_put(pdev);
2041 return NULL;
2042 }
2043
2044 /* --------------------------------------------------------------------
2045 * GCLK
2046 * -------------------------------------------------------------------- */
2047 static struct clk gclk0 = {
2048 .name = "gclk0",
2049 .mode = genclk_mode,
2050 .get_rate = genclk_get_rate,
2051 .set_rate = genclk_set_rate,
2052 .set_parent = genclk_set_parent,
2053 .index = 0,
2054 };
2055 static struct clk gclk1 = {
2056 .name = "gclk1",
2057 .mode = genclk_mode,
2058 .get_rate = genclk_get_rate,
2059 .set_rate = genclk_set_rate,
2060 .set_parent = genclk_set_parent,
2061 .index = 1,
2062 };
2063 static struct clk gclk2 = {
2064 .name = "gclk2",
2065 .mode = genclk_mode,
2066 .get_rate = genclk_get_rate,
2067 .set_rate = genclk_set_rate,
2068 .set_parent = genclk_set_parent,
2069 .index = 2,
2070 };
2071 static struct clk gclk3 = {
2072 .name = "gclk3",
2073 .mode = genclk_mode,
2074 .get_rate = genclk_get_rate,
2075 .set_rate = genclk_set_rate,
2076 .set_parent = genclk_set_parent,
2077 .index = 3,
2078 };
2079 static struct clk gclk4 = {
2080 .name = "gclk4",
2081 .mode = genclk_mode,
2082 .get_rate = genclk_get_rate,
2083 .set_rate = genclk_set_rate,
2084 .set_parent = genclk_set_parent,
2085 .index = 4,
2086 };
2087
2088 struct clk *at32_clock_list[] = {
2089 &osc32k,
2090 &osc0,
2091 &osc1,
2092 &pll0,
2093 &pll1,
2094 &cpu_clk,
2095 &hsb_clk,
2096 &pba_clk,
2097 &pbb_clk,
2098 &at32_pm_pclk,
2099 &at32_intc0_pclk,
2100 &hmatrix_clk,
2101 &ebi_clk,
2102 &hramc_clk,
2103 &sdramc_clk,
2104 &smc0_pclk,
2105 &smc0_mck,
2106 &pdc_hclk,
2107 &pdc_pclk,
2108 &dw_dmac0_hclk,
2109 &pico_clk,
2110 &pio0_mck,
2111 &pio1_mck,
2112 &pio2_mck,
2113 &pio3_mck,
2114 &pio4_mck,
2115 &at32_tcb0_t0_clk,
2116 &at32_tcb1_t0_clk,
2117 &atmel_psif0_pclk,
2118 &atmel_psif1_pclk,
2119 &atmel_usart0_usart,
2120 &atmel_usart1_usart,
2121 &atmel_usart2_usart,
2122 &atmel_usart3_usart,
2123 &atmel_pwm0_mck,
2124 #if defined(CONFIG_CPU_AT32AP7000)
2125 &macb0_hclk,
2126 &macb0_pclk,
2127 &macb1_hclk,
2128 &macb1_pclk,
2129 #endif
2130 &atmel_spi0_spi_clk,
2131 &atmel_spi1_spi_clk,
2132 &atmel_twi0_pclk,
2133 &atmel_mci0_pclk,
2134 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2135 &atmel_lcdfb0_hck1,
2136 &atmel_lcdfb0_pixclk,
2137 #endif
2138 &ssc0_pclk,
2139 &ssc1_pclk,
2140 &ssc2_pclk,
2141 &usba0_hclk,
2142 &usba0_pclk,
2143 &atmel_ac97c0_pclk,
2144 &abdac0_pclk,
2145 &abdac0_sample_clk,
2146 &gclk0,
2147 &gclk1,
2148 &gclk2,
2149 &gclk3,
2150 &gclk4,
2151 };
2152 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2153
2154 void __init setup_platform(void)
2155 {
2156 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2157 int i;
2158
2159 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2160 main_clock = &pll0;
2161 cpu_clk.parent = &pll0;
2162 } else {
2163 main_clock = &osc0;
2164 cpu_clk.parent = &osc0;
2165 }
2166
2167 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2168 pll0.parent = &osc1;
2169 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2170 pll1.parent = &osc1;
2171
2172 genclk_init_parent(&gclk0);
2173 genclk_init_parent(&gclk1);
2174 genclk_init_parent(&gclk2);
2175 genclk_init_parent(&gclk3);
2176 genclk_init_parent(&gclk4);
2177 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2178 genclk_init_parent(&atmel_lcdfb0_pixclk);
2179 #endif
2180 genclk_init_parent(&abdac0_sample_clk);
2181
2182 /*
2183 * Turn on all clocks that have at least one user already, and
2184 * turn off everything else. We only do this for module
2185 * clocks, and even though it isn't particularly pretty to
2186 * check the address of the mode function, it should do the
2187 * trick...
2188 */
2189 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2190 struct clk *clk = at32_clock_list[i];
2191
2192 if (clk->users == 0)
2193 continue;
2194
2195 if (clk->mode == &cpu_clk_mode)
2196 cpu_mask |= 1 << clk->index;
2197 else if (clk->mode == &hsb_clk_mode)
2198 hsb_mask |= 1 << clk->index;
2199 else if (clk->mode == &pba_clk_mode)
2200 pba_mask |= 1 << clk->index;
2201 else if (clk->mode == &pbb_clk_mode)
2202 pbb_mask |= 1 << clk->index;
2203 }
2204
2205 pm_writel(CPU_MASK, cpu_mask);
2206 pm_writel(HSB_MASK, hsb_mask);
2207 pm_writel(PBA_MASK, pba_mask);
2208 pm_writel(PBB_MASK, pbb_mask);
2209
2210 /* Initialize the port muxes */
2211 at32_init_pio(&pio0_device);
2212 at32_init_pio(&pio1_device);
2213 at32_init_pio(&pio2_device);
2214 at32_init_pio(&pio3_device);
2215 at32_init_pio(&pio4_device);
2216 }
2217
2218 struct gen_pool *sram_pool;
2219
2220 static int __init sram_init(void)
2221 {
2222 struct gen_pool *pool;
2223
2224 /* 1KiB granularity */
2225 pool = gen_pool_create(10, -1);
2226 if (!pool)
2227 goto fail;
2228
2229 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2230 goto err_pool_add;
2231
2232 sram_pool = pool;
2233 return 0;
2234
2235 err_pool_add:
2236 gen_pool_destroy(pool);
2237 fail:
2238 pr_err("Failed to create SRAM pool\n");
2239 return -ENOMEM;
2240 }
2241 core_initcall(sram_init);
Linux kernel - Deliverables
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