2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/spi/spi.h>
15 #include <linux/usb/atmel_usba_udc.h>
17 #include <asm/atmel-mci.h>
21 #include <asm/arch/at32ap700x.h>
22 #include <asm/arch/board.h>
23 #include <asm/arch/portmux.h>
24 #include <asm/arch/sram.h>
26 #include <video/atmel_lcdc.h>
37 .end = base + 0x3ff, \
38 .flags = IORESOURCE_MEM, \
44 .flags = IORESOURCE_IRQ, \
46 #define NAMED_IRQ(num, _name) \
51 .flags = IORESOURCE_IRQ, \
54 /* REVISIT these assume *every* device supports DMA, but several
55 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
57 #define DEFINE_DEV(_name, _id) \
58 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
59 static struct platform_device _name##_id##_device = { \
63 .dma_mask = &_name##_id##_dma_mask, \
64 .coherent_dma_mask = DMA_32BIT_MASK, \
66 .resource = _name##_id##_resource, \
67 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
69 #define DEFINE_DEV_DATA(_name, _id) \
70 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
71 static struct platform_device _name##_id##_device = { \
75 .dma_mask = &_name##_id##_dma_mask, \
76 .platform_data = &_name##_id##_data, \
77 .coherent_dma_mask = DMA_32BIT_MASK, \
79 .resource = _name##_id##_resource, \
80 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
83 #define select_peripheral(pin, periph, flags) \
84 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
86 #define DEV_CLK(_name, devname, bus, _index) \
87 static struct clk devname##_##_name = { \
89 .dev = &devname##_device.dev, \
90 .parent = &bus##_clk, \
91 .mode = bus##_clk_mode, \
92 .get_rate = bus##_clk_get_rate, \
96 static DEFINE_SPINLOCK(pm_lock
);
98 static struct clk osc0
;
99 static struct clk osc1
;
101 static unsigned long osc_get_rate(struct clk
*clk
)
103 return at32_board_osc_rates
[clk
->index
];
106 static unsigned long pll_get_rate(struct clk
*clk
, unsigned long control
)
108 unsigned long div
, mul
, rate
;
110 div
= PM_BFEXT(PLLDIV
, control
) + 1;
111 mul
= PM_BFEXT(PLLMUL
, control
) + 1;
113 rate
= clk
->parent
->get_rate(clk
->parent
);
114 rate
= (rate
+ div
/ 2) / div
;
120 static long pll_set_rate(struct clk
*clk
, unsigned long rate
,
124 unsigned long mul_best_fit
= 0;
126 unsigned long div_min
;
127 unsigned long div_max
;
128 unsigned long div_best_fit
= 0;
130 unsigned long pll_in
;
131 unsigned long actual
= 0;
132 unsigned long rate_error
;
133 unsigned long rate_error_prev
= ~0UL;
136 /* Rate must be between 80 MHz and 200 Mhz. */
137 if (rate
< 80000000UL || rate
> 200000000UL)
140 ctrl
= PM_BF(PLLOPT
, 4);
141 base
= clk
->parent
->get_rate(clk
->parent
);
143 /* PLL input frequency must be between 6 MHz and 32 MHz. */
144 div_min
= DIV_ROUND_UP(base
, 32000000UL);
145 div_max
= base
/ 6000000UL;
147 if (div_max
< div_min
)
150 for (div
= div_min
; div
<= div_max
; div
++) {
151 pll_in
= (base
+ div
/ 2) / div
;
152 mul
= (rate
+ pll_in
/ 2) / pll_in
;
157 actual
= pll_in
* mul
;
158 rate_error
= abs(actual
- rate
);
160 if (rate_error
< rate_error_prev
) {
163 rate_error_prev
= rate_error
;
170 if (div_best_fit
== 0)
173 ctrl
|= PM_BF(PLLMUL
, mul_best_fit
- 1);
174 ctrl
|= PM_BF(PLLDIV
, div_best_fit
- 1);
175 ctrl
|= PM_BF(PLLCOUNT
, 16);
177 if (clk
->parent
== &osc1
)
178 ctrl
|= PM_BIT(PLLOSC
);
185 static unsigned long pll0_get_rate(struct clk
*clk
)
189 control
= pm_readl(PLL0
);
191 return pll_get_rate(clk
, control
);
194 static void pll1_mode(struct clk
*clk
, int enabled
)
196 unsigned long timeout
;
200 ctrl
= pm_readl(PLL1
);
203 if (!PM_BFEXT(PLLMUL
, ctrl
) && !PM_BFEXT(PLLDIV
, ctrl
)) {
204 pr_debug("clk %s: failed to enable, rate not set\n",
209 ctrl
|= PM_BIT(PLLEN
);
210 pm_writel(PLL1
, ctrl
);
212 /* Wait for PLL lock. */
213 for (timeout
= 10000; timeout
; timeout
--) {
214 status
= pm_readl(ISR
);
215 if (status
& PM_BIT(LOCK1
))
220 if (!(status
& PM_BIT(LOCK1
)))
221 printk(KERN_ERR
"clk %s: timeout waiting for lock\n",
224 ctrl
&= ~PM_BIT(PLLEN
);
225 pm_writel(PLL1
, ctrl
);
229 static unsigned long pll1_get_rate(struct clk
*clk
)
233 control
= pm_readl(PLL1
);
235 return pll_get_rate(clk
, control
);
238 static long pll1_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
241 unsigned long actual_rate
;
243 actual_rate
= pll_set_rate(clk
, rate
, &ctrl
);
246 if (actual_rate
!= rate
)
250 pr_debug(KERN_INFO
"clk %s: new rate %lu (actual rate %lu)\n",
251 clk
->name
, rate
, actual_rate
);
252 pm_writel(PLL1
, ctrl
);
258 static int pll1_set_parent(struct clk
*clk
, struct clk
*parent
)
265 ctrl
= pm_readl(PLL1
);
266 WARN_ON(ctrl
& PM_BIT(PLLEN
));
269 ctrl
&= ~PM_BIT(PLLOSC
);
270 else if (parent
== &osc1
)
271 ctrl
|= PM_BIT(PLLOSC
);
275 pm_writel(PLL1
, ctrl
);
276 clk
->parent
= parent
;
282 * The AT32AP7000 has five primary clock sources: One 32kHz
283 * oscillator, two crystal oscillators and two PLLs.
285 static struct clk osc32k
= {
287 .get_rate
= osc_get_rate
,
291 static struct clk osc0
= {
293 .get_rate
= osc_get_rate
,
297 static struct clk osc1
= {
299 .get_rate
= osc_get_rate
,
302 static struct clk pll0
= {
304 .get_rate
= pll0_get_rate
,
307 static struct clk pll1
= {
310 .get_rate
= pll1_get_rate
,
311 .set_rate
= pll1_set_rate
,
312 .set_parent
= pll1_set_parent
,
317 * The main clock can be either osc0 or pll0. The boot loader may
318 * have chosen one for us, so we don't really know which one until we
319 * have a look at the SM.
321 static struct clk
*main_clock
;
324 * Synchronous clocks are generated from the main clock. The clocks
325 * must satisfy the constraint
326 * fCPU >= fHSB >= fPB
327 * i.e. each clock must not be faster than its parent.
329 static unsigned long bus_clk_get_rate(struct clk
*clk
, unsigned int shift
)
331 return main_clock
->get_rate(main_clock
) >> shift
;
334 static void cpu_clk_mode(struct clk
*clk
, int enabled
)
339 spin_lock_irqsave(&pm_lock
, flags
);
340 mask
= pm_readl(CPU_MASK
);
342 mask
|= 1 << clk
->index
;
344 mask
&= ~(1 << clk
->index
);
345 pm_writel(CPU_MASK
, mask
);
346 spin_unlock_irqrestore(&pm_lock
, flags
);
349 static unsigned long cpu_clk_get_rate(struct clk
*clk
)
351 unsigned long cksel
, shift
= 0;
353 cksel
= pm_readl(CKSEL
);
354 if (cksel
& PM_BIT(CPUDIV
))
355 shift
= PM_BFEXT(CPUSEL
, cksel
) + 1;
357 return bus_clk_get_rate(clk
, shift
);
360 static long cpu_clk_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
363 unsigned long parent_rate
, child_div
, actual_rate
, div
;
365 parent_rate
= clk
->parent
->get_rate(clk
->parent
);
366 control
= pm_readl(CKSEL
);
368 if (control
& PM_BIT(HSBDIV
))
369 child_div
= 1 << (PM_BFEXT(HSBSEL
, control
) + 1);
373 if (rate
> 3 * (parent_rate
/ 4) || child_div
== 1) {
374 actual_rate
= parent_rate
;
375 control
&= ~PM_BIT(CPUDIV
);
378 div
= (parent_rate
+ rate
/ 2) / rate
;
381 cpusel
= (div
> 1) ? (fls(div
) - 2) : 0;
382 control
= PM_BIT(CPUDIV
) | PM_BFINS(CPUSEL
, cpusel
, control
);
383 actual_rate
= parent_rate
/ (1 << (cpusel
+ 1));
386 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
387 clk
->name
, rate
, actual_rate
);
390 pm_writel(CKSEL
, control
);
395 static void hsb_clk_mode(struct clk
*clk
, int enabled
)
400 spin_lock_irqsave(&pm_lock
, flags
);
401 mask
= pm_readl(HSB_MASK
);
403 mask
|= 1 << clk
->index
;
405 mask
&= ~(1 << clk
->index
);
406 pm_writel(HSB_MASK
, mask
);
407 spin_unlock_irqrestore(&pm_lock
, flags
);
410 static unsigned long hsb_clk_get_rate(struct clk
*clk
)
412 unsigned long cksel
, shift
= 0;
414 cksel
= pm_readl(CKSEL
);
415 if (cksel
& PM_BIT(HSBDIV
))
416 shift
= PM_BFEXT(HSBSEL
, cksel
) + 1;
418 return bus_clk_get_rate(clk
, shift
);
421 static void pba_clk_mode(struct clk
*clk
, int enabled
)
426 spin_lock_irqsave(&pm_lock
, flags
);
427 mask
= pm_readl(PBA_MASK
);
429 mask
|= 1 << clk
->index
;
431 mask
&= ~(1 << clk
->index
);
432 pm_writel(PBA_MASK
, mask
);
433 spin_unlock_irqrestore(&pm_lock
, flags
);
436 static unsigned long pba_clk_get_rate(struct clk
*clk
)
438 unsigned long cksel
, shift
= 0;
440 cksel
= pm_readl(CKSEL
);
441 if (cksel
& PM_BIT(PBADIV
))
442 shift
= PM_BFEXT(PBASEL
, cksel
) + 1;
444 return bus_clk_get_rate(clk
, shift
);
447 static void pbb_clk_mode(struct clk
*clk
, int enabled
)
452 spin_lock_irqsave(&pm_lock
, flags
);
453 mask
= pm_readl(PBB_MASK
);
455 mask
|= 1 << clk
->index
;
457 mask
&= ~(1 << clk
->index
);
458 pm_writel(PBB_MASK
, mask
);
459 spin_unlock_irqrestore(&pm_lock
, flags
);
462 static unsigned long pbb_clk_get_rate(struct clk
*clk
)
464 unsigned long cksel
, shift
= 0;
466 cksel
= pm_readl(CKSEL
);
467 if (cksel
& PM_BIT(PBBDIV
))
468 shift
= PM_BFEXT(PBBSEL
, cksel
) + 1;
470 return bus_clk_get_rate(clk
, shift
);
473 static struct clk cpu_clk
= {
475 .get_rate
= cpu_clk_get_rate
,
476 .set_rate
= cpu_clk_set_rate
,
479 static struct clk hsb_clk
= {
482 .get_rate
= hsb_clk_get_rate
,
484 static struct clk pba_clk
= {
487 .mode
= hsb_clk_mode
,
488 .get_rate
= pba_clk_get_rate
,
491 static struct clk pbb_clk
= {
494 .mode
= hsb_clk_mode
,
495 .get_rate
= pbb_clk_get_rate
,
500 /* --------------------------------------------------------------------
501 * Generic Clock operations
502 * -------------------------------------------------------------------- */
504 static void genclk_mode(struct clk
*clk
, int enabled
)
508 control
= pm_readl(GCCTRL(clk
->index
));
510 control
|= PM_BIT(CEN
);
512 control
&= ~PM_BIT(CEN
);
513 pm_writel(GCCTRL(clk
->index
), control
);
516 static unsigned long genclk_get_rate(struct clk
*clk
)
519 unsigned long div
= 1;
521 control
= pm_readl(GCCTRL(clk
->index
));
522 if (control
& PM_BIT(DIVEN
))
523 div
= 2 * (PM_BFEXT(DIV
, control
) + 1);
525 return clk
->parent
->get_rate(clk
->parent
) / div
;
528 static long genclk_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
531 unsigned long parent_rate
, actual_rate
, div
;
533 parent_rate
= clk
->parent
->get_rate(clk
->parent
);
534 control
= pm_readl(GCCTRL(clk
->index
));
536 if (rate
> 3 * parent_rate
/ 4) {
537 actual_rate
= parent_rate
;
538 control
&= ~PM_BIT(DIVEN
);
540 div
= (parent_rate
+ rate
) / (2 * rate
) - 1;
541 control
= PM_BFINS(DIV
, div
, control
) | PM_BIT(DIVEN
);
542 actual_rate
= parent_rate
/ (2 * (div
+ 1));
545 dev_dbg(clk
->dev
, "clk %s: new rate %lu (actual rate %lu)\n",
546 clk
->name
, rate
, actual_rate
);
549 pm_writel(GCCTRL(clk
->index
), control
);
554 int genclk_set_parent(struct clk
*clk
, struct clk
*parent
)
558 dev_dbg(clk
->dev
, "clk %s: new parent %s (was %s)\n",
559 clk
->name
, parent
->name
, clk
->parent
->name
);
561 control
= pm_readl(GCCTRL(clk
->index
));
563 if (parent
== &osc1
|| parent
== &pll1
)
564 control
|= PM_BIT(OSCSEL
);
565 else if (parent
== &osc0
|| parent
== &pll0
)
566 control
&= ~PM_BIT(OSCSEL
);
570 if (parent
== &pll0
|| parent
== &pll1
)
571 control
|= PM_BIT(PLLSEL
);
573 control
&= ~PM_BIT(PLLSEL
);
575 pm_writel(GCCTRL(clk
->index
), control
);
576 clk
->parent
= parent
;
581 static void __init
genclk_init_parent(struct clk
*clk
)
586 BUG_ON(clk
->index
> 7);
588 control
= pm_readl(GCCTRL(clk
->index
));
589 if (control
& PM_BIT(OSCSEL
))
590 parent
= (control
& PM_BIT(PLLSEL
)) ? &pll1
: &osc1
;
592 parent
= (control
& PM_BIT(PLLSEL
)) ? &pll0
: &osc0
;
594 clk
->parent
= parent
;
597 /* --------------------------------------------------------------------
599 * -------------------------------------------------------------------- */
600 static struct resource at32_pm0_resource
[] = {
604 .flags
= IORESOURCE_MEM
,
609 static struct resource at32ap700x_rtc0_resource
[] = {
613 .flags
= IORESOURCE_MEM
,
618 static struct resource at32_wdt0_resource
[] = {
622 .flags
= IORESOURCE_MEM
,
626 static struct resource at32_eic0_resource
[] = {
630 .flags
= IORESOURCE_MEM
,
635 DEFINE_DEV(at32_pm
, 0);
636 DEFINE_DEV(at32ap700x_rtc
, 0);
637 DEFINE_DEV(at32_wdt
, 0);
638 DEFINE_DEV(at32_eic
, 0);
641 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
644 static struct clk at32_pm_pclk
= {
646 .dev
= &at32_pm0_device
.dev
,
648 .mode
= pbb_clk_mode
,
649 .get_rate
= pbb_clk_get_rate
,
654 static struct resource intc0_resource
[] = {
657 struct platform_device at32_intc0_device
= {
660 .resource
= intc0_resource
,
661 .num_resources
= ARRAY_SIZE(intc0_resource
),
663 DEV_CLK(pclk
, at32_intc0
, pbb
, 1);
665 static struct clk ebi_clk
= {
668 .mode
= hsb_clk_mode
,
669 .get_rate
= hsb_clk_get_rate
,
672 static struct clk hramc_clk
= {
675 .mode
= hsb_clk_mode
,
676 .get_rate
= hsb_clk_get_rate
,
680 static struct clk sdramc_clk
= {
681 .name
= "sdramc_clk",
683 .mode
= pbb_clk_mode
,
684 .get_rate
= pbb_clk_get_rate
,
689 static struct resource smc0_resource
[] = {
693 DEV_CLK(pclk
, smc0
, pbb
, 13);
694 DEV_CLK(mck
, smc0
, hsb
, 0);
696 static struct platform_device pdc_device
= {
700 DEV_CLK(hclk
, pdc
, hsb
, 4);
701 DEV_CLK(pclk
, pdc
, pba
, 16);
703 static struct clk pico_clk
= {
706 .mode
= cpu_clk_mode
,
707 .get_rate
= cpu_clk_get_rate
,
711 static struct resource dmaca0_resource
[] = {
715 .flags
= IORESOURCE_MEM
,
719 DEFINE_DEV(dmaca
, 0);
720 DEV_CLK(hclk
, dmaca0
, hsb
, 10);
722 /* --------------------------------------------------------------------
724 * -------------------------------------------------------------------- */
726 static struct clk hmatrix_clk
= {
727 .name
= "hmatrix_clk",
729 .mode
= pbb_clk_mode
,
730 .get_rate
= pbb_clk_get_rate
,
734 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
736 #define hmatrix_readl(reg) \
737 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
738 #define hmatrix_writel(reg,value) \
739 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
742 * Set bits in the HMATRIX Special Function Register (SFR) used by the
743 * External Bus Interface (EBI). This can be used to enable special
744 * features like CompactFlash support, NAND Flash support, etc. on
745 * certain chipselects.
747 static inline void set_ebi_sfr_bits(u32 mask
)
751 clk_enable(&hmatrix_clk
);
752 sfr
= hmatrix_readl(SFR4
);
754 hmatrix_writel(SFR4
, sfr
);
755 clk_disable(&hmatrix_clk
);
758 /* --------------------------------------------------------------------
760 * -------------------------------------------------------------------- */
762 static struct resource at32_tcb0_resource
[] = {
766 static struct platform_device at32_tcb0_device
= {
769 .resource
= at32_tcb0_resource
,
770 .num_resources
= ARRAY_SIZE(at32_tcb0_resource
),
772 DEV_CLK(t0_clk
, at32_tcb0
, pbb
, 3);
774 static struct resource at32_tcb1_resource
[] = {
778 static struct platform_device at32_tcb1_device
= {
781 .resource
= at32_tcb1_resource
,
782 .num_resources
= ARRAY_SIZE(at32_tcb1_resource
),
784 DEV_CLK(t0_clk
, at32_tcb1
, pbb
, 4);
786 /* --------------------------------------------------------------------
788 * -------------------------------------------------------------------- */
790 static struct resource pio0_resource
[] = {
795 DEV_CLK(mck
, pio0
, pba
, 10);
797 static struct resource pio1_resource
[] = {
802 DEV_CLK(mck
, pio1
, pba
, 11);
804 static struct resource pio2_resource
[] = {
809 DEV_CLK(mck
, pio2
, pba
, 12);
811 static struct resource pio3_resource
[] = {
816 DEV_CLK(mck
, pio3
, pba
, 13);
818 static struct resource pio4_resource
[] = {
823 DEV_CLK(mck
, pio4
, pba
, 14);
825 void __init
at32_add_system_devices(void)
827 platform_device_register(&at32_pm0_device
);
828 platform_device_register(&at32_intc0_device
);
829 platform_device_register(&at32ap700x_rtc0_device
);
830 platform_device_register(&at32_wdt0_device
);
831 platform_device_register(&at32_eic0_device
);
832 platform_device_register(&smc0_device
);
833 platform_device_register(&pdc_device
);
834 platform_device_register(&dmaca0_device
);
836 platform_device_register(&at32_tcb0_device
);
837 platform_device_register(&at32_tcb1_device
);
839 platform_device_register(&pio0_device
);
840 platform_device_register(&pio1_device
);
841 platform_device_register(&pio2_device
);
842 platform_device_register(&pio3_device
);
843 platform_device_register(&pio4_device
);
846 /* --------------------------------------------------------------------
848 * -------------------------------------------------------------------- */
849 static struct resource atmel_psif0_resource
[] __initdata
= {
853 .flags
= IORESOURCE_MEM
,
857 static struct clk atmel_psif0_pclk
= {
860 .mode
= pba_clk_mode
,
861 .get_rate
= pba_clk_get_rate
,
865 static struct resource atmel_psif1_resource
[] __initdata
= {
869 .flags
= IORESOURCE_MEM
,
873 static struct clk atmel_psif1_pclk
= {
876 .mode
= pba_clk_mode
,
877 .get_rate
= pba_clk_get_rate
,
881 struct platform_device
*__init
at32_add_device_psif(unsigned int id
)
883 struct platform_device
*pdev
;
885 if (!(id
== 0 || id
== 1))
888 pdev
= platform_device_alloc("atmel_psif", id
);
894 if (platform_device_add_resources(pdev
, atmel_psif0_resource
,
895 ARRAY_SIZE(atmel_psif0_resource
)))
896 goto err_add_resources
;
897 atmel_psif0_pclk
.dev
= &pdev
->dev
;
898 select_peripheral(PA(8), PERIPH_A
, 0); /* CLOCK */
899 select_peripheral(PA(9), PERIPH_A
, 0); /* DATA */
902 if (platform_device_add_resources(pdev
, atmel_psif1_resource
,
903 ARRAY_SIZE(atmel_psif1_resource
)))
904 goto err_add_resources
;
905 atmel_psif1_pclk
.dev
= &pdev
->dev
;
906 select_peripheral(PB(11), PERIPH_A
, 0); /* CLOCK */
907 select_peripheral(PB(12), PERIPH_A
, 0); /* DATA */
913 platform_device_add(pdev
);
917 platform_device_put(pdev
);
921 /* --------------------------------------------------------------------
923 * -------------------------------------------------------------------- */
925 static struct atmel_uart_data atmel_usart0_data
= {
929 static struct resource atmel_usart0_resource
[] = {
933 DEFINE_DEV_DATA(atmel_usart
, 0);
934 DEV_CLK(usart
, atmel_usart0
, pba
, 3);
936 static struct atmel_uart_data atmel_usart1_data
= {
940 static struct resource atmel_usart1_resource
[] = {
944 DEFINE_DEV_DATA(atmel_usart
, 1);
945 DEV_CLK(usart
, atmel_usart1
, pba
, 4);
947 static struct atmel_uart_data atmel_usart2_data
= {
951 static struct resource atmel_usart2_resource
[] = {
955 DEFINE_DEV_DATA(atmel_usart
, 2);
956 DEV_CLK(usart
, atmel_usart2
, pba
, 5);
958 static struct atmel_uart_data atmel_usart3_data
= {
962 static struct resource atmel_usart3_resource
[] = {
966 DEFINE_DEV_DATA(atmel_usart
, 3);
967 DEV_CLK(usart
, atmel_usart3
, pba
, 6);
969 static inline void configure_usart0_pins(void)
971 select_peripheral(PA(8), PERIPH_B
, 0); /* RXD */
972 select_peripheral(PA(9), PERIPH_B
, 0); /* TXD */
975 static inline void configure_usart1_pins(void)
977 select_peripheral(PA(17), PERIPH_A
, 0); /* RXD */
978 select_peripheral(PA(18), PERIPH_A
, 0); /* TXD */
981 static inline void configure_usart2_pins(void)
983 select_peripheral(PB(26), PERIPH_B
, 0); /* RXD */
984 select_peripheral(PB(27), PERIPH_B
, 0); /* TXD */
987 static inline void configure_usart3_pins(void)
989 select_peripheral(PB(18), PERIPH_B
, 0); /* RXD */
990 select_peripheral(PB(17), PERIPH_B
, 0); /* TXD */
993 static struct platform_device
*__initdata at32_usarts
[4];
995 void __init
at32_map_usart(unsigned int hw_id
, unsigned int line
)
997 struct platform_device
*pdev
;
1001 pdev
= &atmel_usart0_device
;
1002 configure_usart0_pins();
1005 pdev
= &atmel_usart1_device
;
1006 configure_usart1_pins();
1009 pdev
= &atmel_usart2_device
;
1010 configure_usart2_pins();
1013 pdev
= &atmel_usart3_device
;
1014 configure_usart3_pins();
1020 if (PXSEG(pdev
->resource
[0].start
) == P4SEG
) {
1021 /* Addresses in the P4 segment are permanently mapped 1:1 */
1022 struct atmel_uart_data
*data
= pdev
->dev
.platform_data
;
1023 data
->regs
= (void __iomem
*)pdev
->resource
[0].start
;
1027 at32_usarts
[line
] = pdev
;
1030 struct platform_device
*__init
at32_add_device_usart(unsigned int id
)
1032 platform_device_register(at32_usarts
[id
]);
1033 return at32_usarts
[id
];
1036 struct platform_device
*atmel_default_console_device
;
1038 void __init
at32_setup_serial_console(unsigned int usart_id
)
1040 atmel_default_console_device
= at32_usarts
[usart_id
];
1043 /* --------------------------------------------------------------------
1045 * -------------------------------------------------------------------- */
1047 #ifdef CONFIG_CPU_AT32AP7000
1048 static struct eth_platform_data macb0_data
;
1049 static struct resource macb0_resource
[] = {
1053 DEFINE_DEV_DATA(macb
, 0);
1054 DEV_CLK(hclk
, macb0
, hsb
, 8);
1055 DEV_CLK(pclk
, macb0
, pbb
, 6);
1057 static struct eth_platform_data macb1_data
;
1058 static struct resource macb1_resource
[] = {
1062 DEFINE_DEV_DATA(macb
, 1);
1063 DEV_CLK(hclk
, macb1
, hsb
, 9);
1064 DEV_CLK(pclk
, macb1
, pbb
, 7);
1066 struct platform_device
*__init
1067 at32_add_device_eth(unsigned int id
, struct eth_platform_data
*data
)
1069 struct platform_device
*pdev
;
1073 pdev
= &macb0_device
;
1075 select_peripheral(PC(3), PERIPH_A
, 0); /* TXD0 */
1076 select_peripheral(PC(4), PERIPH_A
, 0); /* TXD1 */
1077 select_peripheral(PC(7), PERIPH_A
, 0); /* TXEN */
1078 select_peripheral(PC(8), PERIPH_A
, 0); /* TXCK */
1079 select_peripheral(PC(9), PERIPH_A
, 0); /* RXD0 */
1080 select_peripheral(PC(10), PERIPH_A
, 0); /* RXD1 */
1081 select_peripheral(PC(13), PERIPH_A
, 0); /* RXER */
1082 select_peripheral(PC(15), PERIPH_A
, 0); /* RXDV */
1083 select_peripheral(PC(16), PERIPH_A
, 0); /* MDC */
1084 select_peripheral(PC(17), PERIPH_A
, 0); /* MDIO */
1086 if (!data
->is_rmii
) {
1087 select_peripheral(PC(0), PERIPH_A
, 0); /* COL */
1088 select_peripheral(PC(1), PERIPH_A
, 0); /* CRS */
1089 select_peripheral(PC(2), PERIPH_A
, 0); /* TXER */
1090 select_peripheral(PC(5), PERIPH_A
, 0); /* TXD2 */
1091 select_peripheral(PC(6), PERIPH_A
, 0); /* TXD3 */
1092 select_peripheral(PC(11), PERIPH_A
, 0); /* RXD2 */
1093 select_peripheral(PC(12), PERIPH_A
, 0); /* RXD3 */
1094 select_peripheral(PC(14), PERIPH_A
, 0); /* RXCK */
1095 select_peripheral(PC(18), PERIPH_A
, 0); /* SPD */
1100 pdev
= &macb1_device
;
1102 select_peripheral(PD(13), PERIPH_B
, 0); /* TXD0 */
1103 select_peripheral(PD(14), PERIPH_B
, 0); /* TXD1 */
1104 select_peripheral(PD(11), PERIPH_B
, 0); /* TXEN */
1105 select_peripheral(PD(12), PERIPH_B
, 0); /* TXCK */
1106 select_peripheral(PD(10), PERIPH_B
, 0); /* RXD0 */
1107 select_peripheral(PD(6), PERIPH_B
, 0); /* RXD1 */
1108 select_peripheral(PD(5), PERIPH_B
, 0); /* RXER */
1109 select_peripheral(PD(4), PERIPH_B
, 0); /* RXDV */
1110 select_peripheral(PD(3), PERIPH_B
, 0); /* MDC */
1111 select_peripheral(PD(2), PERIPH_B
, 0); /* MDIO */
1113 if (!data
->is_rmii
) {
1114 select_peripheral(PC(19), PERIPH_B
, 0); /* COL */
1115 select_peripheral(PC(23), PERIPH_B
, 0); /* CRS */
1116 select_peripheral(PC(26), PERIPH_B
, 0); /* TXER */
1117 select_peripheral(PC(27), PERIPH_B
, 0); /* TXD2 */
1118 select_peripheral(PC(28), PERIPH_B
, 0); /* TXD3 */
1119 select_peripheral(PC(29), PERIPH_B
, 0); /* RXD2 */
1120 select_peripheral(PC(30), PERIPH_B
, 0); /* RXD3 */
1121 select_peripheral(PC(24), PERIPH_B
, 0); /* RXCK */
1122 select_peripheral(PD(15), PERIPH_B
, 0); /* SPD */
1130 memcpy(pdev
->dev
.platform_data
, data
, sizeof(struct eth_platform_data
));
1131 platform_device_register(pdev
);
1137 /* --------------------------------------------------------------------
1139 * -------------------------------------------------------------------- */
1140 static struct resource atmel_spi0_resource
[] = {
1144 DEFINE_DEV(atmel_spi
, 0);
1145 DEV_CLK(spi_clk
, atmel_spi0
, pba
, 0);
1147 static struct resource atmel_spi1_resource
[] = {
1151 DEFINE_DEV(atmel_spi
, 1);
1152 DEV_CLK(spi_clk
, atmel_spi1
, pba
, 1);
1155 at32_spi_setup_slaves(unsigned int bus_num
, struct spi_board_info
*b
,
1156 unsigned int n
, const u8
*pins
)
1158 unsigned int pin
, mode
;
1160 for (; n
; n
--, b
++) {
1161 b
->bus_num
= bus_num
;
1162 if (b
->chip_select
>= 4)
1164 pin
= (unsigned)b
->controller_data
;
1166 pin
= pins
[b
->chip_select
];
1167 b
->controller_data
= (void *)pin
;
1169 mode
= AT32_GPIOF_OUTPUT
;
1170 if (!(b
->mode
& SPI_CS_HIGH
))
1171 mode
|= AT32_GPIOF_HIGH
;
1172 at32_select_gpio(pin
, mode
);
1176 struct platform_device
*__init
1177 at32_add_device_spi(unsigned int id
, struct spi_board_info
*b
, unsigned int n
)
1180 * Manage the chipselects as GPIOs, normally using the same pins
1181 * the SPI controller expects; but boards can use other pins.
1183 static u8 __initdata spi0_pins
[] =
1184 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1185 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1186 static u8 __initdata spi1_pins
[] =
1187 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1188 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1189 struct platform_device
*pdev
;
1193 pdev
= &atmel_spi0_device
;
1194 /* pullup MISO so a level is always defined */
1195 select_peripheral(PA(0), PERIPH_A
, AT32_GPIOF_PULLUP
);
1196 select_peripheral(PA(1), PERIPH_A
, 0); /* MOSI */
1197 select_peripheral(PA(2), PERIPH_A
, 0); /* SCK */
1198 at32_spi_setup_slaves(0, b
, n
, spi0_pins
);
1202 pdev
= &atmel_spi1_device
;
1203 /* pullup MISO so a level is always defined */
1204 select_peripheral(PB(0), PERIPH_B
, AT32_GPIOF_PULLUP
);
1205 select_peripheral(PB(1), PERIPH_B
, 0); /* MOSI */
1206 select_peripheral(PB(5), PERIPH_B
, 0); /* SCK */
1207 at32_spi_setup_slaves(1, b
, n
, spi1_pins
);
1214 spi_register_board_info(b
, n
);
1215 platform_device_register(pdev
);
1219 /* --------------------------------------------------------------------
1221 * -------------------------------------------------------------------- */
1222 static struct resource atmel_twi0_resource
[] __initdata
= {
1226 static struct clk atmel_twi0_pclk
= {
1229 .mode
= pba_clk_mode
,
1230 .get_rate
= pba_clk_get_rate
,
1234 struct platform_device
*__init
at32_add_device_twi(unsigned int id
,
1235 struct i2c_board_info
*b
,
1238 struct platform_device
*pdev
;
1243 pdev
= platform_device_alloc("atmel_twi", id
);
1247 if (platform_device_add_resources(pdev
, atmel_twi0_resource
,
1248 ARRAY_SIZE(atmel_twi0_resource
)))
1249 goto err_add_resources
;
1251 select_peripheral(PA(6), PERIPH_A
, 0); /* SDA */
1252 select_peripheral(PA(7), PERIPH_A
, 0); /* SDL */
1254 atmel_twi0_pclk
.dev
= &pdev
->dev
;
1257 i2c_register_board_info(id
, b
, n
);
1259 platform_device_add(pdev
);
1263 platform_device_put(pdev
);
1267 /* --------------------------------------------------------------------
1269 * -------------------------------------------------------------------- */
1270 static struct resource atmel_mci0_resource
[] __initdata
= {
1274 static struct clk atmel_mci0_pclk
= {
1277 .mode
= pbb_clk_mode
,
1278 .get_rate
= pbb_clk_get_rate
,
1282 struct platform_device
*__init
1283 at32_add_device_mci(unsigned int id
, struct mci_platform_data
*data
)
1285 struct mci_platform_data _data
;
1286 struct platform_device
*pdev
;
1287 struct dw_dma_slave
*dws
;
1292 pdev
= platform_device_alloc("atmel_mci", id
);
1296 if (platform_device_add_resources(pdev
, atmel_mci0_resource
,
1297 ARRAY_SIZE(atmel_mci0_resource
)))
1302 memset(data
, 0, sizeof(struct mci_platform_data
));
1305 if (platform_device_add_data(pdev
, data
,
1306 sizeof(struct mci_platform_data
)))
1309 select_peripheral(PA(10), PERIPH_A
, 0); /* CLK */
1310 select_peripheral(PA(11), PERIPH_A
, 0); /* CMD */
1311 select_peripheral(PA(12), PERIPH_A
, 0); /* DATA0 */
1312 select_peripheral(PA(13), PERIPH_A
, 0); /* DATA1 */
1313 select_peripheral(PA(14), PERIPH_A
, 0); /* DATA2 */
1314 select_peripheral(PA(15), PERIPH_A
, 0); /* DATA3 */
1317 if (data
->detect_pin
!= GPIO_PIN_NONE
)
1318 at32_select_gpio(data
->detect_pin
, 0);
1319 if (data
->wp_pin
!= GPIO_PIN_NONE
)
1320 at32_select_gpio(data
->wp_pin
, 0);
1323 atmel_mci0_pclk
.dev
= &pdev
->dev
;
1325 platform_device_add(pdev
);
1329 platform_device_put(pdev
);
1333 /* --------------------------------------------------------------------
1335 * -------------------------------------------------------------------- */
1336 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1337 static struct atmel_lcdfb_info atmel_lcdfb0_data
;
1338 static struct resource atmel_lcdfb0_resource
[] = {
1340 .start
= 0xff000000,
1342 .flags
= IORESOURCE_MEM
,
1346 /* Placeholder for pre-allocated fb memory */
1347 .start
= 0x00000000,
1352 DEFINE_DEV_DATA(atmel_lcdfb
, 0);
1353 DEV_CLK(hck1
, atmel_lcdfb0
, hsb
, 7);
1354 static struct clk atmel_lcdfb0_pixclk
= {
1356 .dev
= &atmel_lcdfb0_device
.dev
,
1357 .mode
= genclk_mode
,
1358 .get_rate
= genclk_get_rate
,
1359 .set_rate
= genclk_set_rate
,
1360 .set_parent
= genclk_set_parent
,
1364 struct platform_device
*__init
1365 at32_add_device_lcdc(unsigned int id
, struct atmel_lcdfb_info
*data
,
1366 unsigned long fbmem_start
, unsigned long fbmem_len
,
1367 unsigned int pin_config
)
1369 struct platform_device
*pdev
;
1370 struct atmel_lcdfb_info
*info
;
1371 struct fb_monspecs
*monspecs
;
1372 struct fb_videomode
*modedb
;
1373 unsigned int modedb_size
;
1376 * Do a deep copy of the fb data, monspecs and modedb. Make
1377 * sure all allocations are done before setting up the
1380 monspecs
= kmemdup(data
->default_monspecs
,
1381 sizeof(struct fb_monspecs
), GFP_KERNEL
);
1385 modedb_size
= sizeof(struct fb_videomode
) * monspecs
->modedb_len
;
1386 modedb
= kmemdup(monspecs
->modedb
, modedb_size
, GFP_KERNEL
);
1388 goto err_dup_modedb
;
1389 monspecs
->modedb
= modedb
;
1393 pdev
= &atmel_lcdfb0_device
;
1395 switch (pin_config
) {
1397 select_peripheral(PC(19), PERIPH_A
, 0); /* CC */
1398 select_peripheral(PC(20), PERIPH_A
, 0); /* HSYNC */
1399 select_peripheral(PC(21), PERIPH_A
, 0); /* PCLK */
1400 select_peripheral(PC(22), PERIPH_A
, 0); /* VSYNC */
1401 select_peripheral(PC(23), PERIPH_A
, 0); /* DVAL */
1402 select_peripheral(PC(24), PERIPH_A
, 0); /* MODE */
1403 select_peripheral(PC(25), PERIPH_A
, 0); /* PWR */
1404 select_peripheral(PC(26), PERIPH_A
, 0); /* DATA0 */
1405 select_peripheral(PC(27), PERIPH_A
, 0); /* DATA1 */
1406 select_peripheral(PC(28), PERIPH_A
, 0); /* DATA2 */
1407 select_peripheral(PC(29), PERIPH_A
, 0); /* DATA3 */
1408 select_peripheral(PC(30), PERIPH_A
, 0); /* DATA4 */
1409 select_peripheral(PC(31), PERIPH_A
, 0); /* DATA5 */
1410 select_peripheral(PD(0), PERIPH_A
, 0); /* DATA6 */
1411 select_peripheral(PD(1), PERIPH_A
, 0); /* DATA7 */
1412 select_peripheral(PD(2), PERIPH_A
, 0); /* DATA8 */
1413 select_peripheral(PD(3), PERIPH_A
, 0); /* DATA9 */
1414 select_peripheral(PD(4), PERIPH_A
, 0); /* DATA10 */
1415 select_peripheral(PD(5), PERIPH_A
, 0); /* DATA11 */
1416 select_peripheral(PD(6), PERIPH_A
, 0); /* DATA12 */
1417 select_peripheral(PD(7), PERIPH_A
, 0); /* DATA13 */
1418 select_peripheral(PD(8), PERIPH_A
, 0); /* DATA14 */
1419 select_peripheral(PD(9), PERIPH_A
, 0); /* DATA15 */
1420 select_peripheral(PD(10), PERIPH_A
, 0); /* DATA16 */
1421 select_peripheral(PD(11), PERIPH_A
, 0); /* DATA17 */
1422 select_peripheral(PD(12), PERIPH_A
, 0); /* DATA18 */
1423 select_peripheral(PD(13), PERIPH_A
, 0); /* DATA19 */
1424 select_peripheral(PD(14), PERIPH_A
, 0); /* DATA20 */
1425 select_peripheral(PD(15), PERIPH_A
, 0); /* DATA21 */
1426 select_peripheral(PD(16), PERIPH_A
, 0); /* DATA22 */
1427 select_peripheral(PD(17), PERIPH_A
, 0); /* DATA23 */
1430 select_peripheral(PE(0), PERIPH_B
, 0); /* CC */
1431 select_peripheral(PC(20), PERIPH_A
, 0); /* HSYNC */
1432 select_peripheral(PC(21), PERIPH_A
, 0); /* PCLK */
1433 select_peripheral(PC(22), PERIPH_A
, 0); /* VSYNC */
1434 select_peripheral(PE(1), PERIPH_B
, 0); /* DVAL */
1435 select_peripheral(PE(2), PERIPH_B
, 0); /* MODE */
1436 select_peripheral(PC(25), PERIPH_A
, 0); /* PWR */
1437 select_peripheral(PE(3), PERIPH_B
, 0); /* DATA0 */
1438 select_peripheral(PE(4), PERIPH_B
, 0); /* DATA1 */
1439 select_peripheral(PE(5), PERIPH_B
, 0); /* DATA2 */
1440 select_peripheral(PE(6), PERIPH_B
, 0); /* DATA3 */
1441 select_peripheral(PE(7), PERIPH_B
, 0); /* DATA4 */
1442 select_peripheral(PC(31), PERIPH_A
, 0); /* DATA5 */
1443 select_peripheral(PD(0), PERIPH_A
, 0); /* DATA6 */
1444 select_peripheral(PD(1), PERIPH_A
, 0); /* DATA7 */
1445 select_peripheral(PE(8), PERIPH_B
, 0); /* DATA8 */
1446 select_peripheral(PE(9), PERIPH_B
, 0); /* DATA9 */
1447 select_peripheral(PE(10), PERIPH_B
, 0); /* DATA10 */
1448 select_peripheral(PE(11), PERIPH_B
, 0); /* DATA11 */
1449 select_peripheral(PE(12), PERIPH_B
, 0); /* DATA12 */
1450 select_peripheral(PD(7), PERIPH_A
, 0); /* DATA13 */
1451 select_peripheral(PD(8), PERIPH_A
, 0); /* DATA14 */
1452 select_peripheral(PD(9), PERIPH_A
, 0); /* DATA15 */
1453 select_peripheral(PE(13), PERIPH_B
, 0); /* DATA16 */
1454 select_peripheral(PE(14), PERIPH_B
, 0); /* DATA17 */
1455 select_peripheral(PE(15), PERIPH_B
, 0); /* DATA18 */
1456 select_peripheral(PE(16), PERIPH_B
, 0); /* DATA19 */
1457 select_peripheral(PE(17), PERIPH_B
, 0); /* DATA20 */
1458 select_peripheral(PE(18), PERIPH_B
, 0); /* DATA21 */
1459 select_peripheral(PD(16), PERIPH_A
, 0); /* DATA22 */
1460 select_peripheral(PD(17), PERIPH_A
, 0); /* DATA23 */
1463 goto err_invalid_id
;
1466 clk_set_parent(&atmel_lcdfb0_pixclk
, &pll0
);
1467 clk_set_rate(&atmel_lcdfb0_pixclk
, clk_get_rate(&pll0
));
1471 goto err_invalid_id
;
1475 pdev
->resource
[2].start
= fbmem_start
;
1476 pdev
->resource
[2].end
= fbmem_start
+ fbmem_len
- 1;
1477 pdev
->resource
[2].flags
= IORESOURCE_MEM
;
1480 info
= pdev
->dev
.platform_data
;
1481 memcpy(info
, data
, sizeof(struct atmel_lcdfb_info
));
1482 info
->default_monspecs
= monspecs
;
1484 platform_device_register(pdev
);
1495 /* --------------------------------------------------------------------
1497 * -------------------------------------------------------------------- */
1498 static struct resource atmel_pwm0_resource
[] __initdata
= {
1502 static struct clk atmel_pwm0_mck
= {
1505 .mode
= pbb_clk_mode
,
1506 .get_rate
= pbb_clk_get_rate
,
1510 struct platform_device
*__init
at32_add_device_pwm(u32 mask
)
1512 struct platform_device
*pdev
;
1517 pdev
= platform_device_alloc("atmel_pwm", 0);
1521 if (platform_device_add_resources(pdev
, atmel_pwm0_resource
,
1522 ARRAY_SIZE(atmel_pwm0_resource
)))
1525 if (platform_device_add_data(pdev
, &mask
, sizeof(mask
)))
1528 if (mask
& (1 << 0))
1529 select_peripheral(PA(28), PERIPH_A
, 0);
1530 if (mask
& (1 << 1))
1531 select_peripheral(PA(29), PERIPH_A
, 0);
1532 if (mask
& (1 << 2))
1533 select_peripheral(PA(21), PERIPH_B
, 0);
1534 if (mask
& (1 << 3))
1535 select_peripheral(PA(22), PERIPH_B
, 0);
1537 atmel_pwm0_mck
.dev
= &pdev
->dev
;
1539 platform_device_add(pdev
);
1544 platform_device_put(pdev
);
1548 /* --------------------------------------------------------------------
1550 * -------------------------------------------------------------------- */
1551 static struct resource ssc0_resource
[] = {
1556 DEV_CLK(pclk
, ssc0
, pba
, 7);
1558 static struct resource ssc1_resource
[] = {
1563 DEV_CLK(pclk
, ssc1
, pba
, 8);
1565 static struct resource ssc2_resource
[] = {
1570 DEV_CLK(pclk
, ssc2
, pba
, 9);
1572 struct platform_device
*__init
1573 at32_add_device_ssc(unsigned int id
, unsigned int flags
)
1575 struct platform_device
*pdev
;
1579 pdev
= &ssc0_device
;
1580 if (flags
& ATMEL_SSC_RF
)
1581 select_peripheral(PA(21), PERIPH_A
, 0); /* RF */
1582 if (flags
& ATMEL_SSC_RK
)
1583 select_peripheral(PA(22), PERIPH_A
, 0); /* RK */
1584 if (flags
& ATMEL_SSC_TK
)
1585 select_peripheral(PA(23), PERIPH_A
, 0); /* TK */
1586 if (flags
& ATMEL_SSC_TF
)
1587 select_peripheral(PA(24), PERIPH_A
, 0); /* TF */
1588 if (flags
& ATMEL_SSC_TD
)
1589 select_peripheral(PA(25), PERIPH_A
, 0); /* TD */
1590 if (flags
& ATMEL_SSC_RD
)
1591 select_peripheral(PA(26), PERIPH_A
, 0); /* RD */
1594 pdev
= &ssc1_device
;
1595 if (flags
& ATMEL_SSC_RF
)
1596 select_peripheral(PA(0), PERIPH_B
, 0); /* RF */
1597 if (flags
& ATMEL_SSC_RK
)
1598 select_peripheral(PA(1), PERIPH_B
, 0); /* RK */
1599 if (flags
& ATMEL_SSC_TK
)
1600 select_peripheral(PA(2), PERIPH_B
, 0); /* TK */
1601 if (flags
& ATMEL_SSC_TF
)
1602 select_peripheral(PA(3), PERIPH_B
, 0); /* TF */
1603 if (flags
& ATMEL_SSC_TD
)
1604 select_peripheral(PA(4), PERIPH_B
, 0); /* TD */
1605 if (flags
& ATMEL_SSC_RD
)
1606 select_peripheral(PA(5), PERIPH_B
, 0); /* RD */
1609 pdev
= &ssc2_device
;
1610 if (flags
& ATMEL_SSC_TD
)
1611 select_peripheral(PB(13), PERIPH_A
, 0); /* TD */
1612 if (flags
& ATMEL_SSC_RD
)
1613 select_peripheral(PB(14), PERIPH_A
, 0); /* RD */
1614 if (flags
& ATMEL_SSC_TK
)
1615 select_peripheral(PB(15), PERIPH_A
, 0); /* TK */
1616 if (flags
& ATMEL_SSC_TF
)
1617 select_peripheral(PB(16), PERIPH_A
, 0); /* TF */
1618 if (flags
& ATMEL_SSC_RF
)
1619 select_peripheral(PB(17), PERIPH_A
, 0); /* RF */
1620 if (flags
& ATMEL_SSC_RK
)
1621 select_peripheral(PB(18), PERIPH_A
, 0); /* RK */
1627 platform_device_register(pdev
);
1631 /* --------------------------------------------------------------------
1632 * USB Device Controller
1633 * -------------------------------------------------------------------- */
1634 static struct resource usba0_resource
[] __initdata
= {
1636 .start
= 0xff300000,
1638 .flags
= IORESOURCE_MEM
,
1640 .start
= 0xfff03000,
1642 .flags
= IORESOURCE_MEM
,
1646 static struct clk usba0_pclk
= {
1649 .mode
= pbb_clk_mode
,
1650 .get_rate
= pbb_clk_get_rate
,
1653 static struct clk usba0_hclk
= {
1656 .mode
= hsb_clk_mode
,
1657 .get_rate
= hsb_clk_get_rate
,
1661 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1665 .fifo_size = maxpkt, \
1666 .nr_banks = maxbk, \
1671 static struct usba_ep_data at32_usba_ep
[] __initdata
= {
1672 EP("ep0", 0, 64, 1, 0, 0),
1673 EP("ep1", 1, 512, 2, 1, 1),
1674 EP("ep2", 2, 512, 2, 1, 1),
1675 EP("ep3-int", 3, 64, 3, 1, 0),
1676 EP("ep4-int", 4, 64, 3, 1, 0),
1677 EP("ep5", 5, 1024, 3, 1, 1),
1678 EP("ep6", 6, 1024, 3, 1, 1),
1683 struct platform_device
*__init
1684 at32_add_device_usba(unsigned int id
, struct usba_platform_data
*data
)
1687 * pdata doesn't have room for any endpoints, so we need to
1688 * append room for the ones we need right after it.
1691 struct usba_platform_data pdata
;
1692 struct usba_ep_data ep
[7];
1694 struct platform_device
*pdev
;
1699 pdev
= platform_device_alloc("atmel_usba_udc", 0);
1703 if (platform_device_add_resources(pdev
, usba0_resource
,
1704 ARRAY_SIZE(usba0_resource
)))
1708 usba_data
.pdata
.vbus_pin
= data
->vbus_pin
;
1710 usba_data
.pdata
.vbus_pin
= -EINVAL
;
1712 data
= &usba_data
.pdata
;
1713 data
->num_ep
= ARRAY_SIZE(at32_usba_ep
);
1714 memcpy(data
->ep
, at32_usba_ep
, sizeof(at32_usba_ep
));
1716 if (platform_device_add_data(pdev
, data
, sizeof(usba_data
)))
1719 if (data
->vbus_pin
>= 0)
1720 at32_select_gpio(data
->vbus_pin
, 0);
1722 usba0_pclk
.dev
= &pdev
->dev
;
1723 usba0_hclk
.dev
= &pdev
->dev
;
1725 platform_device_add(pdev
);
1730 platform_device_put(pdev
);
1734 /* --------------------------------------------------------------------
1735 * IDE / CompactFlash
1736 * -------------------------------------------------------------------- */
1737 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1738 static struct resource at32_smc_cs4_resource
[] __initdata
= {
1740 .start
= 0x04000000,
1742 .flags
= IORESOURCE_MEM
,
1744 IRQ(~0UL), /* Magic IRQ will be overridden */
1746 static struct resource at32_smc_cs5_resource
[] __initdata
= {
1748 .start
= 0x20000000,
1750 .flags
= IORESOURCE_MEM
,
1752 IRQ(~0UL), /* Magic IRQ will be overridden */
1755 static int __init
at32_init_ide_or_cf(struct platform_device
*pdev
,
1756 unsigned int cs
, unsigned int extint
)
1758 static unsigned int extint_pin_map
[4] __initdata
= {
1764 static bool common_pins_initialized __initdata
= false;
1765 unsigned int extint_pin
;
1768 if (extint
>= ARRAY_SIZE(extint_pin_map
))
1770 extint_pin
= extint_pin_map
[extint
];
1774 ret
= platform_device_add_resources(pdev
,
1775 at32_smc_cs4_resource
,
1776 ARRAY_SIZE(at32_smc_cs4_resource
));
1780 select_peripheral(PE(21), PERIPH_A
, 0); /* NCS4 -> OE_N */
1781 set_ebi_sfr_bits(HMATRIX_BIT(CS4A
));
1784 ret
= platform_device_add_resources(pdev
,
1785 at32_smc_cs5_resource
,
1786 ARRAY_SIZE(at32_smc_cs5_resource
));
1790 select_peripheral(PE(22), PERIPH_A
, 0); /* NCS5 -> OE_N */
1791 set_ebi_sfr_bits(HMATRIX_BIT(CS5A
));
1797 if (!common_pins_initialized
) {
1798 select_peripheral(PE(19), PERIPH_A
, 0); /* CFCE1 -> CS0_N */
1799 select_peripheral(PE(20), PERIPH_A
, 0); /* CFCE2 -> CS1_N */
1800 select_peripheral(PE(23), PERIPH_A
, 0); /* CFRNW -> DIR */
1801 select_peripheral(PE(24), PERIPH_A
, 0); /* NWAIT <- IORDY */
1802 common_pins_initialized
= true;
1805 at32_select_periph(extint_pin
, GPIO_PERIPH_A
, AT32_GPIOF_DEGLITCH
);
1807 pdev
->resource
[1].start
= EIM_IRQ_BASE
+ extint
;
1808 pdev
->resource
[1].end
= pdev
->resource
[1].start
;
1813 struct platform_device
*__init
1814 at32_add_device_ide(unsigned int id
, unsigned int extint
,
1815 struct ide_platform_data
*data
)
1817 struct platform_device
*pdev
;
1819 pdev
= platform_device_alloc("at32_ide", id
);
1823 if (platform_device_add_data(pdev
, data
,
1824 sizeof(struct ide_platform_data
)))
1827 if (at32_init_ide_or_cf(pdev
, data
->cs
, extint
))
1830 platform_device_add(pdev
);
1834 platform_device_put(pdev
);
1838 struct platform_device
*__init
1839 at32_add_device_cf(unsigned int id
, unsigned int extint
,
1840 struct cf_platform_data
*data
)
1842 struct platform_device
*pdev
;
1844 pdev
= platform_device_alloc("at32_cf", id
);
1848 if (platform_device_add_data(pdev
, data
,
1849 sizeof(struct cf_platform_data
)))
1852 if (at32_init_ide_or_cf(pdev
, data
->cs
, extint
))
1855 if (data
->detect_pin
!= GPIO_PIN_NONE
)
1856 at32_select_gpio(data
->detect_pin
, AT32_GPIOF_DEGLITCH
);
1857 if (data
->reset_pin
!= GPIO_PIN_NONE
)
1858 at32_select_gpio(data
->reset_pin
, 0);
1859 if (data
->vcc_pin
!= GPIO_PIN_NONE
)
1860 at32_select_gpio(data
->vcc_pin
, 0);
1861 /* READY is used as extint, so we can't select it as gpio */
1863 platform_device_add(pdev
);
1867 platform_device_put(pdev
);
1872 /* --------------------------------------------------------------------
1874 * -------------------------------------------------------------------- */
1875 static struct resource atmel_ac97c0_resource
[] __initdata
= {
1879 static struct clk atmel_ac97c0_pclk
= {
1882 .mode
= pbb_clk_mode
,
1883 .get_rate
= pbb_clk_get_rate
,
1887 struct platform_device
*__init
at32_add_device_ac97c(unsigned int id
)
1889 struct platform_device
*pdev
;
1894 pdev
= platform_device_alloc("atmel_ac97c", id
);
1898 if (platform_device_add_resources(pdev
, atmel_ac97c0_resource
,
1899 ARRAY_SIZE(atmel_ac97c0_resource
)))
1900 goto err_add_resources
;
1902 select_peripheral(PB(20), PERIPH_B
, 0); /* SYNC */
1903 select_peripheral(PB(21), PERIPH_B
, 0); /* SDO */
1904 select_peripheral(PB(22), PERIPH_B
, 0); /* SDI */
1905 select_peripheral(PB(23), PERIPH_B
, 0); /* SCLK */
1907 atmel_ac97c0_pclk
.dev
= &pdev
->dev
;
1909 platform_device_add(pdev
);
1913 platform_device_put(pdev
);
1917 /* --------------------------------------------------------------------
1919 * -------------------------------------------------------------------- */
1920 static struct resource abdac0_resource
[] __initdata
= {
1924 static struct clk abdac0_pclk
= {
1927 .mode
= pbb_clk_mode
,
1928 .get_rate
= pbb_clk_get_rate
,
1931 static struct clk abdac0_sample_clk
= {
1932 .name
= "sample_clk",
1933 .mode
= genclk_mode
,
1934 .get_rate
= genclk_get_rate
,
1935 .set_rate
= genclk_set_rate
,
1936 .set_parent
= genclk_set_parent
,
1940 struct platform_device
*__init
at32_add_device_abdac(unsigned int id
)
1942 struct platform_device
*pdev
;
1947 pdev
= platform_device_alloc("abdac", id
);
1951 if (platform_device_add_resources(pdev
, abdac0_resource
,
1952 ARRAY_SIZE(abdac0_resource
)))
1953 goto err_add_resources
;
1955 select_peripheral(PB(20), PERIPH_A
, 0); /* DATA1 */
1956 select_peripheral(PB(21), PERIPH_A
, 0); /* DATA0 */
1957 select_peripheral(PB(22), PERIPH_A
, 0); /* DATAN1 */
1958 select_peripheral(PB(23), PERIPH_A
, 0); /* DATAN0 */
1960 abdac0_pclk
.dev
= &pdev
->dev
;
1961 abdac0_sample_clk
.dev
= &pdev
->dev
;
1963 platform_device_add(pdev
);
1967 platform_device_put(pdev
);
1971 /* --------------------------------------------------------------------
1973 * -------------------------------------------------------------------- */
1974 static struct clk gclk0
= {
1976 .mode
= genclk_mode
,
1977 .get_rate
= genclk_get_rate
,
1978 .set_rate
= genclk_set_rate
,
1979 .set_parent
= genclk_set_parent
,
1982 static struct clk gclk1
= {
1984 .mode
= genclk_mode
,
1985 .get_rate
= genclk_get_rate
,
1986 .set_rate
= genclk_set_rate
,
1987 .set_parent
= genclk_set_parent
,
1990 static struct clk gclk2
= {
1992 .mode
= genclk_mode
,
1993 .get_rate
= genclk_get_rate
,
1994 .set_rate
= genclk_set_rate
,
1995 .set_parent
= genclk_set_parent
,
1998 static struct clk gclk3
= {
2000 .mode
= genclk_mode
,
2001 .get_rate
= genclk_get_rate
,
2002 .set_rate
= genclk_set_rate
,
2003 .set_parent
= genclk_set_parent
,
2006 static struct clk gclk4
= {
2008 .mode
= genclk_mode
,
2009 .get_rate
= genclk_get_rate
,
2010 .set_rate
= genclk_set_rate
,
2011 .set_parent
= genclk_set_parent
,
2015 struct clk
*at32_clock_list
[] = {
2046 &atmel_usart0_usart
,
2047 &atmel_usart1_usart
,
2048 &atmel_usart2_usart
,
2049 &atmel_usart3_usart
,
2051 #if defined(CONFIG_CPU_AT32AP7000)
2057 &atmel_spi0_spi_clk
,
2058 &atmel_spi1_spi_clk
,
2061 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2063 &atmel_lcdfb0_pixclk
,
2079 unsigned int at32_nr_clocks
= ARRAY_SIZE(at32_clock_list
);
2081 void __init
setup_platform(void)
2083 u32 cpu_mask
= 0, hsb_mask
= 0, pba_mask
= 0, pbb_mask
= 0;
2086 if (pm_readl(MCCTRL
) & PM_BIT(PLLSEL
)) {
2088 cpu_clk
.parent
= &pll0
;
2091 cpu_clk
.parent
= &osc0
;
2094 if (pm_readl(PLL0
) & PM_BIT(PLLOSC
))
2095 pll0
.parent
= &osc1
;
2096 if (pm_readl(PLL1
) & PM_BIT(PLLOSC
))
2097 pll1
.parent
= &osc1
;
2099 genclk_init_parent(&gclk0
);
2100 genclk_init_parent(&gclk1
);
2101 genclk_init_parent(&gclk2
);
2102 genclk_init_parent(&gclk3
);
2103 genclk_init_parent(&gclk4
);
2104 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2105 genclk_init_parent(&atmel_lcdfb0_pixclk
);
2107 genclk_init_parent(&abdac0_sample_clk
);
2110 * Turn on all clocks that have at least one user already, and
2111 * turn off everything else. We only do this for module
2112 * clocks, and even though it isn't particularly pretty to
2113 * check the address of the mode function, it should do the
2116 for (i
= 0; i
< ARRAY_SIZE(at32_clock_list
); i
++) {
2117 struct clk
*clk
= at32_clock_list
[i
];
2119 if (clk
->users
== 0)
2122 if (clk
->mode
== &cpu_clk_mode
)
2123 cpu_mask
|= 1 << clk
->index
;
2124 else if (clk
->mode
== &hsb_clk_mode
)
2125 hsb_mask
|= 1 << clk
->index
;
2126 else if (clk
->mode
== &pba_clk_mode
)
2127 pba_mask
|= 1 << clk
->index
;
2128 else if (clk
->mode
== &pbb_clk_mode
)
2129 pbb_mask
|= 1 << clk
->index
;
2132 pm_writel(CPU_MASK
, cpu_mask
);
2133 pm_writel(HSB_MASK
, hsb_mask
);
2134 pm_writel(PBA_MASK
, pba_mask
);
2135 pm_writel(PBB_MASK
, pbb_mask
);
2137 /* Initialize the port muxes */
2138 at32_init_pio(&pio0_device
);
2139 at32_init_pio(&pio1_device
);
2140 at32_init_pio(&pio2_device
);
2141 at32_init_pio(&pio3_device
);
2142 at32_init_pio(&pio4_device
);
2145 struct gen_pool
*sram_pool
;
2147 static int __init
sram_init(void)
2149 struct gen_pool
*pool
;
2151 /* 1KiB granularity */
2152 pool
= gen_pool_create(10, -1);
2156 if (gen_pool_add(pool
, 0x24000000, 0x8000, -1))
2163 gen_pool_destroy(pool
);
2165 pr_err("Failed to create SRAM pool\n");
2168 core_initcall(sram_init
);