arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29
  30 config ZONE_DMA
  31         bool
  32         default y
  33
  34 config GENERIC_FIND_NEXT_BIT
  35         bool
  36         default y
  37
  38 config GENERIC_HWEIGHT
  39         bool
  40         default y
  41
  42 config GENERIC_HARDIRQS
  43         bool
  44         default y
  45
  46 config GENERIC_IRQ_PROBE
  47         bool
  48         default y
  49
  50 config GENERIC_GPIO
  51         bool
  52         default y
  53
  54 config FORCE_MAX_ZONEORDER
  55         int
  56         default "14"
  57
  58 config GENERIC_CALIBRATE_DELAY
  59         bool
  60         default y
  61
  62 config HARDWARE_PM
  63         def_bool y
  64         depends on OPROFILE
  65
  66 source "init/Kconfig"
  67 source "kernel/Kconfig.preempt"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF522
  78         bool "BF522"
  79         help
  80           BF522 Processor Support.
  81
  82 config BF523
  83         bool "BF523"
  84         help
  85           BF523 Processor Support.
  86
  87 config BF524
  88         bool "BF524"
  89         help
  90           BF524 Processor Support.
  91
  92 config BF525
  93         bool "BF525"
  94         help
  95           BF525 Processor Support.
  96
  97 config BF526
  98         bool "BF526"
  99         help
 100           BF526 Processor Support.
 101
 102 config BF527
 103         bool "BF527"
 104         help
 105           BF527 Processor Support.
 106
 107 config BF531
 108         bool "BF531"
 109         help
 110           BF531 Processor Support.
 111
 112 config BF532
 113         bool "BF532"
 114         help
 115           BF532 Processor Support.
 116
 117 config BF533
 118         bool "BF533"
 119         help
 120           BF533 Processor Support.
 121
 122 config BF534
 123         bool "BF534"
 124         help
 125           BF534 Processor Support.
 126
 127 config BF536
 128         bool "BF536"
 129         help
 130           BF536 Processor Support.
 131
 132 config BF537
 133         bool "BF537"
 134         help
 135           BF537 Processor Support.
 136
 137 config BF542
 138         bool "BF542"
 139         help
 140           BF542 Processor Support.
 141
 142 config BF544
 143         bool "BF544"
 144         help
 145           BF544 Processor Support.
 146
 147 config BF547
 148         bool "BF547"
 149         help
 150           BF547 Processor Support.
 151
 152 config BF548
 153         bool "BF548"
 154         help
 155           BF548 Processor Support.
 156
 157 config BF549
 158         bool "BF549"
 159         help
 160           BF549 Processor Support.
 161
 162 config BF561
 163         bool "BF561"
 164         help
 165           Not Supported Yet - Work in progress - BF561 Processor Support.
 166
 167 endchoice
 168
 169 choice
 170         prompt "Silicon Rev"
 171         default BF_REV_0_1 if BF527
 172         default BF_REV_0_2 if BF537
 173         default BF_REV_0_3 if BF533
 174         default BF_REV_0_0 if BF549
 175
 176 config BF_REV_0_0
 177         bool "0.0"
 178         depends on (BF52x || BF54x)
 179
 180 config BF_REV_0_1
 181         bool "0.1"
 182         depends on (BF52x || BF54x)
 183
 184 config BF_REV_0_2
 185         bool "0.2"
 186         depends on (BF537 || BF536 || BF534)
 187
 188 config BF_REV_0_3
 189         bool "0.3"
 190         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 191
 192 config BF_REV_0_4
 193         bool "0.4"
 194         depends on (BF561 || BF533 || BF532 || BF531)
 195
 196 config BF_REV_0_5
 197         bool "0.5"
 198         depends on (BF561 || BF533 || BF532 || BF531)
 199
 200 config BF_REV_ANY
 201         bool "any"
 202
 203 config BF_REV_NONE
 204         bool "none"
 205
 206 endchoice
 207
 208 config BF52x
 209         bool
 210         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 211         default y
 212
 213 config BF53x
 214         bool
 215         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 216         default y
 217
 218 config BF54x
 219         bool
 220         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 221         default y
 222
 223 config BFIN_DUAL_CORE
 224         bool
 225         depends on (BF561)
 226         default y
 227
 228 config BFIN_SINGLE_CORE
 229         bool
 230         depends on !BFIN_DUAL_CORE
 231         default y
 232
 233 config MEM_GENERIC_BOARD
 234         bool
 235         depends on GENERIC_BOARD
 236         default y
 237
 238 config MEM_MT48LC64M4A2FB_7E
 239         bool
 240         depends on (BFIN533_STAMP)
 241         default y
 242
 243 config MEM_MT48LC16M16A2TG_75
 244         bool
 245         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 246                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 247                 || H8606_HVSISTEMAS)
 248         default y
 249
 250 config MEM_MT48LC32M8A2_75
 251         bool
 252         depends on (BFIN537_STAMP || PNAV10)
 253         default y
 254
 255 config MEM_MT48LC8M32B2B5_7
 256         bool
 257         depends on (BFIN561_BLUETECHNIX_CM)
 258         default y
 259
 260 config MEM_MT48LC32M16A2TG_75
 261         bool
 262         depends on (BFIN527_EZKIT)
 263         default y
 264
 265 source "arch/blackfin/mach-bf527/Kconfig"
 266 source "arch/blackfin/mach-bf533/Kconfig"
 267 source "arch/blackfin/mach-bf561/Kconfig"
 268 source "arch/blackfin/mach-bf537/Kconfig"
 269 source "arch/blackfin/mach-bf548/Kconfig"
 270
 271 menu "Board customizations"
 272
 273 config CMDLINE_BOOL
 274         bool "Default bootloader kernel arguments"
 275
 276 config CMDLINE
 277         string "Initial kernel command string"
 278         depends on CMDLINE_BOOL
 279         default "console=ttyBF0,57600"
 280         help
 281           If you don't have a boot loader capable of passing a command line string
 282           to the kernel, you may specify one here. As a minimum, you should specify
 283           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 284
 285 comment "Clock/PLL Setup"
 286
 287 config CLKIN_HZ
 288         int "Crystal Frequency in Hz"
 289         default "11059200" if BFIN533_STAMP
 290         default "27000000" if BFIN533_EZKIT
 291         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
 292         default "30000000" if BFIN561_EZKIT
 293         default "24576000" if PNAV10
 294         help
 295           The frequency of CLKIN crystal oscillator on the board in Hz.
 296
 297 config BFIN_KERNEL_CLOCK
 298         bool "Re-program Clocks while Kernel boots?"
 299         default n
 300         help
 301           This option decides if kernel clocks are re-programed from the
 302           bootloader settings. If the clocks are not set, the SDRAM settings
 303           are also not changed, and the Bootloader does 100% of the hardware
 304           configuration.
 305
 306 config PLL_BYPASS
 307         bool "Bypass PLL"
 308         depends on BFIN_KERNEL_CLOCK
 309         default n
 310
 311 config CLKIN_HALF
 312         bool "Half Clock In"
 313         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 314         default n
 315         help
 316           If this is set the clock will be divided by 2, before it goes to the PLL.
 317
 318 config VCO_MULT
 319         int "VCO Multiplier"
 320         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 321         range 1 64
 322         default "22" if BFIN533_EZKIT
 323         default "45" if BFIN533_STAMP
 324         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
 325         default "22" if BFIN533_BLUETECHNIX_CM
 326         default "20" if BFIN537_BLUETECHNIX_CM
 327         default "20" if BFIN561_BLUETECHNIX_CM
 328         default "20" if BFIN561_EZKIT
 329         default "16" if H8606_HVSISTEMAS
 330         help
 331           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 332           PLL Frequency = (Crystal Frequency) * (this setting)
 333
 334 choice
 335         prompt "Core Clock Divider"
 336         depends on BFIN_KERNEL_CLOCK
 337         default CCLK_DIV_1
 338         help
 339           This sets the frequency of the core. It can be 1, 2, 4 or 8
 340           Core Frequency = (PLL frequency) / (this setting)
 341
 342 config CCLK_DIV_1
 343         bool "1"
 344
 345 config CCLK_DIV_2
 346         bool "2"
 347
 348 config CCLK_DIV_4
 349         bool "4"
 350
 351 config CCLK_DIV_8
 352         bool "8"
 353 endchoice
 354
 355 config SCLK_DIV
 356         int "System Clock Divider"
 357         depends on BFIN_KERNEL_CLOCK
 358         range 1 15
 359         default 5 if BFIN533_EZKIT
 360         default 5 if BFIN533_STAMP
 361         default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
 362         default 5 if BFIN533_BLUETECHNIX_CM
 363         default 4 if BFIN537_BLUETECHNIX_CM
 364         default 4 if BFIN561_BLUETECHNIX_CM
 365         default 5 if BFIN561_EZKIT
 366         default 3 if H8606_HVSISTEMAS
 367         help
 368           This sets the frequency of the system clock (including SDRAM or DDR).
 369           This can be between 1 and 15
 370           System Clock = (PLL frequency) / (this setting)
 371
 372 #
 373 # Max & Min Speeds for various Chips
 374 #
 375 config MAX_VCO_HZ
 376         int
 377         default 600000000 if BF522
 378         default 400000000 if BF523
 379         default 400000000 if BF524
 380         default 600000000 if BF525
 381         default 400000000 if BF526
 382         default 600000000 if BF527
 383         default 400000000 if BF531
 384         default 400000000 if BF532
 385         default 750000000 if BF533
 386         default 500000000 if BF534
 387         default 400000000 if BF536
 388         default 600000000 if BF537
 389         default 533333333 if BF538
 390         default 533333333 if BF539
 391         default 600000000 if BF542
 392         default 533333333 if BF544
 393         default 600000000 if BF547
 394         default 600000000 if BF548
 395         default 533333333 if BF549
 396         default 600000000 if BF561
 397
 398 config MIN_VCO_HZ
 399         int
 400         default 50000000
 401
 402 config MAX_SCLK_HZ
 403         int
 404         default 133333333
 405
 406 config MIN_SCLK_HZ
 407         int
 408         default 27000000
 409
 410 comment "Kernel Timer/Scheduler"
 411
 412 source kernel/Kconfig.hz
 413
 414 config GENERIC_TIME
 415         bool "Generic time"
 416         default y
 417
 418 config GENERIC_CLOCKEVENTS
 419         bool "Generic clock events"
 420         depends on GENERIC_TIME
 421         default y
 422
 423 config CYCLES_CLOCKSOURCE
 424         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 425         depends on EXPERIMENTAL
 426         depends on GENERIC_CLOCKEVENTS
 427         depends on !BFIN_SCRATCH_REG_CYCLES
 428         default n
 429         help
 430           If you say Y here, you will enable support for using the 'cycles'
 431           registers as a clock source.  Doing so means you will be unable to
 432           safely write to the 'cycles' register during runtime.  You will
 433           still be able to read it (such as for performance monitoring), but
 434           writing the registers will most likely crash the kernel.
 435
 436 source kernel/time/Kconfig
 437
 438 comment "Memory Setup"
 439
 440 config MEM_SIZE
 441         int "SDRAM Memory Size in MBytes"
 442         default  32 if BFIN533_EZKIT
 443         default  64 if BFIN527_EZKIT
 444         default  64 if BFIN537_STAMP
 445         default  64 if BFIN548_EZKIT
 446         default  64 if BFIN561_EZKIT
 447         default 128 if BFIN533_STAMP
 448         default  64 if PNAV10
 449         default  32 if H8606_HVSISTEMAS
 450
 451 config MEM_ADD_WIDTH
 452         int "SDRAM Memory Address Width"
 453         depends on (!BF54x)
 454         default  9 if BFIN533_EZKIT
 455         default  9 if BFIN561_EZKIT
 456         default  9 if H8606_HVSISTEMAS
 457         default 10 if BFIN527_EZKIT
 458         default 10 if BFIN537_STAMP
 459         default 11 if BFIN533_STAMP
 460         default 10 if PNAV10
 461
 462
 463 choice
 464         prompt "DDR SDRAM Chip Type"
 465         depends on BFIN548_EZKIT
 466         default MEM_MT46V32M16_5B
 467
 468 config MEM_MT46V32M16_6T
 469         bool "MT46V32M16_6T"
 470
 471 config MEM_MT46V32M16_5B
 472         bool "MT46V32M16_5B"
 473 endchoice
 474
 475 config ENET_FLASH_PIN
 476         int "PF port/pin used for flash and ethernet sharing"
 477         depends on (BFIN533_STAMP)
 478         default  0
 479         help
 480           PF port/pin used for flash and ethernet sharing to allow other PF
 481           pins to be used on other platforms without having to touch common
 482           code.
 483           For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
 484
 485 config BOOT_LOAD
 486         hex "Kernel load address for booting"
 487         default "0x1000"
 488         range 0x1000 0x20000000
 489         help
 490           This option allows you to set the load address of the kernel.
 491           This can be useful if you are on a board which has a small amount
 492           of memory or you wish to reserve some memory at the beginning of
 493           the address space.
 494
 495           Note that you need to keep this value above 4k (0x1000) as this
 496           memory region is used to capture NULL pointer references as well
 497           as some core kernel functions.
 498
 499 choice
 500         prompt "Blackfin Exception Scratch Register"
 501         default BFIN_SCRATCH_REG_RETN
 502         help
 503           Select the resource to reserve for the Exception handler:
 504             - RETN: Non-Maskable Interrupt (NMI)
 505             - RETE: Exception Return (JTAG/ICE)
 506             - CYCLES: Performance counter
 507
 508           If you are unsure, please select "RETN".
 509
 510 config BFIN_SCRATCH_REG_RETN
 511         bool "RETN"
 512         help
 513           Use the RETN register in the Blackfin exception handler
 514           as a stack scratch register.  This means you cannot
 515           safely use NMI on the Blackfin while running Linux, but
 516           you can debug the system with a JTAG ICE and use the
 517           CYCLES performance registers.
 518
 519           If you are unsure, please select "RETN".
 520
 521 config BFIN_SCRATCH_REG_RETE
 522         bool "RETE"
 523         help
 524           Use the RETE register in the Blackfin exception handler
 525           as a stack scratch register.  This means you cannot
 526           safely use a JTAG ICE while debugging a Blackfin board,
 527           but you can safely use the CYCLES performance registers
 528           and the NMI.
 529
 530           If you are unsure, please select "RETN".
 531
 532 config BFIN_SCRATCH_REG_CYCLES
 533         bool "CYCLES"
 534         help
 535           Use the CYCLES register in the Blackfin exception handler
 536           as a stack scratch register.  This means you cannot
 537           safely use the CYCLES performance registers on a Blackfin
 538           board at anytime, but you can debug the system with a JTAG
 539           ICE and use the NMI.
 540
 541           If you are unsure, please select "RETN".
 542
 543 endchoice
 544
 545 endmenu
 546
 547
 548 menu "Blackfin Kernel Optimizations"
 549
 550 comment "Memory Optimizations"
 551
 552 config I_ENTRY_L1
 553         bool "Locate interrupt entry code in L1 Memory"
 554         default y
 555         help
 556           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 557           into L1 instruction memory. (less latency)
 558
 559 config EXCPT_IRQ_SYSC_L1
 560         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 561         default y
 562         help
 563           If enabled, the entire ASM lowlevel exception and interrupt entry code
 564           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 565           (less latency)
 566
 567 config DO_IRQ_L1
 568         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 569         default y
 570         help
 571           If enabled, the frequently called do_irq dispatcher function is linked
 572           into L1 instruction memory. (less latency)
 573
 574 config CORE_TIMER_IRQ_L1
 575         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 576         default y
 577         help
 578           If enabled, the frequently called timer_interrupt() function is linked
 579           into L1 instruction memory. (less latency)
 580
 581 config IDLE_L1
 582         bool "Locate frequently idle function in L1 Memory"
 583         default y
 584         help
 585           If enabled, the frequently called idle function is linked
 586           into L1 instruction memory. (less latency)
 587
 588 config SCHEDULE_L1
 589         bool "Locate kernel schedule function in L1 Memory"
 590         default y
 591         help
 592           If enabled, the frequently called kernel schedule is linked
 593           into L1 instruction memory. (less latency)
 594
 595 config ARITHMETIC_OPS_L1
 596         bool "Locate kernel owned arithmetic functions in L1 Memory"
 597         default y
 598         help
 599           If enabled, arithmetic functions are linked
 600           into L1 instruction memory. (less latency)
 601
 602 config ACCESS_OK_L1
 603         bool "Locate access_ok function in L1 Memory"
 604         default y
 605         help
 606           If enabled, the access_ok function is linked
 607           into L1 instruction memory. (less latency)
 608
 609 config MEMSET_L1
 610         bool "Locate memset function in L1 Memory"
 611         default y
 612         help
 613           If enabled, the memset function is linked
 614           into L1 instruction memory. (less latency)
 615
 616 config MEMCPY_L1
 617         bool "Locate memcpy function in L1 Memory"
 618         default y
 619         help
 620           If enabled, the memcpy function is linked
 621           into L1 instruction memory. (less latency)
 622
 623 config SYS_BFIN_SPINLOCK_L1
 624         bool "Locate sys_bfin_spinlock function in L1 Memory"
 625         default y
 626         help
 627           If enabled, sys_bfin_spinlock function is linked
 628           into L1 instruction memory. (less latency)
 629
 630 config IP_CHECKSUM_L1
 631         bool "Locate IP Checksum function in L1 Memory"
 632         default n
 633         help
 634           If enabled, the IP Checksum function is linked
 635           into L1 instruction memory. (less latency)
 636
 637 config CACHELINE_ALIGNED_L1
 638         bool "Locate cacheline_aligned data to L1 Data Memory"
 639         default y if !BF54x
 640         default n if BF54x
 641         depends on !BF531
 642         help
 643           If enabled, cacheline_anligned data is linked
 644           into L1 data memory. (less latency)
 645
 646 config SYSCALL_TAB_L1
 647         bool "Locate Syscall Table L1 Data Memory"
 648         default n
 649         depends on !BF531
 650         help
 651           If enabled, the Syscall LUT is linked
 652           into L1 data memory. (less latency)
 653
 654 config CPLB_SWITCH_TAB_L1
 655         bool "Locate CPLB Switch Tables L1 Data Memory"
 656         default n
 657         depends on !BF531
 658         help
 659           If enabled, the CPLB Switch Tables are linked
 660           into L1 data memory. (less latency)
 661
 662 endmenu
 663
 664
 665 choice
 666         prompt "Kernel executes from"
 667         help
 668           Choose the memory type that the kernel will be running in.
 669
 670 config RAMKERNEL
 671         bool "RAM"
 672         help
 673           The kernel will be resident in RAM when running.
 674
 675 config ROMKERNEL
 676         bool "ROM"
 677         help
 678           The kernel will be resident in FLASH/ROM when running.
 679
 680 endchoice
 681
 682 source "mm/Kconfig"
 683
 684 config LARGE_ALLOCS
 685         bool "Allow allocating large blocks (> 1MB) of memory"
 686         help
 687           Allow the slab memory allocator to keep chains for very large
 688           memory sizes - upto 32MB. You may need this if your system has
 689           a lot of RAM, and you need to able to allocate very large
 690           contiguous chunks. If unsure, say N.
 691
 692 config BFIN_GPTIMERS
 693         tristate "Enable Blackfin General Purpose Timers API"
 694         default n
 695         help
 696           Enable support for the General Purpose Timers API.  If you
 697           are unsure, say N.
 698
 699           To compile this driver as a module, choose M here: the module
 700           will be called gptimers.ko.
 701
 702 config BFIN_DMA_5XX
 703         bool "Enable DMA Support"
 704         depends on (BF52x || BF53x || BF561 || BF54x)
 705         default y
 706         help
 707           DMA driver for BF5xx.
 708
 709 choice
 710         prompt "Uncached SDRAM region"
 711         default DMA_UNCACHED_1M
 712         depends on BFIN_DMA_5XX
 713 config DMA_UNCACHED_2M
 714         bool "Enable 2M DMA region"
 715 config DMA_UNCACHED_1M
 716         bool "Enable 1M DMA region"
 717 config DMA_UNCACHED_NONE
 718         bool "Disable DMA region"
 719 endchoice
 720
 721
 722 comment "Cache Support"
 723 config BFIN_ICACHE
 724         bool "Enable ICACHE"
 725 config BFIN_DCACHE
 726         bool "Enable DCACHE"
 727 config BFIN_DCACHE_BANKA
 728         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 729         depends on BFIN_DCACHE && !BF531
 730         default n
 731 config BFIN_ICACHE_LOCK
 732         bool "Enable Instruction Cache Locking"
 733
 734 choice
 735         prompt "Policy"
 736         depends on BFIN_DCACHE
 737         default BFIN_WB
 738 config BFIN_WB
 739         bool "Write back"
 740         help
 741           Write Back Policy:
 742             Cached data will be written back to SDRAM only when needed.
 743             This can give a nice increase in performance, but beware of
 744             broken drivers that do not properly invalidate/flush their
 745             cache.
 746
 747           Write Through Policy:
 748             Cached data will always be written back to SDRAM when the
 749             cache is updated.  This is a completely safe setting, but
 750             performance is worse than Write Back.
 751
 752           If you are unsure of the options and you want to be safe,
 753           then go with Write Through.
 754
 755 config BFIN_WT
 756         bool "Write through"
 757         help
 758           Write Back Policy:
 759             Cached data will be written back to SDRAM only when needed.
 760             This can give a nice increase in performance, but beware of
 761             broken drivers that do not properly invalidate/flush their
 762             cache.
 763
 764           Write Through Policy:
 765             Cached data will always be written back to SDRAM when the
 766             cache is updated.  This is a completely safe setting, but
 767             performance is worse than Write Back.
 768
 769           If you are unsure of the options and you want to be safe,
 770           then go with Write Through.
 771
 772 endchoice
 773
 774 config L1_MAX_PIECE
 775         int "Set the max L1 SRAM pieces"
 776         default 16
 777         help
 778           Set the max memory pieces for the L1 SRAM allocation algorithm.
 779           Min value is 16. Max value is 1024.
 780
 781
 782 config MPU
 783         bool "Enable the memory protection unit (EXPERIMENTAL)"
 784         default n
 785         help
 786           Use the processor's MPU to protect applications from accessing
 787           memory they do not own.  This comes at a performance penalty
 788           and is recommended only for debugging.
 789
 790 comment "Asynchonous Memory Configuration"
 791
 792 menu "EBIU_AMGCTL Global Control"
 793 config C_AMCKEN
 794         bool "Enable CLKOUT"
 795         default y
 796
 797 config C_CDPRIO
 798         bool "DMA has priority over core for ext. accesses"
 799         default n
 800
 801 config C_B0PEN
 802         depends on BF561
 803         bool "Bank 0 16 bit packing enable"
 804         default y
 805
 806 config C_B1PEN
 807         depends on BF561
 808         bool "Bank 1 16 bit packing enable"
 809         default y
 810
 811 config C_B2PEN
 812         depends on BF561
 813         bool "Bank 2 16 bit packing enable"
 814         default y
 815
 816 config C_B3PEN
 817         depends on BF561
 818         bool "Bank 3 16 bit packing enable"
 819         default n
 820
 821 choice
 822         prompt"Enable Asynchonous Memory Banks"
 823         default C_AMBEN_ALL
 824
 825 config C_AMBEN
 826         bool "Disable All Banks"
 827
 828 config C_AMBEN_B0
 829         bool "Enable Bank 0"
 830
 831 config C_AMBEN_B0_B1
 832         bool "Enable Bank 0 & 1"
 833
 834 config C_AMBEN_B0_B1_B2
 835         bool "Enable Bank 0 & 1 & 2"
 836
 837 config C_AMBEN_ALL
 838         bool "Enable All Banks"
 839 endchoice
 840 endmenu
 841
 842 menu "EBIU_AMBCTL Control"
 843 config BANK_0
 844         hex "Bank 0"
 845         default 0x7BB0
 846
 847 config BANK_1
 848         hex "Bank 1"
 849         default 0x7BB0
 850
 851 config BANK_2
 852         hex "Bank 2"
 853         default 0x7BB0
 854
 855 config BANK_3
 856         hex "Bank 3"
 857         default 0x99B3
 858 endmenu
 859
 860 config EBIU_MBSCTLVAL
 861         hex "EBIU Bank Select Control Register"
 862         depends on BF54x
 863         default 0
 864
 865 config EBIU_MODEVAL
 866         hex "Flash Memory Mode Control Register"
 867         depends on BF54x
 868         default 1
 869
 870 config EBIU_FCTLVAL
 871         hex "Flash Memory Bank Control Register"
 872         depends on BF54x
 873         default 6
 874 endmenu
 875
 876 #############################################################################
 877 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
 878
 879 config PCI
 880         bool "PCI support"
 881         help
 882           Support for PCI bus.
 883
 884 source "drivers/pci/Kconfig"
 885
 886 config HOTPLUG
 887         bool "Support for hot-pluggable device"
 888           help
 889           Say Y here if you want to plug devices into your computer while
 890           the system is running, and be able to use them quickly.  In many
 891           cases, the devices can likewise be unplugged at any time too.
 892
 893           One well known example of this is PCMCIA- or PC-cards, credit-card
 894           size devices such as network cards, modems or hard drives which are
 895           plugged into slots found on all modern laptop computers.  Another
 896           example, used on modern desktops as well as laptops, is USB.
 897
 898           Enable HOTPLUG and KMOD, and build a modular kernel.  Get agent
 899           software (at <http://linux-hotplug.sourceforge.net/>) and install it.
 900           Then your kernel will automatically call out to a user mode "policy
 901           agent" (/sbin/hotplug) to load modules and set up software needed
 902           to use devices as you hotplug them.
 903
 904 source "drivers/pcmcia/Kconfig"
 905
 906 source "drivers/pci/hotplug/Kconfig"
 907
 908 endmenu
 909
 910 menu "Executable file formats"
 911
 912 source "fs/Kconfig.binfmt"
 913
 914 endmenu
 915
 916 menu "Power management options"
 917 source "kernel/power/Kconfig"
 918
 919 config ARCH_SUSPEND_POSSIBLE
 920         def_bool y
 921         depends on !SMP
 922
 923 choice
 924         prompt "Default Power Saving Mode"
 925         depends on PM
 926         default PM_BFIN_SLEEP_DEEPER
 927 config  PM_BFIN_SLEEP_DEEPER
 928         bool "Sleep Deeper"
 929         help
 930           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
 931           power dissipation by disabling the clock to the processor core (CCLK).
 932           Furthermore, Standby sets the internal power supply voltage (VDDINT)
 933           to 0.85 V to provide the greatest power savings, while preserving the
 934           processor state.
 935           The PLL and system clock (SCLK) continue to operate at a very low
 936           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
 937           the SDRAM is put into Self Refresh Mode. Typically an external event
 938           such as GPIO interrupt or RTC activity wakes up the processor.
 939           Various Peripherals such as UART, SPORT, PPI may not function as
 940           normal during Sleep Deeper, due to the reduced SCLK frequency.
 941           When in the sleep mode, system DMA access to L1 memory is not supported.
 942
 943 config  PM_BFIN_SLEEP
 944         bool "Sleep"
 945         help
 946           Sleep Mode (High Power Savings) - The sleep mode reduces power
 947           dissipation by disabling the clock to the processor core (CCLK).
 948           The PLL and system clock (SCLK), however, continue to operate in
 949           this mode. Typically an external event or RTC activity will wake
 950           up the processor. When in the sleep mode,
 951           system DMA access to L1 memory is not supported.
 952 endchoice
 953
 954 config PM_WAKEUP_BY_GPIO
 955         bool "Cause Wakeup Event by GPIO"
 956
 957 config PM_WAKEUP_GPIO_NUMBER
 958         int "Wakeup GPIO number"
 959         range 0 47
 960         depends on PM_WAKEUP_BY_GPIO
 961         default 2 if BFIN537_STAMP
 962
 963 choice
 964         prompt "GPIO Polarity"
 965         depends on PM_WAKEUP_BY_GPIO
 966         default PM_WAKEUP_GPIO_POLAR_H
 967 config  PM_WAKEUP_GPIO_POLAR_H
 968         bool "Active High"
 969 config  PM_WAKEUP_GPIO_POLAR_L
 970         bool "Active Low"
 971 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
 972         bool "Falling EDGE"
 973 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
 974         bool "Rising EDGE"
 975 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
 976         bool "Both EDGE"
 977 endchoice
 978
 979 endmenu
 980
 981 if (BF537 || BF533 || BF54x)
 982
 983 menu "CPU Frequency scaling"
 984
 985 source "drivers/cpufreq/Kconfig"
 986
 987 config CPU_FREQ
 988         bool
 989         default n
 990         help
 991           If you want to enable this option, you should select the
 992           DPMC driver from Character Devices.
 993 endmenu
 994
 995 endif
 996
 997 source "net/Kconfig"
 998
 999 source "drivers/Kconfig"
1000
1001 source "fs/Kconfig"
1002
1003 source "arch/blackfin/Kconfig.debug"
1004
1005 source "security/Kconfig"
1006
1007 source "crypto/Kconfig"
1008
1009 source "lib/Kconfig"