arch/blackfin/Kconfig

   1 config SYMBOL_PREFIX
   2         string
   3         default "_"
   4
   5 config MMU
   6         def_bool n
   7
   8 config FPU
   9         def_bool n
  10
  11 config RWSEM_GENERIC_SPINLOCK
  12         def_bool y
  13
  14 config RWSEM_XCHGADD_ALGORITHM
  15         def_bool n
  16
  17 config BLACKFIN
  18         def_bool y
  19         select HAVE_ARCH_KGDB
  20         select HAVE_ARCH_TRACEHOOK
  21         select HAVE_DYNAMIC_FTRACE
  22         select HAVE_FTRACE_MCOUNT_RECORD
  23         select HAVE_FUNCTION_GRAPH_TRACER
  24         select HAVE_FUNCTION_TRACER
  25         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26         select HAVE_IDE
  27         select HAVE_IRQ_WORK
  28         select HAVE_KERNEL_GZIP if RAMKERNEL
  29         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30         select HAVE_KERNEL_LZMA if RAMKERNEL
  31         select HAVE_KERNEL_LZO if RAMKERNEL
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select ARCH_WANT_OPTIONAL_GPIOLIB
  35         select HAVE_GENERIC_HARDIRQS
  36         select GENERIC_ATOMIC64
  37         select GENERIC_IRQ_PROBE
  38         select IRQ_PER_CPU if SMP
  39
  40 config GENERIC_CSUM
  41         def_bool y
  42
  43 config GENERIC_BUG
  44         def_bool y
  45         depends on BUG
  46
  47 config ZONE_DMA
  48         def_bool y
  49
  50 config GENERIC_GPIO
  51         def_bool y
  52
  53 config FORCE_MAX_ZONEORDER
  54         int
  55         default "14"
  56
  57 config GENERIC_CALIBRATE_DELAY
  58         def_bool y
  59
  60 config LOCKDEP_SUPPORT
  61         def_bool y
  62
  63 config STACKTRACE_SUPPORT
  64         def_bool y
  65
  66 config TRACE_IRQFLAGS_SUPPORT
  67         def_bool y
  68
  69 source "init/Kconfig"
  70
  71 source "kernel/Kconfig.preempt"
  72
  73 source "kernel/Kconfig.freezer"
  74
  75 menu "Blackfin Processor Options"
  76
  77 comment "Processor and Board Settings"
  78
  79 choice
  80         prompt "CPU"
  81         default BF533
  82
  83 config BF512
  84         bool "BF512"
  85         help
  86           BF512 Processor Support.
  87
  88 config BF514
  89         bool "BF514"
  90         help
  91           BF514 Processor Support.
  92
  93 config BF516
  94         bool "BF516"
  95         help
  96           BF516 Processor Support.
  97
  98 config BF518
  99         bool "BF518"
 100         help
 101           BF518 Processor Support.
 102
 103 config BF522
 104         bool "BF522"
 105         help
 106           BF522 Processor Support.
 107
 108 config BF523
 109         bool "BF523"
 110         help
 111           BF523 Processor Support.
 112
 113 config BF524
 114         bool "BF524"
 115         help
 116           BF524 Processor Support.
 117
 118 config BF525
 119         bool "BF525"
 120         help
 121           BF525 Processor Support.
 122
 123 config BF526
 124         bool "BF526"
 125         help
 126           BF526 Processor Support.
 127
 128 config BF527
 129         bool "BF527"
 130         help
 131           BF527 Processor Support.
 132
 133 config BF531
 134         bool "BF531"
 135         help
 136           BF531 Processor Support.
 137
 138 config BF532
 139         bool "BF532"
 140         help
 141           BF532 Processor Support.
 142
 143 config BF533
 144         bool "BF533"
 145         help
 146           BF533 Processor Support.
 147
 148 config BF534
 149         bool "BF534"
 150         help
 151           BF534 Processor Support.
 152
 153 config BF536
 154         bool "BF536"
 155         help
 156           BF536 Processor Support.
 157
 158 config BF537
 159         bool "BF537"
 160         help
 161           BF537 Processor Support.
 162
 163 config BF538
 164         bool "BF538"
 165         help
 166           BF538 Processor Support.
 167
 168 config BF539
 169         bool "BF539"
 170         help
 171           BF539 Processor Support.
 172
 173 config BF542_std
 174         bool "BF542"
 175         help
 176           BF542 Processor Support.
 177
 178 config BF542M
 179         bool "BF542m"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF544_std
 184         bool "BF544"
 185         help
 186           BF544 Processor Support.
 187
 188 config BF544M
 189         bool "BF544m"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF547_std
 194         bool "BF547"
 195         help
 196           BF547 Processor Support.
 197
 198 config BF547M
 199         bool "BF547m"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF548_std
 204         bool "BF548"
 205         help
 206           BF548 Processor Support.
 207
 208 config BF548M
 209         bool "BF548m"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF549_std
 214         bool "BF549"
 215         help
 216           BF549 Processor Support.
 217
 218 config BF549M
 219         bool "BF549m"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF561
 224         bool "BF561"
 225         help
 226           BF561 Processor Support.
 227
 228 endchoice
 229
 230 config SMP
 231         depends on BF561
 232         select TICKSOURCE_CORETMR
 233         bool "Symmetric multi-processing support"
 234         ---help---
 235           This enables support for systems with more than one CPU,
 236           like the dual core BF561. If you have a system with only one
 237           CPU, say N. If you have a system with more than one CPU, say Y.
 238
 239           If you don't know what to do here, say N.
 240
 241 config NR_CPUS
 242         int
 243         depends on SMP
 244         default 2 if BF561
 245
 246 config HOTPLUG_CPU
 247         bool "Support for hot-pluggable CPUs"
 248         depends on SMP && HOTPLUG
 249         default y
 250
 251 config HAVE_LEGACY_PER_CPU_AREA
 252         def_bool y
 253         depends on SMP
 254
 255 config BF_REV_MIN
 256         int
 257         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 258         default 2 if (BF537 || BF536 || BF534)
 259         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 260         default 4 if (BF538 || BF539)
 261
 262 config BF_REV_MAX
 263         int
 264         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 265         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 266         default 5 if (BF561 || BF538 || BF539)
 267         default 6 if (BF533 || BF532 || BF531)
 268
 269 choice
 270         prompt "Silicon Rev"
 271         default BF_REV_0_0 if (BF51x || BF52x)
 272         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 273         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 274
 275 config BF_REV_0_0
 276         bool "0.0"
 277         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 278
 279 config BF_REV_0_1
 280         bool "0.1"
 281         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 282
 283 config BF_REV_0_2
 284         bool "0.2"
 285         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 286
 287 config BF_REV_0_3
 288         bool "0.3"
 289         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 290
 291 config BF_REV_0_4
 292         bool "0.4"
 293         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 294
 295 config BF_REV_0_5
 296         bool "0.5"
 297         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 298
 299 config BF_REV_0_6
 300         bool "0.6"
 301         depends on (BF533 || BF532 || BF531)
 302
 303 config BF_REV_ANY
 304         bool "any"
 305
 306 config BF_REV_NONE
 307         bool "none"
 308
 309 endchoice
 310
 311 config BF53x
 312         bool
 313         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 314         default y
 315
 316 config MEM_MT48LC64M4A2FB_7E
 317         bool
 318         depends on (BFIN533_STAMP)
 319         default y
 320
 321 config MEM_MT48LC16M16A2TG_75
 322         bool
 323         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 324                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 325                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 326                 || BFIN527_BLUETECHNIX_CM)
 327         default y
 328
 329 config MEM_MT48LC32M8A2_75
 330         bool
 331         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 332         default y
 333
 334 config MEM_MT48LC8M32B2B5_7
 335         bool
 336         depends on (BFIN561_BLUETECHNIX_CM)
 337         default y
 338
 339 config MEM_MT48LC32M16A2TG_75
 340         bool
 341         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 342         default y
 343
 344 config MEM_MT48H32M16LFCJ_75
 345         bool
 346         depends on (BFIN526_EZBRD)
 347         default y
 348
 349 source "arch/blackfin/mach-bf518/Kconfig"
 350 source "arch/blackfin/mach-bf527/Kconfig"
 351 source "arch/blackfin/mach-bf533/Kconfig"
 352 source "arch/blackfin/mach-bf561/Kconfig"
 353 source "arch/blackfin/mach-bf537/Kconfig"
 354 source "arch/blackfin/mach-bf538/Kconfig"
 355 source "arch/blackfin/mach-bf548/Kconfig"
 356
 357 menu "Board customizations"
 358
 359 config CMDLINE_BOOL
 360         bool "Default bootloader kernel arguments"
 361
 362 config CMDLINE
 363         string "Initial kernel command string"
 364         depends on CMDLINE_BOOL
 365         default "console=ttyBF0,57600"
 366         help
 367           If you don't have a boot loader capable of passing a command line string
 368           to the kernel, you may specify one here. As a minimum, you should specify
 369           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 370
 371 config BOOT_LOAD
 372         hex "Kernel load address for booting"
 373         default "0x1000"
 374         range 0x1000 0x20000000
 375         help
 376           This option allows you to set the load address of the kernel.
 377           This can be useful if you are on a board which has a small amount
 378           of memory or you wish to reserve some memory at the beginning of
 379           the address space.
 380
 381           Note that you need to keep this value above 4k (0x1000) as this
 382           memory region is used to capture NULL pointer references as well
 383           as some core kernel functions.
 384
 385 config ROM_BASE
 386         hex "Kernel ROM Base"
 387         depends on ROMKERNEL
 388         default "0x20040040"
 389         range 0x20000000 0x20400000 if !(BF54x || BF561)
 390         range 0x20000000 0x30000000 if (BF54x || BF561)
 391         help
 392           Make sure your ROM base does not include any file-header
 393           information that is prepended to the kernel.
 394
 395           For example, the bootable U-Boot format (created with
 396           mkimage) has a 64 byte header (0x40).  So while the image
 397           you write to flash might start at say 0x20080000, you have
 398           to add 0x40 to get the kernel's ROM base as it will come
 399           after the header.
 400
 401 comment "Clock/PLL Setup"
 402
 403 config CLKIN_HZ
 404         int "Frequency of the crystal on the board in Hz"
 405         default "10000000" if BFIN532_IP0X
 406         default "11059200" if BFIN533_STAMP
 407         default "24576000" if PNAV10
 408         default "25000000" # most people use this
 409         default "27000000" if BFIN533_EZKIT
 410         default "30000000" if BFIN561_EZKIT
 411         default "24000000" if BFIN527_AD7160EVAL
 412         help
 413           The frequency of CLKIN crystal oscillator on the board in Hz.
 414           Warning: This value should match the crystal on the board. Otherwise,
 415           peripherals won't work properly.
 416
 417 config BFIN_KERNEL_CLOCK
 418         bool "Re-program Clocks while Kernel boots?"
 419         default n
 420         help
 421           This option decides if kernel clocks are re-programed from the
 422           bootloader settings. If the clocks are not set, the SDRAM settings
 423           are also not changed, and the Bootloader does 100% of the hardware
 424           configuration.
 425
 426 config PLL_BYPASS
 427         bool "Bypass PLL"
 428         depends on BFIN_KERNEL_CLOCK
 429         default n
 430
 431 config CLKIN_HALF
 432         bool "Half Clock In"
 433         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 434         default n
 435         help
 436           If this is set the clock will be divided by 2, before it goes to the PLL.
 437
 438 config VCO_MULT
 439         int "VCO Multiplier"
 440         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 441         range 1 64
 442         default "22" if BFIN533_EZKIT
 443         default "45" if BFIN533_STAMP
 444         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 445         default "22" if BFIN533_BLUETECHNIX_CM
 446         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 447         default "20" if BFIN561_EZKIT
 448         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 449         default "25" if BFIN527_AD7160EVAL
 450         help
 451           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 452           PLL Frequency = (Crystal Frequency) * (this setting)
 453
 454 choice
 455         prompt "Core Clock Divider"
 456         depends on BFIN_KERNEL_CLOCK
 457         default CCLK_DIV_1
 458         help
 459           This sets the frequency of the core. It can be 1, 2, 4 or 8
 460           Core Frequency = (PLL frequency) / (this setting)
 461
 462 config CCLK_DIV_1
 463         bool "1"
 464
 465 config CCLK_DIV_2
 466         bool "2"
 467
 468 config CCLK_DIV_4
 469         bool "4"
 470
 471 config CCLK_DIV_8
 472         bool "8"
 473 endchoice
 474
 475 config SCLK_DIV
 476         int "System Clock Divider"
 477         depends on BFIN_KERNEL_CLOCK
 478         range 1 15
 479         default 5
 480         help
 481           This sets the frequency of the system clock (including SDRAM or DDR).
 482           This can be between 1 and 15
 483           System Clock = (PLL frequency) / (this setting)
 484
 485 choice
 486         prompt "DDR SDRAM Chip Type"
 487         depends on BFIN_KERNEL_CLOCK
 488         depends on BF54x
 489         default MEM_MT46V32M16_5B
 490
 491 config MEM_MT46V32M16_6T
 492         bool "MT46V32M16_6T"
 493
 494 config MEM_MT46V32M16_5B
 495         bool "MT46V32M16_5B"
 496 endchoice
 497
 498 choice
 499         prompt "DDR/SDRAM Timing"
 500         depends on BFIN_KERNEL_CLOCK
 501         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 502         help
 503           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 504           The calculated SDRAM timing parameters may not be 100%
 505           accurate - This option is therefore marked experimental.
 506
 507 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 508         bool "Calculate Timings (EXPERIMENTAL)"
 509         depends on EXPERIMENTAL
 510
 511 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 512         bool "Provide accurate Timings based on target SCLK"
 513         help
 514           Please consult the Blackfin Hardware Reference Manuals as well
 515           as the memory device datasheet.
 516           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 517 endchoice
 518
 519 menu "Memory Init Control"
 520         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 521
 522 config MEM_DDRCTL0
 523         depends on BF54x
 524         hex "DDRCTL0"
 525         default 0x0
 526
 527 config MEM_DDRCTL1
 528         depends on BF54x
 529         hex "DDRCTL1"
 530         default 0x0
 531
 532 config MEM_DDRCTL2
 533         depends on BF54x
 534         hex "DDRCTL2"
 535         default 0x0
 536
 537 config MEM_EBIU_DDRQUE
 538         depends on BF54x
 539         hex "DDRQUE"
 540         default 0x0
 541
 542 config MEM_SDRRC
 543         depends on !BF54x
 544         hex "SDRRC"
 545         default 0x0
 546
 547 config MEM_SDGCTL
 548         depends on !BF54x
 549         hex "SDGCTL"
 550         default 0x0
 551 endmenu
 552
 553 #
 554 # Max & Min Speeds for various Chips
 555 #
 556 config MAX_VCO_HZ
 557         int
 558         default 400000000 if BF512
 559         default 400000000 if BF514
 560         default 400000000 if BF516
 561         default 400000000 if BF518
 562         default 400000000 if BF522
 563         default 600000000 if BF523
 564         default 400000000 if BF524
 565         default 600000000 if BF525
 566         default 400000000 if BF526
 567         default 600000000 if BF527
 568         default 400000000 if BF531
 569         default 400000000 if BF532
 570         default 750000000 if BF533
 571         default 500000000 if BF534
 572         default 400000000 if BF536
 573         default 600000000 if BF537
 574         default 533333333 if BF538
 575         default 533333333 if BF539
 576         default 600000000 if BF542
 577         default 533333333 if BF544
 578         default 600000000 if BF547
 579         default 600000000 if BF548
 580         default 533333333 if BF549
 581         default 600000000 if BF561
 582
 583 config MIN_VCO_HZ
 584         int
 585         default 50000000
 586
 587 config MAX_SCLK_HZ
 588         int
 589         default 133333333
 590
 591 config MIN_SCLK_HZ
 592         int
 593         default 27000000
 594
 595 comment "Kernel Timer/Scheduler"
 596
 597 source kernel/Kconfig.hz
 598
 599 config GENERIC_CLOCKEVENTS
 600         bool "Generic clock events"
 601         default y
 602
 603 menu "Clock event device"
 604         depends on GENERIC_CLOCKEVENTS
 605 config TICKSOURCE_GPTMR0
 606         bool "GPTimer0"
 607         depends on !SMP
 608         select BFIN_GPTIMERS
 609
 610 config TICKSOURCE_CORETMR
 611         bool "Core timer"
 612         default y
 613 endmenu
 614
 615 menu "Clock souce"
 616         depends on GENERIC_CLOCKEVENTS
 617 config CYCLES_CLOCKSOURCE
 618         bool "CYCLES"
 619         default y
 620         depends on !BFIN_SCRATCH_REG_CYCLES
 621         depends on !SMP
 622         help
 623           If you say Y here, you will enable support for using the 'cycles'
 624           registers as a clock source.  Doing so means you will be unable to
 625           safely write to the 'cycles' register during runtime.  You will
 626           still be able to read it (such as for performance monitoring), but
 627           writing the registers will most likely crash the kernel.
 628
 629 config GPTMR0_CLOCKSOURCE
 630         bool "GPTimer0"
 631         select BFIN_GPTIMERS
 632         depends on !TICKSOURCE_GPTMR0
 633 endmenu
 634
 635 config ARCH_USES_GETTIMEOFFSET
 636         depends on !GENERIC_CLOCKEVENTS
 637         def_bool y
 638
 639 source kernel/time/Kconfig
 640
 641 comment "Misc"
 642
 643 choice
 644         prompt "Blackfin Exception Scratch Register"
 645         default BFIN_SCRATCH_REG_RETN
 646         help
 647           Select the resource to reserve for the Exception handler:
 648             - RETN: Non-Maskable Interrupt (NMI)
 649             - RETE: Exception Return (JTAG/ICE)
 650             - CYCLES: Performance counter
 651
 652           If you are unsure, please select "RETN".
 653
 654 config BFIN_SCRATCH_REG_RETN
 655         bool "RETN"
 656         help
 657           Use the RETN register in the Blackfin exception handler
 658           as a stack scratch register.  This means you cannot
 659           safely use NMI on the Blackfin while running Linux, but
 660           you can debug the system with a JTAG ICE and use the
 661           CYCLES performance registers.
 662
 663           If you are unsure, please select "RETN".
 664
 665 config BFIN_SCRATCH_REG_RETE
 666         bool "RETE"
 667         help
 668           Use the RETE register in the Blackfin exception handler
 669           as a stack scratch register.  This means you cannot
 670           safely use a JTAG ICE while debugging a Blackfin board,
 671           but you can safely use the CYCLES performance registers
 672           and the NMI.
 673
 674           If you are unsure, please select "RETN".
 675
 676 config BFIN_SCRATCH_REG_CYCLES
 677         bool "CYCLES"
 678         help
 679           Use the CYCLES register in the Blackfin exception handler
 680           as a stack scratch register.  This means you cannot
 681           safely use the CYCLES performance registers on a Blackfin
 682           board at anytime, but you can debug the system with a JTAG
 683           ICE and use the NMI.
 684
 685           If you are unsure, please select "RETN".
 686
 687 endchoice
 688
 689 endmenu
 690
 691
 692 menu "Blackfin Kernel Optimizations"
 693
 694 comment "Memory Optimizations"
 695
 696 config I_ENTRY_L1
 697         bool "Locate interrupt entry code in L1 Memory"
 698         default y
 699         depends on !SMP
 700         help
 701           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 702           into L1 instruction memory. (less latency)
 703
 704 config EXCPT_IRQ_SYSC_L1
 705         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 706         default y
 707         depends on !SMP
 708         help
 709           If enabled, the entire ASM lowlevel exception and interrupt entry code
 710           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 711           (less latency)
 712
 713 config DO_IRQ_L1
 714         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 715         default y
 716         depends on !SMP
 717         help
 718           If enabled, the frequently called do_irq dispatcher function is linked
 719           into L1 instruction memory. (less latency)
 720
 721 config CORE_TIMER_IRQ_L1
 722         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 723         default y
 724         depends on !SMP
 725         help
 726           If enabled, the frequently called timer_interrupt() function is linked
 727           into L1 instruction memory. (less latency)
 728
 729 config IDLE_L1
 730         bool "Locate frequently idle function in L1 Memory"
 731         default y
 732         depends on !SMP
 733         help
 734           If enabled, the frequently called idle function is linked
 735           into L1 instruction memory. (less latency)
 736
 737 config SCHEDULE_L1
 738         bool "Locate kernel schedule function in L1 Memory"
 739         default y
 740         depends on !SMP
 741         help
 742           If enabled, the frequently called kernel schedule is linked
 743           into L1 instruction memory. (less latency)
 744
 745 config ARITHMETIC_OPS_L1
 746         bool "Locate kernel owned arithmetic functions in L1 Memory"
 747         default y
 748         depends on !SMP
 749         help
 750           If enabled, arithmetic functions are linked
 751           into L1 instruction memory. (less latency)
 752
 753 config ACCESS_OK_L1
 754         bool "Locate access_ok function in L1 Memory"
 755         default y
 756         depends on !SMP
 757         help
 758           If enabled, the access_ok function is linked
 759           into L1 instruction memory. (less latency)
 760
 761 config MEMSET_L1
 762         bool "Locate memset function in L1 Memory"
 763         default y
 764         depends on !SMP
 765         help
 766           If enabled, the memset function is linked
 767           into L1 instruction memory. (less latency)
 768
 769 config MEMCPY_L1
 770         bool "Locate memcpy function in L1 Memory"
 771         default y
 772         depends on !SMP
 773         help
 774           If enabled, the memcpy function is linked
 775           into L1 instruction memory. (less latency)
 776
 777 config STRCMP_L1
 778         bool "locate strcmp function in L1 Memory"
 779         default y
 780         depends on !SMP
 781         help
 782           If enabled, the strcmp function is linked
 783           into L1 instruction memory (less latency).
 784
 785 config STRNCMP_L1
 786         bool "locate strncmp function in L1 Memory"
 787         default y
 788         depends on !SMP
 789         help
 790           If enabled, the strncmp function is linked
 791           into L1 instruction memory (less latency).
 792
 793 config STRCPY_L1
 794         bool "locate strcpy function in L1 Memory"
 795         default y
 796         depends on !SMP
 797         help
 798           If enabled, the strcpy function is linked
 799           into L1 instruction memory (less latency).
 800
 801 config STRNCPY_L1
 802         bool "locate strncpy function in L1 Memory"
 803         default y
 804         depends on !SMP
 805         help
 806           If enabled, the strncpy function is linked
 807           into L1 instruction memory (less latency).
 808
 809 config SYS_BFIN_SPINLOCK_L1
 810         bool "Locate sys_bfin_spinlock function in L1 Memory"
 811         default y
 812         depends on !SMP
 813         help
 814           If enabled, sys_bfin_spinlock function is linked
 815           into L1 instruction memory. (less latency)
 816
 817 config IP_CHECKSUM_L1
 818         bool "Locate IP Checksum function in L1 Memory"
 819         default n
 820         depends on !SMP
 821         help
 822           If enabled, the IP Checksum function is linked
 823           into L1 instruction memory. (less latency)
 824
 825 config CACHELINE_ALIGNED_L1
 826         bool "Locate cacheline_aligned data to L1 Data Memory"
 827         default y if !BF54x
 828         default n if BF54x
 829         depends on !SMP && !BF531
 830         help
 831           If enabled, cacheline_aligned data is linked
 832           into L1 data memory. (less latency)
 833
 834 config SYSCALL_TAB_L1
 835         bool "Locate Syscall Table L1 Data Memory"
 836         default n
 837         depends on !SMP && !BF531
 838         help
 839           If enabled, the Syscall LUT is linked
 840           into L1 data memory. (less latency)
 841
 842 config CPLB_SWITCH_TAB_L1
 843         bool "Locate CPLB Switch Tables L1 Data Memory"
 844         default n
 845         depends on !SMP && !BF531
 846         help
 847           If enabled, the CPLB Switch Tables are linked
 848           into L1 data memory. (less latency)
 849
 850 config ICACHE_FLUSH_L1
 851         bool "Locate icache flush funcs in L1 Inst Memory"
 852         default y
 853         help
 854           If enabled, the Blackfin icache flushing functions are linked
 855           into L1 instruction memory.
 856
 857           Note that this might be required to address anomalies, but
 858           these functions are pretty small, so it shouldn't be too bad.
 859           If you are using a processor affected by an anomaly, the build
 860           system will double check for you and prevent it.
 861
 862 config DCACHE_FLUSH_L1
 863         bool "Locate dcache flush funcs in L1 Inst Memory"
 864         default y
 865         depends on !SMP
 866         help
 867           If enabled, the Blackfin dcache flushing functions are linked
 868           into L1 instruction memory.
 869
 870 config APP_STACK_L1
 871         bool "Support locating application stack in L1 Scratch Memory"
 872         default y
 873         depends on !SMP
 874         help
 875           If enabled the application stack can be located in L1
 876           scratch memory (less latency).
 877
 878           Currently only works with FLAT binaries.
 879
 880 config EXCEPTION_L1_SCRATCH
 881         bool "Locate exception stack in L1 Scratch Memory"
 882         default n
 883         depends on !SMP && !APP_STACK_L1
 884         help
 885           Whenever an exception occurs, use the L1 Scratch memory for
 886           stack storage.  You cannot place the stacks of FLAT binaries
 887           in L1 when using this option.
 888
 889           If you don't use L1 Scratch, then you should say Y here.
 890
 891 comment "Speed Optimizations"
 892 config BFIN_INS_LOWOVERHEAD
 893         bool "ins[bwl] low overhead, higher interrupt latency"
 894         default y
 895         depends on !SMP
 896         help
 897           Reads on the Blackfin are speculative. In Blackfin terms, this means
 898           they can be interrupted at any time (even after they have been issued
 899           on to the external bus), and re-issued after the interrupt occurs.
 900           For memory - this is not a big deal, since memory does not change if
 901           it sees a read.
 902
 903           If a FIFO is sitting on the end of the read, it will see two reads,
 904           when the core only sees one since the FIFO receives both the read
 905           which is cancelled (and not delivered to the core) and the one which
 906           is re-issued (which is delivered to the core).
 907
 908           To solve this, interrupts are turned off before reads occur to
 909           I/O space. This option controls which the overhead/latency of
 910           controlling interrupts during this time
 911            "n" turns interrupts off every read
 912                 (higher overhead, but lower interrupt latency)
 913            "y" turns interrupts off every loop
 914                 (low overhead, but longer interrupt latency)
 915
 916           default behavior is to leave this set to on (type "Y"). If you are experiencing
 917           interrupt latency issues, it is safe and OK to turn this off.
 918
 919 endmenu
 920
 921 choice
 922         prompt "Kernel executes from"
 923         help
 924           Choose the memory type that the kernel will be running in.
 925
 926 config RAMKERNEL
 927         bool "RAM"
 928         help
 929           The kernel will be resident in RAM when running.
 930
 931 config ROMKERNEL
 932         bool "ROM"
 933         help
 934           The kernel will be resident in FLASH/ROM when running.
 935
 936 endchoice
 937
 938 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 939 config XIP_KERNEL
 940         bool
 941         default y
 942         depends on ROMKERNEL
 943
 944 source "mm/Kconfig"
 945
 946 config BFIN_GPTIMERS
 947         tristate "Enable Blackfin General Purpose Timers API"
 948         default n
 949         help
 950           Enable support for the General Purpose Timers API.  If you
 951           are unsure, say N.
 952
 953           To compile this driver as a module, choose M here: the module
 954           will be called gptimers.
 955
 956 choice
 957         prompt "Uncached DMA region"
 958         default DMA_UNCACHED_1M
 959 config DMA_UNCACHED_4M
 960         bool "Enable 4M DMA region"
 961 config DMA_UNCACHED_2M
 962         bool "Enable 2M DMA region"
 963 config DMA_UNCACHED_1M
 964         bool "Enable 1M DMA region"
 965 config DMA_UNCACHED_512K
 966         bool "Enable 512K DMA region"
 967 config DMA_UNCACHED_256K
 968         bool "Enable 256K DMA region"
 969 config DMA_UNCACHED_128K
 970         bool "Enable 128K DMA region"
 971 config DMA_UNCACHED_NONE
 972         bool "Disable DMA region"
 973 endchoice
 974
 975
 976 comment "Cache Support"
 977
 978 config BFIN_ICACHE
 979         bool "Enable ICACHE"
 980         default y
 981 config BFIN_EXTMEM_ICACHEABLE
 982         bool "Enable ICACHE for external memory"
 983         depends on BFIN_ICACHE
 984         default y
 985 config BFIN_L2_ICACHEABLE
 986         bool "Enable ICACHE for L2 SRAM"
 987         depends on BFIN_ICACHE
 988         depends on BF54x || BF561
 989         default n
 990
 991 config BFIN_DCACHE
 992         bool "Enable DCACHE"
 993         default y
 994 config BFIN_DCACHE_BANKA
 995         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 996         depends on BFIN_DCACHE && !BF531
 997         default n
 998 config BFIN_EXTMEM_DCACHEABLE
 999         bool "Enable DCACHE for external memory"
1000         depends on BFIN_DCACHE
1001         default y
1002 choice
1003         prompt "External memory DCACHE policy"
1004         depends on BFIN_EXTMEM_DCACHEABLE
1005         default BFIN_EXTMEM_WRITEBACK if !SMP
1006         default BFIN_EXTMEM_WRITETHROUGH if SMP
1007 config BFIN_EXTMEM_WRITEBACK
1008         bool "Write back"
1009         depends on !SMP
1010         help
1011           Write Back Policy:
1012             Cached data will be written back to SDRAM only when needed.
1013             This can give a nice increase in performance, but beware of
1014             broken drivers that do not properly invalidate/flush their
1015             cache.
1016
1017           Write Through Policy:
1018             Cached data will always be written back to SDRAM when the
1019             cache is updated.  This is a completely safe setting, but
1020             performance is worse than Write Back.
1021
1022           If you are unsure of the options and you want to be safe,
1023           then go with Write Through.
1024
1025 config BFIN_EXTMEM_WRITETHROUGH
1026         bool "Write through"
1027         help
1028           Write Back Policy:
1029             Cached data will be written back to SDRAM only when needed.
1030             This can give a nice increase in performance, but beware of
1031             broken drivers that do not properly invalidate/flush their
1032             cache.
1033
1034           Write Through Policy:
1035             Cached data will always be written back to SDRAM when the
1036             cache is updated.  This is a completely safe setting, but
1037             performance is worse than Write Back.
1038
1039           If you are unsure of the options and you want to be safe,
1040           then go with Write Through.
1041
1042 endchoice
1043
1044 config BFIN_L2_DCACHEABLE
1045         bool "Enable DCACHE for L2 SRAM"
1046         depends on BFIN_DCACHE
1047         depends on (BF54x || BF561) && !SMP
1048         default n
1049 choice
1050         prompt "L2 SRAM DCACHE policy"
1051         depends on BFIN_L2_DCACHEABLE
1052         default BFIN_L2_WRITEBACK
1053 config BFIN_L2_WRITEBACK
1054         bool "Write back"
1055
1056 config BFIN_L2_WRITETHROUGH
1057         bool "Write through"
1058 endchoice
1059
1060
1061 comment "Memory Protection Unit"
1062 config MPU
1063         bool "Enable the memory protection unit (EXPERIMENTAL)"
1064         default n
1065         help
1066           Use the processor's MPU to protect applications from accessing
1067           memory they do not own.  This comes at a performance penalty
1068           and is recommended only for debugging.
1069
1070 comment "Asynchronous Memory Configuration"
1071
1072 menu "EBIU_AMGCTL Global Control"
1073 config C_AMCKEN
1074         bool "Enable CLKOUT"
1075         default y
1076
1077 config C_CDPRIO
1078         bool "DMA has priority over core for ext. accesses"
1079         default n
1080
1081 config C_B0PEN
1082         depends on BF561
1083         bool "Bank 0 16 bit packing enable"
1084         default y
1085
1086 config C_B1PEN
1087         depends on BF561
1088         bool "Bank 1 16 bit packing enable"
1089         default y
1090
1091 config C_B2PEN
1092         depends on BF561
1093         bool "Bank 2 16 bit packing enable"
1094         default y
1095
1096 config C_B3PEN
1097         depends on BF561
1098         bool "Bank 3 16 bit packing enable"
1099         default n
1100
1101 choice
1102         prompt "Enable Asynchronous Memory Banks"
1103         default C_AMBEN_ALL
1104
1105 config C_AMBEN
1106         bool "Disable All Banks"
1107
1108 config C_AMBEN_B0
1109         bool "Enable Bank 0"
1110
1111 config C_AMBEN_B0_B1
1112         bool "Enable Bank 0 & 1"
1113
1114 config C_AMBEN_B0_B1_B2
1115         bool "Enable Bank 0 & 1 & 2"
1116
1117 config C_AMBEN_ALL
1118         bool "Enable All Banks"
1119 endchoice
1120 endmenu
1121
1122 menu "EBIU_AMBCTL Control"
1123 config BANK_0
1124         hex "Bank 0 (AMBCTL0.L)"
1125         default 0x7BB0
1126         help
1127           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1128           used to control the Asynchronous Memory Bank 0 settings.
1129
1130 config BANK_1
1131         hex "Bank 1 (AMBCTL0.H)"
1132         default 0x7BB0
1133         default 0x5558 if BF54x
1134         help
1135           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1136           used to control the Asynchronous Memory Bank 1 settings.
1137
1138 config BANK_2
1139         hex "Bank 2 (AMBCTL1.L)"
1140         default 0x7BB0
1141         help
1142           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1143           used to control the Asynchronous Memory Bank 2 settings.
1144
1145 config BANK_3
1146         hex "Bank 3 (AMBCTL1.H)"
1147         default 0x99B3
1148         help
1149           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1150           used to control the Asynchronous Memory Bank 3 settings.
1151
1152 endmenu
1153
1154 config EBIU_MBSCTLVAL
1155         hex "EBIU Bank Select Control Register"
1156         depends on BF54x
1157         default 0
1158
1159 config EBIU_MODEVAL
1160         hex "Flash Memory Mode Control Register"
1161         depends on BF54x
1162         default 1
1163
1164 config EBIU_FCTLVAL
1165         hex "Flash Memory Bank Control Register"
1166         depends on BF54x
1167         default 6
1168 endmenu
1169
1170 #############################################################################
1171 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1172
1173 config PCI
1174         bool "PCI support"
1175         depends on BROKEN
1176         help
1177           Support for PCI bus.
1178
1179 source "drivers/pci/Kconfig"
1180
1181 source "drivers/pcmcia/Kconfig"
1182
1183 source "drivers/pci/hotplug/Kconfig"
1184
1185 endmenu
1186
1187 menu "Executable file formats"
1188
1189 source "fs/Kconfig.binfmt"
1190
1191 endmenu
1192
1193 menu "Power management options"
1194
1195 source "kernel/power/Kconfig"
1196
1197 config ARCH_SUSPEND_POSSIBLE
1198         def_bool y
1199
1200 choice
1201         prompt "Standby Power Saving Mode"
1202         depends on PM
1203         default PM_BFIN_SLEEP_DEEPER
1204 config  PM_BFIN_SLEEP_DEEPER
1205         bool "Sleep Deeper"
1206         help
1207           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1208           power dissipation by disabling the clock to the processor core (CCLK).
1209           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1210           to 0.85 V to provide the greatest power savings, while preserving the
1211           processor state.
1212           The PLL and system clock (SCLK) continue to operate at a very low
1213           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1214           the SDRAM is put into Self Refresh Mode. Typically an external event
1215           such as GPIO interrupt or RTC activity wakes up the processor.
1216           Various Peripherals such as UART, SPORT, PPI may not function as
1217           normal during Sleep Deeper, due to the reduced SCLK frequency.
1218           When in the sleep mode, system DMA access to L1 memory is not supported.
1219
1220           If unsure, select "Sleep Deeper".
1221
1222 config  PM_BFIN_SLEEP
1223         bool "Sleep"
1224         help
1225           Sleep Mode (High Power Savings) - The sleep mode reduces power
1226           dissipation by disabling the clock to the processor core (CCLK).
1227           The PLL and system clock (SCLK), however, continue to operate in
1228           this mode. Typically an external event or RTC activity will wake
1229           up the processor. When in the sleep mode, system DMA access to L1
1230           memory is not supported.
1231
1232           If unsure, select "Sleep Deeper".
1233 endchoice
1234
1235 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1236         depends on PM
1237
1238 config PM_BFIN_WAKE_PH6
1239         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1240         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1241         default n
1242         help
1243           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1244
1245 config PM_BFIN_WAKE_GP
1246         bool "Allow Wake-Up from GPIOs"
1247         depends on PM && BF54x
1248         default n
1249         help
1250           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1251           (all processors, except ADSP-BF549). This option sets
1252           the general-purpose wake-up enable (GPWE) control bit to enable
1253           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1254           On ADSP-BF549 this option enables the the same functionality on the
1255           /MRXON pin also PH7.
1256
1257 endmenu
1258
1259 menu "CPU Frequency scaling"
1260
1261 source "drivers/cpufreq/Kconfig"
1262
1263 config BFIN_CPU_FREQ
1264         bool
1265         depends on CPU_FREQ
1266         select CPU_FREQ_TABLE
1267         default y
1268
1269 config CPU_VOLTAGE
1270         bool "CPU Voltage scaling"
1271         depends on EXPERIMENTAL
1272         depends on CPU_FREQ
1273         default n
1274         help
1275           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1276           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1277           manuals. There is a theoretical risk that during VDDINT transitions
1278           the PLL may unlock.
1279
1280 endmenu
1281
1282 source "net/Kconfig"
1283
1284 source "drivers/Kconfig"
1285
1286 source "drivers/firmware/Kconfig"
1287
1288 source "fs/Kconfig"
1289
1290 source "arch/blackfin/Kconfig.debug"
1291
1292 source "security/Kconfig"
1293
1294 source "crypto/Kconfig"
1295
1296 source "lib/Kconfig"