arch/blackfin/Kconfig

   1 config SYMBOL_PREFIX
   2         string
   3         default "_"
   4
   5 config MMU
   6         def_bool n
   7
   8 config FPU
   9         def_bool n
  10
  11 config RWSEM_GENERIC_SPINLOCK
  12         def_bool y
  13
  14 config RWSEM_XCHGADD_ALGORITHM
  15         def_bool n
  16
  17 config BLACKFIN
  18         def_bool y
  19         select HAVE_ARCH_KGDB
  20         select HAVE_ARCH_TRACEHOOK
  21         select HAVE_DYNAMIC_FTRACE
  22         select HAVE_FTRACE_MCOUNT_RECORD
  23         select HAVE_FUNCTION_GRAPH_TRACER
  24         select HAVE_FUNCTION_TRACER
  25         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26         select HAVE_IDE
  27         select HAVE_IRQ_WORK
  28         select HAVE_KERNEL_GZIP if RAMKERNEL
  29         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30         select HAVE_KERNEL_LZMA if RAMKERNEL
  31         select HAVE_KERNEL_LZO if RAMKERNEL
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select ARCH_HAVE_CUSTOM_GPIO_H
  35         select ARCH_WANT_OPTIONAL_GPIOLIB
  36         select HAVE_UID16
  37         select ARCH_WANT_IPC_PARSE_VERSION
  38         select HAVE_GENERIC_HARDIRQS
  39         select GENERIC_ATOMIC64
  40         select GENERIC_IRQ_PROBE
  41         select IRQ_PER_CPU if SMP
  42         select USE_GENERIC_SMP_HELPERS if SMP
  43         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  44         select GENERIC_SMP_IDLE_THREAD
  45         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  46         select HAVE_MOD_ARCH_SPECIFIC
  47         select MODULES_USE_ELF_RELA
  48         select GENERIC_KERNEL_THREAD
  49         select GENERIC_KERNEL_EXECVE
  50
  51 config GENERIC_CSUM
  52         def_bool y
  53
  54 config GENERIC_BUG
  55         def_bool y
  56         depends on BUG
  57
  58 config ZONE_DMA
  59         def_bool y
  60
  61 config GENERIC_GPIO
  62         def_bool y
  63
  64 config FORCE_MAX_ZONEORDER
  65         int
  66         default "14"
  67
  68 config GENERIC_CALIBRATE_DELAY
  69         def_bool y
  70
  71 config LOCKDEP_SUPPORT
  72         def_bool y
  73
  74 config STACKTRACE_SUPPORT
  75         def_bool y
  76
  77 config TRACE_IRQFLAGS_SUPPORT
  78         def_bool y
  79
  80 source "init/Kconfig"
  81
  82 source "kernel/Kconfig.preempt"
  83
  84 source "kernel/Kconfig.freezer"
  85
  86 menu "Blackfin Processor Options"
  87
  88 comment "Processor and Board Settings"
  89
  90 choice
  91         prompt "CPU"
  92         default BF533
  93
  94 config BF512
  95         bool "BF512"
  96         help
  97           BF512 Processor Support.
  98
  99 config BF514
 100         bool "BF514"
 101         help
 102           BF514 Processor Support.
 103
 104 config BF516
 105         bool "BF516"
 106         help
 107           BF516 Processor Support.
 108
 109 config BF518
 110         bool "BF518"
 111         help
 112           BF518 Processor Support.
 113
 114 config BF522
 115         bool "BF522"
 116         help
 117           BF522 Processor Support.
 118
 119 config BF523
 120         bool "BF523"
 121         help
 122           BF523 Processor Support.
 123
 124 config BF524
 125         bool "BF524"
 126         help
 127           BF524 Processor Support.
 128
 129 config BF525
 130         bool "BF525"
 131         help
 132           BF525 Processor Support.
 133
 134 config BF526
 135         bool "BF526"
 136         help
 137           BF526 Processor Support.
 138
 139 config BF527
 140         bool "BF527"
 141         help
 142           BF527 Processor Support.
 143
 144 config BF531
 145         bool "BF531"
 146         help
 147           BF531 Processor Support.
 148
 149 config BF532
 150         bool "BF532"
 151         help
 152           BF532 Processor Support.
 153
 154 config BF533
 155         bool "BF533"
 156         help
 157           BF533 Processor Support.
 158
 159 config BF534
 160         bool "BF534"
 161         help
 162           BF534 Processor Support.
 163
 164 config BF536
 165         bool "BF536"
 166         help
 167           BF536 Processor Support.
 168
 169 config BF537
 170         bool "BF537"
 171         help
 172           BF537 Processor Support.
 173
 174 config BF538
 175         bool "BF538"
 176         help
 177           BF538 Processor Support.
 178
 179 config BF539
 180         bool "BF539"
 181         help
 182           BF539 Processor Support.
 183
 184 config BF542_std
 185         bool "BF542"
 186         help
 187           BF542 Processor Support.
 188
 189 config BF542M
 190         bool "BF542m"
 191         help
 192           BF542 Processor Support.
 193
 194 config BF544_std
 195         bool "BF544"
 196         help
 197           BF544 Processor Support.
 198
 199 config BF544M
 200         bool "BF544m"
 201         help
 202           BF544 Processor Support.
 203
 204 config BF547_std
 205         bool "BF547"
 206         help
 207           BF547 Processor Support.
 208
 209 config BF547M
 210         bool "BF547m"
 211         help
 212           BF547 Processor Support.
 213
 214 config BF548_std
 215         bool "BF548"
 216         help
 217           BF548 Processor Support.
 218
 219 config BF548M
 220         bool "BF548m"
 221         help
 222           BF548 Processor Support.
 223
 224 config BF549_std
 225         bool "BF549"
 226         help
 227           BF549 Processor Support.
 228
 229 config BF549M
 230         bool "BF549m"
 231         help
 232           BF549 Processor Support.
 233
 234 config BF561
 235         bool "BF561"
 236         help
 237           BF561 Processor Support.
 238
 239 config BF609
 240         bool "BF609"
 241         select CLKDEV_LOOKUP
 242         help
 243           BF609 Processor Support.
 244
 245 endchoice
 246
 247 config SMP
 248         depends on BF561
 249         select TICKSOURCE_CORETMR
 250         bool "Symmetric multi-processing support"
 251         ---help---
 252           This enables support for systems with more than one CPU,
 253           like the dual core BF561. If you have a system with only one
 254           CPU, say N. If you have a system with more than one CPU, say Y.
 255
 256           If you don't know what to do here, say N.
 257
 258 config NR_CPUS
 259         int
 260         depends on SMP
 261         default 2 if BF561
 262
 263 config HOTPLUG_CPU
 264         bool "Support for hot-pluggable CPUs"
 265         depends on SMP && HOTPLUG
 266         default y
 267
 268 config BF_REV_MIN
 269         int
 270         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 271         default 2 if (BF537 || BF536 || BF534)
 272         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 273         default 4 if (BF538 || BF539)
 274
 275 config BF_REV_MAX
 276         int
 277         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 278         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 279         default 5 if (BF561 || BF538 || BF539)
 280         default 6 if (BF533 || BF532 || BF531)
 281
 282 choice
 283         prompt "Silicon Rev"
 284         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 285         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 286         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 287
 288 config BF_REV_0_0
 289         bool "0.0"
 290         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 291
 292 config BF_REV_0_1
 293         bool "0.1"
 294         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 295
 296 config BF_REV_0_2
 297         bool "0.2"
 298         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 299
 300 config BF_REV_0_3
 301         bool "0.3"
 302         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 303
 304 config BF_REV_0_4
 305         bool "0.4"
 306         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 307
 308 config BF_REV_0_5
 309         bool "0.5"
 310         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 311
 312 config BF_REV_0_6
 313         bool "0.6"
 314         depends on (BF533 || BF532 || BF531)
 315
 316 config BF_REV_ANY
 317         bool "any"
 318
 319 config BF_REV_NONE
 320         bool "none"
 321
 322 endchoice
 323
 324 config BF53x
 325         bool
 326         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 327         default y
 328
 329 config MEM_MT48LC64M4A2FB_7E
 330         bool
 331         depends on (BFIN533_STAMP)
 332         default y
 333
 334 config MEM_MT48LC16M16A2TG_75
 335         bool
 336         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 337                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 338                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 339                 || BFIN527_BLUETECHNIX_CM)
 340         default y
 341
 342 config MEM_MT48LC32M8A2_75
 343         bool
 344         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 345         default y
 346
 347 config MEM_MT48LC8M32B2B5_7
 348         bool
 349         depends on (BFIN561_BLUETECHNIX_CM)
 350         default y
 351
 352 config MEM_MT48LC32M16A2TG_75
 353         bool
 354         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 355         default y
 356
 357 config MEM_MT48H32M16LFCJ_75
 358         bool
 359         depends on (BFIN526_EZBRD)
 360         default y
 361
 362 config MEM_MT47H64M16
 363         bool
 364         depends on (BFIN609_EZKIT)
 365         default y
 366
 367 source "arch/blackfin/mach-bf518/Kconfig"
 368 source "arch/blackfin/mach-bf527/Kconfig"
 369 source "arch/blackfin/mach-bf533/Kconfig"
 370 source "arch/blackfin/mach-bf561/Kconfig"
 371 source "arch/blackfin/mach-bf537/Kconfig"
 372 source "arch/blackfin/mach-bf538/Kconfig"
 373 source "arch/blackfin/mach-bf548/Kconfig"
 374 source "arch/blackfin/mach-bf609/Kconfig"
 375
 376 menu "Board customizations"
 377
 378 config CMDLINE_BOOL
 379         bool "Default bootloader kernel arguments"
 380
 381 config CMDLINE
 382         string "Initial kernel command string"
 383         depends on CMDLINE_BOOL
 384         default "console=ttyBF0,57600"
 385         help
 386           If you don't have a boot loader capable of passing a command line string
 387           to the kernel, you may specify one here. As a minimum, you should specify
 388           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 389
 390 config BOOT_LOAD
 391         hex "Kernel load address for booting"
 392         default "0x1000"
 393         range 0x1000 0x20000000
 394         help
 395           This option allows you to set the load address of the kernel.
 396           This can be useful if you are on a board which has a small amount
 397           of memory or you wish to reserve some memory at the beginning of
 398           the address space.
 399
 400           Note that you need to keep this value above 4k (0x1000) as this
 401           memory region is used to capture NULL pointer references as well
 402           as some core kernel functions.
 403
 404 config PHY_RAM_BASE_ADDRESS
 405         hex "Physical RAM Base"
 406         default 0x0
 407         help
 408           set BF609 FPGA physical SRAM base address
 409
 410 config ROM_BASE
 411         hex "Kernel ROM Base"
 412         depends on ROMKERNEL
 413         default "0x20040040"
 414         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 415         range 0x20000000 0x30000000 if (BF54x || BF561)
 416         range 0xB0000000 0xC0000000 if (BF60x)
 417         help
 418           Make sure your ROM base does not include any file-header
 419           information that is prepended to the kernel.
 420
 421           For example, the bootable U-Boot format (created with
 422           mkimage) has a 64 byte header (0x40).  So while the image
 423           you write to flash might start at say 0x20080000, you have
 424           to add 0x40 to get the kernel's ROM base as it will come
 425           after the header.
 426
 427 comment "Clock/PLL Setup"
 428
 429 config CLKIN_HZ
 430         int "Frequency of the crystal on the board in Hz"
 431         default "10000000" if BFIN532_IP0X
 432         default "11059200" if BFIN533_STAMP
 433         default "24576000" if PNAV10
 434         default "25000000" # most people use this
 435         default "27000000" if BFIN533_EZKIT
 436         default "30000000" if BFIN561_EZKIT
 437         default "24000000" if BFIN527_AD7160EVAL
 438         help
 439           The frequency of CLKIN crystal oscillator on the board in Hz.
 440           Warning: This value should match the crystal on the board. Otherwise,
 441           peripherals won't work properly.
 442
 443 config BFIN_KERNEL_CLOCK
 444         bool "Re-program Clocks while Kernel boots?"
 445         default n
 446         help
 447           This option decides if kernel clocks are re-programed from the
 448           bootloader settings. If the clocks are not set, the SDRAM settings
 449           are also not changed, and the Bootloader does 100% of the hardware
 450           configuration.
 451
 452 config PLL_BYPASS
 453         bool "Bypass PLL"
 454         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 455         default n
 456
 457 config CLKIN_HALF
 458         bool "Half Clock In"
 459         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 460         default n
 461         help
 462           If this is set the clock will be divided by 2, before it goes to the PLL.
 463
 464 config VCO_MULT
 465         int "VCO Multiplier"
 466         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 467         range 1 64
 468         default "22" if BFIN533_EZKIT
 469         default "45" if BFIN533_STAMP
 470         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 471         default "22" if BFIN533_BLUETECHNIX_CM
 472         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 473         default "20" if (BFIN561_EZKIT || BF609)
 474         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 475         default "25" if BFIN527_AD7160EVAL
 476         help
 477           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 478           PLL Frequency = (Crystal Frequency) * (this setting)
 479
 480 choice
 481         prompt "Core Clock Divider"
 482         depends on BFIN_KERNEL_CLOCK
 483         default CCLK_DIV_1
 484         help
 485           This sets the frequency of the core. It can be 1, 2, 4 or 8
 486           Core Frequency = (PLL frequency) / (this setting)
 487
 488 config CCLK_DIV_1
 489         bool "1"
 490
 491 config CCLK_DIV_2
 492         bool "2"
 493
 494 config CCLK_DIV_4
 495         bool "4"
 496
 497 config CCLK_DIV_8
 498         bool "8"
 499 endchoice
 500
 501 config SCLK_DIV
 502         int "System Clock Divider"
 503         depends on BFIN_KERNEL_CLOCK
 504         range 1 15
 505         default 4
 506         help
 507           This sets the frequency of the system clock (including SDRAM or DDR) on
 508           !BF60x else it set the clock for system buses and provides the
 509           source from which SCLK0 and SCLK1 are derived.
 510           This can be between 1 and 15
 511           System Clock = (PLL frequency) / (this setting)
 512
 513 config SCLK0_DIV
 514         int "System Clock0 Divider"
 515         depends on BFIN_KERNEL_CLOCK && BF60x
 516         range 1 15
 517         default 1
 518         help
 519           This sets the frequency of the system clock0 for PVP and all other
 520           peripherals not clocked by SCLK1.
 521           This can be between 1 and 15
 522           System Clock0 = (System Clock) / (this setting)
 523
 524 config SCLK1_DIV
 525         int "System Clock1 Divider"
 526         depends on BFIN_KERNEL_CLOCK && BF60x
 527         range 1 15
 528         default 1
 529         help
 530           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 531           This can be between 1 and 15
 532           System Clock1 = (System Clock) / (this setting)
 533
 534 config DCLK_DIV
 535         int "DDR Clock Divider"
 536         depends on BFIN_KERNEL_CLOCK && BF60x
 537         range 1 15
 538         default 2
 539         help
 540           This sets the frequency of the DDR memory.
 541           This can be between 1 and 15
 542           DDR Clock = (PLL frequency) / (this setting)
 543
 544 choice
 545         prompt "DDR SDRAM Chip Type"
 546         depends on BFIN_KERNEL_CLOCK
 547         depends on BF54x
 548         default MEM_MT46V32M16_5B
 549
 550 config MEM_MT46V32M16_6T
 551         bool "MT46V32M16_6T"
 552
 553 config MEM_MT46V32M16_5B
 554         bool "MT46V32M16_5B"
 555 endchoice
 556
 557 choice
 558         prompt "DDR/SDRAM Timing"
 559         depends on BFIN_KERNEL_CLOCK && !BF60x
 560         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 561         help
 562           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 563           The calculated SDRAM timing parameters may not be 100%
 564           accurate - This option is therefore marked experimental.
 565
 566 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 567         bool "Calculate Timings (EXPERIMENTAL)"
 568         depends on EXPERIMENTAL
 569
 570 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 571         bool "Provide accurate Timings based on target SCLK"
 572         help
 573           Please consult the Blackfin Hardware Reference Manuals as well
 574           as the memory device datasheet.
 575           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 576 endchoice
 577
 578 menu "Memory Init Control"
 579         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 580
 581 config MEM_DDRCTL0
 582         depends on BF54x
 583         hex "DDRCTL0"
 584         default 0x0
 585
 586 config MEM_DDRCTL1
 587         depends on BF54x
 588         hex "DDRCTL1"
 589         default 0x0
 590
 591 config MEM_DDRCTL2
 592         depends on BF54x
 593         hex "DDRCTL2"
 594         default 0x0
 595
 596 config MEM_EBIU_DDRQUE
 597         depends on BF54x
 598         hex "DDRQUE"
 599         default 0x0
 600
 601 config MEM_SDRRC
 602         depends on !BF54x
 603         hex "SDRRC"
 604         default 0x0
 605
 606 config MEM_SDGCTL
 607         depends on !BF54x
 608         hex "SDGCTL"
 609         default 0x0
 610 endmenu
 611
 612 #
 613 # Max & Min Speeds for various Chips
 614 #
 615 config MAX_VCO_HZ
 616         int
 617         default 400000000 if BF512
 618         default 400000000 if BF514
 619         default 400000000 if BF516
 620         default 400000000 if BF518
 621         default 400000000 if BF522
 622         default 600000000 if BF523
 623         default 400000000 if BF524
 624         default 600000000 if BF525
 625         default 400000000 if BF526
 626         default 600000000 if BF527
 627         default 400000000 if BF531
 628         default 400000000 if BF532
 629         default 750000000 if BF533
 630         default 500000000 if BF534
 631         default 400000000 if BF536
 632         default 600000000 if BF537
 633         default 533333333 if BF538
 634         default 533333333 if BF539
 635         default 600000000 if BF542
 636         default 533333333 if BF544
 637         default 600000000 if BF547
 638         default 600000000 if BF548
 639         default 533333333 if BF549
 640         default 600000000 if BF561
 641         default 800000000 if BF609
 642
 643 config MIN_VCO_HZ
 644         int
 645         default 50000000
 646
 647 config MAX_SCLK_HZ
 648         int
 649         default 200000000 if BF609
 650         default 133333333
 651
 652 config MIN_SCLK_HZ
 653         int
 654         default 27000000
 655
 656 comment "Kernel Timer/Scheduler"
 657
 658 source kernel/Kconfig.hz
 659
 660 config SET_GENERIC_CLOCKEVENTS
 661         bool "Generic clock events"
 662         default y
 663         select GENERIC_CLOCKEVENTS
 664
 665 menu "Clock event device"
 666         depends on GENERIC_CLOCKEVENTS
 667 config TICKSOURCE_GPTMR0
 668         bool "GPTimer0"
 669         depends on !SMP
 670         select BFIN_GPTIMERS
 671
 672 config TICKSOURCE_CORETMR
 673         bool "Core timer"
 674         default y
 675 endmenu
 676
 677 menu "Clock souce"
 678         depends on GENERIC_CLOCKEVENTS
 679 config CYCLES_CLOCKSOURCE
 680         bool "CYCLES"
 681         default y
 682         depends on !BFIN_SCRATCH_REG_CYCLES
 683         depends on !SMP
 684         help
 685           If you say Y here, you will enable support for using the 'cycles'
 686           registers as a clock source.  Doing so means you will be unable to
 687           safely write to the 'cycles' register during runtime.  You will
 688           still be able to read it (such as for performance monitoring), but
 689           writing the registers will most likely crash the kernel.
 690
 691 config GPTMR0_CLOCKSOURCE
 692         bool "GPTimer0"
 693         select BFIN_GPTIMERS
 694         depends on !TICKSOURCE_GPTMR0
 695 endmenu
 696
 697 comment "Misc"
 698
 699 choice
 700         prompt "Blackfin Exception Scratch Register"
 701         default BFIN_SCRATCH_REG_RETN
 702         help
 703           Select the resource to reserve for the Exception handler:
 704             - RETN: Non-Maskable Interrupt (NMI)
 705             - RETE: Exception Return (JTAG/ICE)
 706             - CYCLES: Performance counter
 707
 708           If you are unsure, please select "RETN".
 709
 710 config BFIN_SCRATCH_REG_RETN
 711         bool "RETN"
 712         help
 713           Use the RETN register in the Blackfin exception handler
 714           as a stack scratch register.  This means you cannot
 715           safely use NMI on the Blackfin while running Linux, but
 716           you can debug the system with a JTAG ICE and use the
 717           CYCLES performance registers.
 718
 719           If you are unsure, please select "RETN".
 720
 721 config BFIN_SCRATCH_REG_RETE
 722         bool "RETE"
 723         help
 724           Use the RETE register in the Blackfin exception handler
 725           as a stack scratch register.  This means you cannot
 726           safely use a JTAG ICE while debugging a Blackfin board,
 727           but you can safely use the CYCLES performance registers
 728           and the NMI.
 729
 730           If you are unsure, please select "RETN".
 731
 732 config BFIN_SCRATCH_REG_CYCLES
 733         bool "CYCLES"
 734         help
 735           Use the CYCLES register in the Blackfin exception handler
 736           as a stack scratch register.  This means you cannot
 737           safely use the CYCLES performance registers on a Blackfin
 738           board at anytime, but you can debug the system with a JTAG
 739           ICE and use the NMI.
 740
 741           If you are unsure, please select "RETN".
 742
 743 endchoice
 744
 745 endmenu
 746
 747
 748 menu "Blackfin Kernel Optimizations"
 749
 750 comment "Memory Optimizations"
 751
 752 config I_ENTRY_L1
 753         bool "Locate interrupt entry code in L1 Memory"
 754         default y
 755         depends on !SMP
 756         help
 757           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 758           into L1 instruction memory. (less latency)
 759
 760 config EXCPT_IRQ_SYSC_L1
 761         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 762         default y
 763         depends on !SMP
 764         help
 765           If enabled, the entire ASM lowlevel exception and interrupt entry code
 766           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 767           (less latency)
 768
 769 config DO_IRQ_L1
 770         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 771         default y
 772         depends on !SMP
 773         help
 774           If enabled, the frequently called do_irq dispatcher function is linked
 775           into L1 instruction memory. (less latency)
 776
 777 config CORE_TIMER_IRQ_L1
 778         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 779         default y
 780         depends on !SMP
 781         help
 782           If enabled, the frequently called timer_interrupt() function is linked
 783           into L1 instruction memory. (less latency)
 784
 785 config IDLE_L1
 786         bool "Locate frequently idle function in L1 Memory"
 787         default y
 788         depends on !SMP
 789         help
 790           If enabled, the frequently called idle function is linked
 791           into L1 instruction memory. (less latency)
 792
 793 config SCHEDULE_L1
 794         bool "Locate kernel schedule function in L1 Memory"
 795         default y
 796         depends on !SMP
 797         help
 798           If enabled, the frequently called kernel schedule is linked
 799           into L1 instruction memory. (less latency)
 800
 801 config ARITHMETIC_OPS_L1
 802         bool "Locate kernel owned arithmetic functions in L1 Memory"
 803         default y
 804         depends on !SMP
 805         help
 806           If enabled, arithmetic functions are linked
 807           into L1 instruction memory. (less latency)
 808
 809 config ACCESS_OK_L1
 810         bool "Locate access_ok function in L1 Memory"
 811         default y
 812         depends on !SMP
 813         help
 814           If enabled, the access_ok function is linked
 815           into L1 instruction memory. (less latency)
 816
 817 config MEMSET_L1
 818         bool "Locate memset function in L1 Memory"
 819         default y
 820         depends on !SMP
 821         help
 822           If enabled, the memset function is linked
 823           into L1 instruction memory. (less latency)
 824
 825 config MEMCPY_L1
 826         bool "Locate memcpy function in L1 Memory"
 827         default y
 828         depends on !SMP
 829         help
 830           If enabled, the memcpy function is linked
 831           into L1 instruction memory. (less latency)
 832
 833 config STRCMP_L1
 834         bool "locate strcmp function in L1 Memory"
 835         default y
 836         depends on !SMP
 837         help
 838           If enabled, the strcmp function is linked
 839           into L1 instruction memory (less latency).
 840
 841 config STRNCMP_L1
 842         bool "locate strncmp function in L1 Memory"
 843         default y
 844         depends on !SMP
 845         help
 846           If enabled, the strncmp function is linked
 847           into L1 instruction memory (less latency).
 848
 849 config STRCPY_L1
 850         bool "locate strcpy function in L1 Memory"
 851         default y
 852         depends on !SMP
 853         help
 854           If enabled, the strcpy function is linked
 855           into L1 instruction memory (less latency).
 856
 857 config STRNCPY_L1
 858         bool "locate strncpy function in L1 Memory"
 859         default y
 860         depends on !SMP
 861         help
 862           If enabled, the strncpy function is linked
 863           into L1 instruction memory (less latency).
 864
 865 config SYS_BFIN_SPINLOCK_L1
 866         bool "Locate sys_bfin_spinlock function in L1 Memory"
 867         default y
 868         depends on !SMP
 869         help
 870           If enabled, sys_bfin_spinlock function is linked
 871           into L1 instruction memory. (less latency)
 872
 873 config IP_CHECKSUM_L1
 874         bool "Locate IP Checksum function in L1 Memory"
 875         default n
 876         depends on !SMP
 877         help
 878           If enabled, the IP Checksum function is linked
 879           into L1 instruction memory. (less latency)
 880
 881 config CACHELINE_ALIGNED_L1
 882         bool "Locate cacheline_aligned data to L1 Data Memory"
 883         default y if !BF54x
 884         default n if BF54x
 885         depends on !SMP && !BF531 && !CRC32
 886         help
 887           If enabled, cacheline_aligned data is linked
 888           into L1 data memory. (less latency)
 889
 890 config SYSCALL_TAB_L1
 891         bool "Locate Syscall Table L1 Data Memory"
 892         default n
 893         depends on !SMP && !BF531
 894         help
 895           If enabled, the Syscall LUT is linked
 896           into L1 data memory. (less latency)
 897
 898 config CPLB_SWITCH_TAB_L1
 899         bool "Locate CPLB Switch Tables L1 Data Memory"
 900         default n
 901         depends on !SMP && !BF531
 902         help
 903           If enabled, the CPLB Switch Tables are linked
 904           into L1 data memory. (less latency)
 905
 906 config ICACHE_FLUSH_L1
 907         bool "Locate icache flush funcs in L1 Inst Memory"
 908         default y
 909         help
 910           If enabled, the Blackfin icache flushing functions are linked
 911           into L1 instruction memory.
 912
 913           Note that this might be required to address anomalies, but
 914           these functions are pretty small, so it shouldn't be too bad.
 915           If you are using a processor affected by an anomaly, the build
 916           system will double check for you and prevent it.
 917
 918 config DCACHE_FLUSH_L1
 919         bool "Locate dcache flush funcs in L1 Inst Memory"
 920         default y
 921         depends on !SMP
 922         help
 923           If enabled, the Blackfin dcache flushing functions are linked
 924           into L1 instruction memory.
 925
 926 config APP_STACK_L1
 927         bool "Support locating application stack in L1 Scratch Memory"
 928         default y
 929         depends on !SMP
 930         help
 931           If enabled the application stack can be located in L1
 932           scratch memory (less latency).
 933
 934           Currently only works with FLAT binaries.
 935
 936 config EXCEPTION_L1_SCRATCH
 937         bool "Locate exception stack in L1 Scratch Memory"
 938         default n
 939         depends on !SMP && !APP_STACK_L1
 940         help
 941           Whenever an exception occurs, use the L1 Scratch memory for
 942           stack storage.  You cannot place the stacks of FLAT binaries
 943           in L1 when using this option.
 944
 945           If you don't use L1 Scratch, then you should say Y here.
 946
 947 comment "Speed Optimizations"
 948 config BFIN_INS_LOWOVERHEAD
 949         bool "ins[bwl] low overhead, higher interrupt latency"
 950         default y
 951         depends on !SMP
 952         help
 953           Reads on the Blackfin are speculative. In Blackfin terms, this means
 954           they can be interrupted at any time (even after they have been issued
 955           on to the external bus), and re-issued after the interrupt occurs.
 956           For memory - this is not a big deal, since memory does not change if
 957           it sees a read.
 958
 959           If a FIFO is sitting on the end of the read, it will see two reads,
 960           when the core only sees one since the FIFO receives both the read
 961           which is cancelled (and not delivered to the core) and the one which
 962           is re-issued (which is delivered to the core).
 963
 964           To solve this, interrupts are turned off before reads occur to
 965           I/O space. This option controls which the overhead/latency of
 966           controlling interrupts during this time
 967            "n" turns interrupts off every read
 968                 (higher overhead, but lower interrupt latency)
 969            "y" turns interrupts off every loop
 970                 (low overhead, but longer interrupt latency)
 971
 972           default behavior is to leave this set to on (type "Y"). If you are experiencing
 973           interrupt latency issues, it is safe and OK to turn this off.
 974
 975 endmenu
 976
 977 choice
 978         prompt "Kernel executes from"
 979         help
 980           Choose the memory type that the kernel will be running in.
 981
 982 config RAMKERNEL
 983         bool "RAM"
 984         help
 985           The kernel will be resident in RAM when running.
 986
 987 config ROMKERNEL
 988         bool "ROM"
 989         help
 990           The kernel will be resident in FLASH/ROM when running.
 991
 992 endchoice
 993
 994 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 995 config XIP_KERNEL
 996         bool
 997         default y
 998         depends on ROMKERNEL
 999
1000 source "mm/Kconfig"
1001
1002 config BFIN_GPTIMERS
1003         tristate "Enable Blackfin General Purpose Timers API"
1004         default n
1005         help
1006           Enable support for the General Purpose Timers API.  If you
1007           are unsure, say N.
1008
1009           To compile this driver as a module, choose M here: the module
1010           will be called gptimers.
1011
1012 choice
1013         prompt "Uncached DMA region"
1014         default DMA_UNCACHED_1M
1015 config DMA_UNCACHED_32M
1016         bool "Enable 32M DMA region"
1017 config DMA_UNCACHED_16M
1018         bool "Enable 16M DMA region"
1019 config DMA_UNCACHED_8M
1020         bool "Enable 8M DMA region"
1021 config DMA_UNCACHED_4M
1022         bool "Enable 4M DMA region"
1023 config DMA_UNCACHED_2M
1024         bool "Enable 2M DMA region"
1025 config DMA_UNCACHED_1M
1026         bool "Enable 1M DMA region"
1027 config DMA_UNCACHED_512K
1028         bool "Enable 512K DMA region"
1029 config DMA_UNCACHED_256K
1030         bool "Enable 256K DMA region"
1031 config DMA_UNCACHED_128K
1032         bool "Enable 128K DMA region"
1033 config DMA_UNCACHED_NONE
1034         bool "Disable DMA region"
1035 endchoice
1036
1037
1038 comment "Cache Support"
1039
1040 config BFIN_ICACHE
1041         bool "Enable ICACHE"
1042         default y
1043 config BFIN_EXTMEM_ICACHEABLE
1044         bool "Enable ICACHE for external memory"
1045         depends on BFIN_ICACHE
1046         default y
1047 config BFIN_L2_ICACHEABLE
1048         bool "Enable ICACHE for L2 SRAM"
1049         depends on BFIN_ICACHE
1050         depends on (BF54x || BF561 || BF60x) && !SMP
1051         default n
1052
1053 config BFIN_DCACHE
1054         bool "Enable DCACHE"
1055         default y
1056 config BFIN_DCACHE_BANKA
1057         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1058         depends on BFIN_DCACHE && !BF531
1059         default n
1060 config BFIN_EXTMEM_DCACHEABLE
1061         bool "Enable DCACHE for external memory"
1062         depends on BFIN_DCACHE
1063         default y
1064 choice
1065         prompt "External memory DCACHE policy"
1066         depends on BFIN_EXTMEM_DCACHEABLE
1067         default BFIN_EXTMEM_WRITEBACK if !SMP
1068         default BFIN_EXTMEM_WRITETHROUGH if SMP
1069 config BFIN_EXTMEM_WRITEBACK
1070         bool "Write back"
1071         depends on !SMP
1072         help
1073           Write Back Policy:
1074             Cached data will be written back to SDRAM only when needed.
1075             This can give a nice increase in performance, but beware of
1076             broken drivers that do not properly invalidate/flush their
1077             cache.
1078
1079           Write Through Policy:
1080             Cached data will always be written back to SDRAM when the
1081             cache is updated.  This is a completely safe setting, but
1082             performance is worse than Write Back.
1083
1084           If you are unsure of the options and you want to be safe,
1085           then go with Write Through.
1086
1087 config BFIN_EXTMEM_WRITETHROUGH
1088         bool "Write through"
1089         help
1090           Write Back Policy:
1091             Cached data will be written back to SDRAM only when needed.
1092             This can give a nice increase in performance, but beware of
1093             broken drivers that do not properly invalidate/flush their
1094             cache.
1095
1096           Write Through Policy:
1097             Cached data will always be written back to SDRAM when the
1098             cache is updated.  This is a completely safe setting, but
1099             performance is worse than Write Back.
1100
1101           If you are unsure of the options and you want to be safe,
1102           then go with Write Through.
1103
1104 endchoice
1105
1106 config BFIN_L2_DCACHEABLE
1107         bool "Enable DCACHE for L2 SRAM"
1108         depends on BFIN_DCACHE
1109         depends on (BF54x || BF561 || BF60x) && !SMP
1110         default n
1111 choice
1112         prompt "L2 SRAM DCACHE policy"
1113         depends on BFIN_L2_DCACHEABLE
1114         default BFIN_L2_WRITEBACK
1115 config BFIN_L2_WRITEBACK
1116         bool "Write back"
1117
1118 config BFIN_L2_WRITETHROUGH
1119         bool "Write through"
1120 endchoice
1121
1122
1123 comment "Memory Protection Unit"
1124 config MPU
1125         bool "Enable the memory protection unit (EXPERIMENTAL)"
1126         default n
1127         help
1128           Use the processor's MPU to protect applications from accessing
1129           memory they do not own.  This comes at a performance penalty
1130           and is recommended only for debugging.
1131
1132 comment "Asynchronous Memory Configuration"
1133
1134 menu "EBIU_AMGCTL Global Control"
1135         depends on !BF60x
1136 config C_AMCKEN
1137         bool "Enable CLKOUT"
1138         default y
1139
1140 config C_CDPRIO
1141         bool "DMA has priority over core for ext. accesses"
1142         default n
1143
1144 config C_B0PEN
1145         depends on BF561
1146         bool "Bank 0 16 bit packing enable"
1147         default y
1148
1149 config C_B1PEN
1150         depends on BF561
1151         bool "Bank 1 16 bit packing enable"
1152         default y
1153
1154 config C_B2PEN
1155         depends on BF561
1156         bool "Bank 2 16 bit packing enable"
1157         default y
1158
1159 config C_B3PEN
1160         depends on BF561
1161         bool "Bank 3 16 bit packing enable"
1162         default n
1163
1164 choice
1165         prompt "Enable Asynchronous Memory Banks"
1166         default C_AMBEN_ALL
1167
1168 config C_AMBEN
1169         bool "Disable All Banks"
1170
1171 config C_AMBEN_B0
1172         bool "Enable Bank 0"
1173
1174 config C_AMBEN_B0_B1
1175         bool "Enable Bank 0 & 1"
1176
1177 config C_AMBEN_B0_B1_B2
1178         bool "Enable Bank 0 & 1 & 2"
1179
1180 config C_AMBEN_ALL
1181         bool "Enable All Banks"
1182 endchoice
1183 endmenu
1184
1185 menu "EBIU_AMBCTL Control"
1186         depends on !BF60x
1187 config BANK_0
1188         hex "Bank 0 (AMBCTL0.L)"
1189         default 0x7BB0
1190         help
1191           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1192           used to control the Asynchronous Memory Bank 0 settings.
1193
1194 config BANK_1
1195         hex "Bank 1 (AMBCTL0.H)"
1196         default 0x7BB0
1197         default 0x5558 if BF54x
1198         help
1199           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1200           used to control the Asynchronous Memory Bank 1 settings.
1201
1202 config BANK_2
1203         hex "Bank 2 (AMBCTL1.L)"
1204         default 0x7BB0
1205         help
1206           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1207           used to control the Asynchronous Memory Bank 2 settings.
1208
1209 config BANK_3
1210         hex "Bank 3 (AMBCTL1.H)"
1211         default 0x99B3
1212         help
1213           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1214           used to control the Asynchronous Memory Bank 3 settings.
1215
1216 endmenu
1217
1218 config EBIU_MBSCTLVAL
1219         hex "EBIU Bank Select Control Register"
1220         depends on BF54x
1221         default 0
1222
1223 config EBIU_MODEVAL
1224         hex "Flash Memory Mode Control Register"
1225         depends on BF54x
1226         default 1
1227
1228 config EBIU_FCTLVAL
1229         hex "Flash Memory Bank Control Register"
1230         depends on BF54x
1231         default 6
1232 endmenu
1233
1234 #############################################################################
1235 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1236
1237 config PCI
1238         bool "PCI support"
1239         depends on BROKEN
1240         help
1241           Support for PCI bus.
1242
1243 source "drivers/pci/Kconfig"
1244
1245 source "drivers/pcmcia/Kconfig"
1246
1247 source "drivers/pci/hotplug/Kconfig"
1248
1249 endmenu
1250
1251 menu "Executable file formats"
1252
1253 source "fs/Kconfig.binfmt"
1254
1255 endmenu
1256
1257 menu "Power management options"
1258
1259 source "kernel/power/Kconfig"
1260
1261 config ARCH_SUSPEND_POSSIBLE
1262         def_bool y
1263
1264 choice
1265         prompt "Standby Power Saving Mode"
1266         depends on PM && !BF60x
1267         default PM_BFIN_SLEEP_DEEPER
1268 config  PM_BFIN_SLEEP_DEEPER
1269         bool "Sleep Deeper"
1270         help
1271           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1272           power dissipation by disabling the clock to the processor core (CCLK).
1273           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1274           to 0.85 V to provide the greatest power savings, while preserving the
1275           processor state.
1276           The PLL and system clock (SCLK) continue to operate at a very low
1277           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1278           the SDRAM is put into Self Refresh Mode. Typically an external event
1279           such as GPIO interrupt or RTC activity wakes up the processor.
1280           Various Peripherals such as UART, SPORT, PPI may not function as
1281           normal during Sleep Deeper, due to the reduced SCLK frequency.
1282           When in the sleep mode, system DMA access to L1 memory is not supported.
1283
1284           If unsure, select "Sleep Deeper".
1285
1286 config  PM_BFIN_SLEEP
1287         bool "Sleep"
1288         help
1289           Sleep Mode (High Power Savings) - The sleep mode reduces power
1290           dissipation by disabling the clock to the processor core (CCLK).
1291           The PLL and system clock (SCLK), however, continue to operate in
1292           this mode. Typically an external event or RTC activity will wake
1293           up the processor. When in the sleep mode, system DMA access to L1
1294           memory is not supported.
1295
1296           If unsure, select "Sleep Deeper".
1297 endchoice
1298
1299 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1300         depends on PM
1301
1302 config PM_BFIN_WAKE_PH6
1303         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1304         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1305         default n
1306         help
1307           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1308
1309 config PM_BFIN_WAKE_GP
1310         bool "Allow Wake-Up from GPIOs"
1311         depends on PM && BF54x
1312         default n
1313         help
1314           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1315           (all processors, except ADSP-BF549). This option sets
1316           the general-purpose wake-up enable (GPWE) control bit to enable
1317           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1318           On ADSP-BF549 this option enables the same functionality on the
1319           /MRXON pin also PH7.
1320
1321 config PM_BFIN_WAKE_PA15
1322         bool "Allow Wake-Up from PA15"
1323         depends on PM && BF60x
1324         default n
1325         help
1326           Enable PA15 Wake-Up
1327
1328 config PM_BFIN_WAKE_PA15_POL
1329         int "Wake-up priority"
1330         depends on PM_BFIN_WAKE_PA15
1331         default 0
1332         help
1333           Wake-Up priority 0(low) 1(high)
1334
1335 config PM_BFIN_WAKE_PB15
1336         bool "Allow Wake-Up from PB15"
1337         depends on PM && BF60x
1338         default n
1339         help
1340           Enable PB15 Wake-Up
1341
1342 config PM_BFIN_WAKE_PB15_POL
1343         int "Wake-up priority"
1344         depends on PM_BFIN_WAKE_PB15
1345         default 0
1346         help
1347           Wake-Up priority 0(low) 1(high)
1348
1349 config PM_BFIN_WAKE_PC15
1350         bool "Allow Wake-Up from PC15"
1351         depends on PM && BF60x
1352         default n
1353         help
1354           Enable PC15 Wake-Up
1355
1356 config PM_BFIN_WAKE_PC15_POL
1357         int "Wake-up priority"
1358         depends on PM_BFIN_WAKE_PC15
1359         default 0
1360         help
1361           Wake-Up priority 0(low) 1(high)
1362
1363 config PM_BFIN_WAKE_PD06
1364         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1365         depends on PM && BF60x
1366         default n
1367         help
1368           Enable PD06(ETH0_PHYINT) Wake-up
1369
1370 config PM_BFIN_WAKE_PD06_POL
1371         int "Wake-up priority"
1372         depends on PM_BFIN_WAKE_PD06
1373         default 0
1374         help
1375           Wake-Up priority 0(low) 1(high)
1376
1377 config PM_BFIN_WAKE_PE12
1378         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1379         depends on PM && BF60x
1380         default n
1381         help
1382           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1383
1384 config PM_BFIN_WAKE_PE12_POL
1385         int "Wake-up priority"
1386         depends on PM_BFIN_WAKE_PE12
1387         default 0
1388         help
1389           Wake-Up priority 0(low) 1(high)
1390
1391 config PM_BFIN_WAKE_PG04
1392         bool "Allow Wake-Up from PG04(CAN0_RX)"
1393         depends on PM && BF60x
1394         default n
1395         help
1396           Enable PG04(CAN0_RX) Wake-up
1397
1398 config PM_BFIN_WAKE_PG04_POL
1399         int "Wake-up priority"
1400         depends on PM_BFIN_WAKE_PG04
1401         default 0
1402         help
1403           Wake-Up priority 0(low) 1(high)
1404
1405 config PM_BFIN_WAKE_PG13
1406         bool "Allow Wake-Up from PG13"
1407         depends on PM && BF60x
1408         default n
1409         help
1410           Enable PG13 Wake-Up
1411
1412 config PM_BFIN_WAKE_PG13_POL
1413         int "Wake-up priority"
1414         depends on PM_BFIN_WAKE_PG13
1415         default 0
1416         help
1417           Wake-Up priority 0(low) 1(high)
1418
1419 config PM_BFIN_WAKE_USB
1420         bool "Allow Wake-Up from (USB)"
1421         depends on PM && BF60x
1422         default n
1423         help
1424           Enable (USB) Wake-up
1425
1426 config PM_BFIN_WAKE_USB_POL
1427         int "Wake-up priority"
1428         depends on PM_BFIN_WAKE_USB
1429         default 0
1430         help
1431           Wake-Up priority 0(low) 1(high)
1432
1433 endmenu
1434
1435 menu "CPU Frequency scaling"
1436
1437 source "drivers/cpufreq/Kconfig"
1438
1439 config BFIN_CPU_FREQ
1440         bool
1441         depends on CPU_FREQ
1442         select CPU_FREQ_TABLE
1443         default y
1444
1445 config CPU_VOLTAGE
1446         bool "CPU Voltage scaling"
1447         depends on EXPERIMENTAL
1448         depends on CPU_FREQ
1449         default n
1450         help
1451           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1452           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1453           manuals. There is a theoretical risk that during VDDINT transitions
1454           the PLL may unlock.
1455
1456 endmenu
1457
1458 source "net/Kconfig"
1459
1460 source "drivers/Kconfig"
1461
1462 source "drivers/firmware/Kconfig"
1463
1464 source "fs/Kconfig"
1465
1466 source "arch/blackfin/Kconfig.debug"
1467
1468 source "security/Kconfig"
1469
1470 source "crypto/Kconfig"
1471
1472 source "lib/Kconfig"