arch/blackfin/include/asm/bfin5xx_spi.h

   1 /*
   2  * Blackfin On-Chip SPI Driver
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef _SPI_CHANNEL_H_
  10 #define _SPI_CHANNEL_H_
  11
  12 #define MIN_SPI_BAUD_VAL        2
  13
  14 #define SPI_READ              0
  15 #define SPI_WRITE             1
  16
  17 #define SPI_CTRL_OFF            0x0
  18 #define SPI_FLAG_OFF            0x4
  19 #define SPI_STAT_OFF            0x8
  20 #define SPI_TXBUFF_OFF          0xc
  21 #define SPI_RXBUFF_OFF          0x10
  22 #define SPI_BAUD_OFF            0x14
  23 #define SPI_SHAW_OFF            0x18
  24
  25
  26 #define BIT_CTL_ENABLE      0x4000
  27 #define BIT_CTL_OPENDRAIN   0x2000
  28 #define BIT_CTL_MASTER      0x1000
  29 #define BIT_CTL_CPOL        0x0800
  30 #define BIT_CTL_CPHA        0x0400
  31 #define BIT_CTL_LSBF        0x0200
  32 #define BIT_CTL_WORDSIZE    0x0100
  33 #define BIT_CTL_EMISO       0x0020
  34 #define BIT_CTL_PSSE        0x0010
  35 #define BIT_CTL_GM          0x0008
  36 #define BIT_CTL_SZ          0x0004
  37 #define BIT_CTL_RXMOD       0x0000
  38 #define BIT_CTL_TXMOD       0x0001
  39 #define BIT_CTL_TIMOD_DMA_TX 0x0003
  40 #define BIT_CTL_TIMOD_DMA_RX 0x0002
  41 #define BIT_CTL_SENDOPT     0x0004
  42 #define BIT_CTL_TIMOD       0x0003
  43
  44 #define BIT_STAT_SPIF       0x0001
  45 #define BIT_STAT_MODF       0x0002
  46 #define BIT_STAT_TXE        0x0004
  47 #define BIT_STAT_TXS        0x0008
  48 #define BIT_STAT_RBSY       0x0010
  49 #define BIT_STAT_RXS        0x0020
  50 #define BIT_STAT_TXCOL      0x0040
  51 #define BIT_STAT_CLR        0xFFFF
  52
  53 #define BIT_STU_SENDOVER    0x0001
  54 #define BIT_STU_RECVFULL    0x0020
  55
  56 #define CFG_SPI_ENABLE      1
  57 #define CFG_SPI_DISABLE     0
  58
  59 #define CFG_SPI_OUTENABLE   1
  60 #define CFG_SPI_OUTDISABLE  0
  61
  62 #define CFG_SPI_ACTLOW      1
  63 #define CFG_SPI_ACTHIGH     0
  64
  65 #define CFG_SPI_PHASESTART  1
  66 #define CFG_SPI_PHASEMID    0
  67
  68 #define CFG_SPI_MASTER      1
  69 #define CFG_SPI_SLAVE       0
  70
  71 #define CFG_SPI_SENELAST    0
  72 #define CFG_SPI_SENDZERO    1
  73
  74 #define CFG_SPI_RCVFLUSH    1
  75 #define CFG_SPI_RCVDISCARD  0
  76
  77 #define CFG_SPI_LSBFIRST    1
  78 #define CFG_SPI_MSBFIRST    0
  79
  80 #define CFG_SPI_WORDSIZE16  1
  81 #define CFG_SPI_WORDSIZE8   0
  82
  83 #define CFG_SPI_MISOENABLE   1
  84 #define CFG_SPI_MISODISABLE  0
  85
  86 #define CFG_SPI_READ      0x00
  87 #define CFG_SPI_WRITE     0x01
  88 #define CFG_SPI_DMAREAD   0x02
  89 #define CFG_SPI_DMAWRITE  0x03
  90
  91 #define CFG_SPI_CSCLEARALL  0
  92 #define CFG_SPI_CHIPSEL1    1
  93 #define CFG_SPI_CHIPSEL2    2
  94 #define CFG_SPI_CHIPSEL3    3
  95 #define CFG_SPI_CHIPSEL4    4
  96 #define CFG_SPI_CHIPSEL5    5
  97 #define CFG_SPI_CHIPSEL6    6
  98 #define CFG_SPI_CHIPSEL7    7
  99
 100 #define CFG_SPI_CS1VALUE    1
 101 #define CFG_SPI_CS2VALUE    2
 102 #define CFG_SPI_CS3VALUE    3
 103 #define CFG_SPI_CS4VALUE    4
 104 #define CFG_SPI_CS5VALUE    5
 105 #define CFG_SPI_CS6VALUE    6
 106 #define CFG_SPI_CS7VALUE    7
 107
 108 #define CMD_SPI_SET_BAUDRATE  2
 109 #define CMD_SPI_GET_SYSTEMCLOCK   25
 110 #define CMD_SPI_SET_WRITECONTINUOUS     26
 111
 112 #define MAX_CTRL_CS          8  /* cs in spi controller */
 113
 114 /* device.platform_data for SSP controller devices */
 115 struct bfin5xx_spi_master {
 116         u16 num_chipselect;
 117         u8 enable_dma;
 118         u16 pin_req[7];
 119 };
 120
 121 /* spi_board_info.controller_data for SPI slave devices,
 122  * copied to spi_device.platform_data ... mostly for dma tuning
 123  */
 124 struct bfin5xx_spi_chip {
 125         u16 ctl_reg;
 126         u8 enable_dma;
 127         u8 bits_per_word;
 128         u16 cs_chg_udelay; /* Some devices require 16-bit delays */
 129         /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
 130         u16 idle_tx_val;
 131         u8 pio_interrupt; /* Enable spi data irq */
 132 };
 133
 134 #endif /* _SPI_CHANNEL_H_ */