arch/blackfin/mach-bf561/head.S

   1 /*
   2  * File:         arch/blackfin/mach-bf561/head.S
   3  * Based on:     arch/blackfin/mach-bf533/head.S
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  BF561 startup file
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/linkage.h>
  31 #include <linux/init.h>
  32 #include <asm/blackfin.h>
  33 #include <asm/trace.h>
  34
  35 #if CONFIG_BFIN_KERNEL_CLOCK
  36 #include <asm/mach-common/clocks.h>
  37 #include <asm/mach/mem_init.h>
  38 #endif
  39
  40 .extern ___bss_stop
  41 .extern ___bss_start
  42 .extern _bf53x_relocate_l1_mem
  43
  44 #define INITIAL_STACK   0xFFB01000
  45
  46 __INIT
  47
  48 ENTRY(__start)
  49         /* R0: argument of command line string, passed from uboot, save it */
  50         R7 = R0;
  51         /* Enable Cycle Counter and Nesting Of Interrupts */
  52 #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
  53         R0 = SYSCFG_SNEN;
  54 #else
  55         R0 = SYSCFG_SNEN | SYSCFG_CCEN;
  56 #endif
  57         SYSCFG = R0;
  58         R0 = 0;
  59
  60         /* Clear Out All the data and pointer Registers */
  61         R1 = R0;
  62         R2 = R0;
  63         R3 = R0;
  64         R4 = R0;
  65         R5 = R0;
  66         R6 = R0;
  67
  68         P0 = R0;
  69         P1 = R0;
  70         P2 = R0;
  71         P3 = R0;
  72         P4 = R0;
  73         P5 = R0;
  74
  75         LC0 = r0;
  76         LC1 = r0;
  77         L0 = r0;
  78         L1 = r0;
  79         L2 = r0;
  80         L3 = r0;
  81
  82         /* Clear Out All the DAG Registers */
  83         B0 = r0;
  84         B1 = r0;
  85         B2 = r0;
  86         B3 = r0;
  87
  88         I0 = r0;
  89         I1 = r0;
  90         I2 = r0;
  91         I3 = r0;
  92
  93         M0 = r0;
  94         M1 = r0;
  95         M2 = r0;
  96         M3 = r0;
  97
  98         trace_buffer_init(p0,r0);
  99         P0 = R1;
 100         R0 = R1;
 101
 102         /* Turn off the icache */
 103         p0.l = LO(IMEM_CONTROL);
 104         p0.h = HI(IMEM_CONTROL);
 105         R1 = [p0];
 106         R0 = ~ENICPLB;
 107         R0 = R0 & R1;
 108
 109 #if ANOMALY_05000125
 110         CLI R2;
 111         SSYNC;
 112 #endif
 113         [p0] = R0;
 114         SSYNC;
 115 #if ANOMALY_05000125
 116         STI R2;
 117 #endif
 118
 119         /* Turn off the dcache */
 120         p0.l = LO(DMEM_CONTROL);
 121         p0.h = HI(DMEM_CONTROL);
 122         R1 = [p0];
 123         R0 = ~ENDCPLB;
 124         R0 = R0 & R1;
 125
 126         /* Anomaly 05000125 */
 127 #if ANOMALY_05000125
 128         CLI R2;
 129         SSYNC;
 130 #endif
 131         [p0] = R0;
 132         SSYNC;
 133 #if ANOMALY_05000125
 134         STI R2;
 135 #endif
 136
 137         /* Initialise UART - when booting from u-boot, the UART is not disabled
 138          * so if we dont initalize here, our serial console gets hosed */
 139         p0.h = hi(BFIN_UART_LCR);
 140         p0.l = lo(BFIN_UART_LCR);
 141         r0 = 0x0(Z);
 142         w[p0] = r0.L;   /* To enable DLL writes */
 143         ssync;
 144
 145         p0.h = hi(BFIN_UART_DLL);
 146         p0.l = lo(BFIN_UART_DLL);
 147         r0 = 0x0(Z);
 148         w[p0] = r0.L;
 149         ssync;
 150
 151         p0.h = hi(BFIN_UART_DLH);
 152         p0.l = lo(BFIN_UART_DLH);
 153         r0 = 0x00(Z);
 154         w[p0] = r0.L;
 155         ssync;
 156
 157         p0.h = hi(BFIN_UART_GCTL);
 158         p0.l = lo(BFIN_UART_GCTL);
 159         r0 = 0x0(Z);
 160         w[p0] = r0.L;   /* To enable UART clock */
 161         ssync;
 162
 163         /* Initialize stack pointer */
 164         sp.l = lo(INITIAL_STACK);
 165         sp.h = hi(INITIAL_STACK);
 166         fp = sp;
 167         usp = sp;
 168
 169 #ifdef CONFIG_EARLY_PRINTK
 170         SP += -12;
 171         call _init_early_exception_vectors;
 172         SP += 12;
 173 #endif
 174
 175         /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
 176         call _bf53x_relocate_l1_mem;
 177 #if CONFIG_BFIN_KERNEL_CLOCK
 178         call _start_dma_code;
 179 #endif
 180
 181         /* Code for initializing Async memory banks */
 182
 183         p2.h = hi(EBIU_AMBCTL1);
 184         p2.l = lo(EBIU_AMBCTL1);
 185         r0.h = hi(AMBCTL1VAL);
 186         r0.l = lo(AMBCTL1VAL);
 187         [p2] = r0;
 188         ssync;
 189
 190         p2.h = hi(EBIU_AMBCTL0);
 191         p2.l = lo(EBIU_AMBCTL0);
 192         r0.h = hi(AMBCTL0VAL);
 193         r0.l = lo(AMBCTL0VAL);
 194         [p2] = r0;
 195         ssync;
 196
 197         p2.h = hi(EBIU_AMGCTL);
 198         p2.l = lo(EBIU_AMGCTL);
 199         r0 = AMGCTLVAL;
 200         w[p2] = r0;
 201         ssync;
 202
 203         /* This section keeps the processor in supervisor mode
 204          * during kernel boot.  Switches to user mode at end of boot.
 205          * See page 3-9 of Hardware Reference manual for documentation.
 206          */
 207
 208         /* EVT15 = _real_start */
 209
 210         p0.l = lo(EVT15);
 211         p0.h = hi(EVT15);
 212         p1.l = _real_start;
 213         p1.h = _real_start;
 214         [p0] = p1;
 215         csync;
 216
 217         p0.l = lo(IMASK);
 218         p0.h = hi(IMASK);
 219         p1.l = IMASK_IVG15;
 220         p1.h = 0x0;
 221         [p0] = p1;
 222         csync;
 223
 224         raise 15;
 225         p0.l = .LWAIT_HERE;
 226         p0.h = .LWAIT_HERE;
 227         reti = p0;
 228 #if ANOMALY_05000281
 229         nop; nop; nop;
 230 #endif
 231         rti;
 232
 233 .LWAIT_HERE:
 234         jump .LWAIT_HERE;
 235 ENDPROC(__start)
 236
 237 ENTRY(_real_start)
 238         [ -- sp ] = reti;
 239         p0.l = lo(WDOGA_CTL);
 240         p0.h = hi(WDOGA_CTL);
 241         r0 = 0xAD6(z);
 242         w[p0] = r0;     /* watchdog off for now */
 243         ssync;
 244
 245         /* Code update for BSS size == 0
 246          * Zero out the bss region.
 247          */
 248
 249         p1.l = ___bss_start;
 250         p1.h = ___bss_start;
 251         p2.l = ___bss_stop;
 252         p2.h = ___bss_stop;
 253         r0 = 0;
 254         p2 -= p1;
 255         lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
 256 .L_clear_bss:
 257         B[p1++] = r0;
 258
 259         /* In case there is a NULL pointer reference
 260          * Zero out region before stext
 261          */
 262
 263         p1.l = 0x0;
 264         p1.h = 0x0;
 265         r0.l = __stext;
 266         r0.h = __stext;
 267         r0 = r0 >> 1;
 268         p2 = r0;
 269         r0 = 0;
 270         lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
 271 .L_clear_zero:
 272         W[p1++] = r0;
 273
 274         /* pass the uboot arguments to the global value command line */
 275         R0 = R7;
 276         call _cmdline_init;
 277
 278         p1.l = __rambase;
 279         p1.h = __rambase;
 280         r0.l = __sdata;
 281         r0.h = __sdata;
 282         [p1] = r0;
 283
 284         p1.l = __ramstart;
 285         p1.h = __ramstart;
 286         p3.l = ___bss_stop;
 287         p3.h = ___bss_stop;
 288
 289         r1 = p3;
 290         [p1] = r1;
 291
 292         /*
 293          * load the current thread pointer and stack
 294          */
 295         r1.l = _init_thread_union;
 296         r1.h = _init_thread_union;
 297
 298         r2.l = 0x2000;
 299         r2.h = 0x0000;
 300         r1 = r1 + r2;
 301         sp = r1;
 302         usp = sp;
 303         fp = sp;
 304         jump.l _start_kernel;
 305 ENDPROC(_real_start)
 306
 307 __FINIT
 308
 309 .section .l1.text
 310 #if CONFIG_BFIN_KERNEL_CLOCK
 311 ENTRY(_start_dma_code)
 312         p0.h = hi(SICA_IWR0);
 313         p0.l = lo(SICA_IWR0);
 314         r0.l = 0x1;
 315         [p0] = r0;
 316         SSYNC;
 317
 318         /*
 319          *  Set PLL_CTL
 320          *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
 321          *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
 322          *   - [7]     = output delay (add 200ps of delay to mem signals)
 323          *   - [6]     = input delay (add 200ps of input delay to mem signals)
 324          *   - [5]     = PDWN      : 1=All Clocks off
 325          *   - [3]     = STOPCK    : 1=Core Clock off
 326          *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
 327          *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
 328          *   all other bits set to zero
 329          */
 330
 331         p0.h = hi(PLL_LOCKCNT);
 332         p0.l = lo(PLL_LOCKCNT);
 333         r0 = 0x300(Z);
 334         w[p0] = r0.l;
 335         ssync;
 336
 337         P2.H = hi(EBIU_SDGCTL);
 338         P2.L = lo(EBIU_SDGCTL);
 339         R0 = [P2];
 340         BITSET (R0, 24);
 341         [P2] = R0;
 342         SSYNC;
 343
 344         r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
 345         r0 = r0 << 9;                    /* Shift it over,                  */
 346         r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
 347         r0 = r1 | r0;
 348         r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
 349         r1 = r1 << 8;                    /* Shift it over                   */
 350         r0 = r1 | r0;                    /* add them all together           */
 351
 352         p0.h = hi(PLL_CTL);
 353         p0.l = lo(PLL_CTL);              /* Load the address                */
 354         cli r2;                          /* Disable interrupts              */
 355         ssync;
 356         w[p0] = r0.l;                    /* Set the value                   */
 357         idle;                            /* Wait for the PLL to stablize    */
 358         sti r2;                          /* Enable interrupts               */
 359
 360 .Lcheck_again:
 361         p0.h = hi(PLL_STAT);
 362         p0.l = lo(PLL_STAT);
 363         R0 = W[P0](Z);
 364         CC = BITTST(R0,5);
 365         if ! CC jump .Lcheck_again;
 366
 367         /* Configure SCLK & CCLK Dividers */
 368         r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
 369         p0.h = hi(PLL_DIV);
 370         p0.l = lo(PLL_DIV);
 371         w[p0] = r0.l;
 372         ssync;
 373
 374         p0.l = lo(EBIU_SDRRC);
 375         p0.h = hi(EBIU_SDRRC);
 376         r0 = mem_SDRRC;
 377         w[p0] = r0.l;
 378         ssync;
 379
 380         P2.H = hi(EBIU_SDGCTL);
 381         P2.L = lo(EBIU_SDGCTL);
 382         R0 = [P2];
 383         BITCLR (R0, 24);
 384         p0.h = hi(EBIU_SDSTAT);
 385         p0.l = lo(EBIU_SDSTAT);
 386         r2.l = w[p0];
 387         cc = bittst(r2,3);
 388         if !cc jump .Lskip;
 389         NOP;
 390         BITSET (R0, 23);
 391 .Lskip:
 392         [P2] = R0;
 393         SSYNC;
 394
 395         R0.L = lo(mem_SDGCTL);
 396         R0.H = hi(mem_SDGCTL);
 397         R1 = [p2];
 398         R1 = R1 | R0;
 399         [P2] = R1;
 400         SSYNC;
 401
 402         RTS;
 403 ENDPROC(_start_dma_code)
 404 #endif /* CONFIG_BFIN_KERNEL_CLOCK */