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Merge commit 'origin/queue' into for-queue
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority.c
1 /*
2 * Set up the interrupt priorities
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
10 *
11 * Licensed under the GPL-2
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
19 #include <linux/syscore_ops.h>
20 #include <asm/delay.h>
21 #ifdef CONFIG_IPIPE
22 #include <linux/ipipe.h>
23 #endif
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
26 #include <asm/gpio.h>
27 #include <asm/irq_handler.h>
28 #include <asm/dpmc.h>
29 #include <asm/traps.h>
30
31 #ifndef SEC_GCTL
32 # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
33 #else
34 # define SIC_SYSIRQ(irq) ((irq) - IVG15)
35 #endif
36
37 /*
38 * NOTES:
39 * - we have separated the physical Hardware interrupt from the
40 * levels that the LINUX kernel sees (see the description in irq.h)
41 * -
42 */
43
44 #ifndef CONFIG_SMP
45 /* Initialize this to an actual value to force it into the .data
46 * section so that we know it is properly initialized at entry into
47 * the kernel but before bss is initialized to zero (which is where
48 * it would live otherwise). The 0x1f magic represents the IRQs we
49 * cannot actually mask out in hardware.
50 */
51 unsigned long bfin_irq_flags = 0x1f;
52 EXPORT_SYMBOL(bfin_irq_flags);
53 #endif
54
55 #ifdef CONFIG_PM
56 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
57 unsigned vr_wakeup;
58 #endif
59
60 #ifndef SEC_GCTL
61 static struct ivgx {
62 /* irq number for request_irq, available in mach-bf5xx/irq.h */
63 unsigned int irqno;
64 /* corresponding bit in the SIC_ISR register */
65 unsigned int isrflag;
66 } ivg_table[NR_PERI_INTS];
67
68 static struct ivg_slice {
69 /* position of first irq in ivg_table for given ivg */
70 struct ivgx *ifirst;
71 struct ivgx *istop;
72 } ivg7_13[IVG13 - IVG7 + 1];
73
74
75 /*
76 * Search SIC_IAR and fill tables with the irqvalues
77 * and their positions in the SIC_ISR register.
78 */
79 static void __init search_IAR(void)
80 {
81 unsigned ivg, irq_pos = 0;
82 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
83 int irqN;
84
85 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
86
87 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
88 int irqn;
89 u32 iar =
90 bfin_read32((unsigned long *)SIC_IAR0 +
91 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
92 defined(CONFIG_BF538) || defined(CONFIG_BF539)
93 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
94 #else
95 (irqN >> 3)
96 #endif
97 );
98 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
99 int iar_shift = (irqn & 7) * 4;
100 if (ivg == (0xf & (iar >> iar_shift))) {
101 ivg_table[irq_pos].irqno = IVG7 + irqn;
102 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
103 ivg7_13[ivg].istop++;
104 irq_pos++;
105 }
106 }
107 }
108 }
109 }
110 #endif
111
112 /*
113 * This is for core internal IRQs
114 */
115 void bfin_ack_noop(struct irq_data *d)
116 {
117 /* Dummy function. */
118 }
119
120 static void bfin_core_mask_irq(struct irq_data *d)
121 {
122 bfin_irq_flags &= ~(1 << d->irq);
123 if (!hard_irqs_disabled())
124 hard_local_irq_enable();
125 }
126
127 static void bfin_core_unmask_irq(struct irq_data *d)
128 {
129 bfin_irq_flags |= 1 << d->irq;
130 /*
131 * If interrupts are enabled, IMASK must contain the same value
132 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
133 * are currently disabled we need not do anything; one of the
134 * callers will take care of setting IMASK to the proper value
135 * when reenabling interrupts.
136 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
137 * what we need.
138 */
139 if (!hard_irqs_disabled())
140 hard_local_irq_enable();
141 return;
142 }
143
144 void bfin_internal_mask_irq(unsigned int irq)
145 {
146 unsigned long flags = hard_local_irq_save();
147 #ifndef SEC_GCTL
148 #ifdef SIC_IMASK0
149 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
150 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
151 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
152 ~(1 << mask_bit));
153 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
154 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
155 ~(1 << mask_bit));
156 # endif
157 #else
158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << SIC_SYSIRQ(irq)));
160 #endif /* end of SIC_IMASK0 */
161 #endif
162 hard_local_irq_restore(flags);
163 }
164
165 static void bfin_internal_mask_irq_chip(struct irq_data *d)
166 {
167 bfin_internal_mask_irq(d->irq);
168 }
169
170 #ifdef CONFIG_SMP
171 void bfin_internal_unmask_irq_affinity(unsigned int irq,
172 const struct cpumask *affinity)
173 #else
174 void bfin_internal_unmask_irq(unsigned int irq)
175 #endif
176 {
177 unsigned long flags = hard_local_irq_save();
178
179 #ifndef SEC_GCTL
180 #ifdef SIC_IMASK0
181 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
182 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
183 # ifdef CONFIG_SMP
184 if (cpumask_test_cpu(0, affinity))
185 # endif
186 bfin_write_SIC_IMASK(mask_bank,
187 bfin_read_SIC_IMASK(mask_bank) |
188 (1 << mask_bit));
189 # ifdef CONFIG_SMP
190 if (cpumask_test_cpu(1, affinity))
191 bfin_write_SICB_IMASK(mask_bank,
192 bfin_read_SICB_IMASK(mask_bank) |
193 (1 << mask_bit));
194 # endif
195 #else
196 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
197 (1 << SIC_SYSIRQ(irq)));
198 #endif
199 #endif
200 hard_local_irq_restore(flags);
201 }
202
203 #ifdef SEC_GCTL
204 static void bfin_sec_preflow_handler(struct irq_data *d)
205 {
206 unsigned long flags = hard_local_irq_save();
207 unsigned int sid = SIC_SYSIRQ(d->irq);
208
209 bfin_write_SEC_SCI(0, SEC_CSID, sid);
210
211 hard_local_irq_restore(flags);
212 }
213
214 static void bfin_sec_mask_ack_irq(struct irq_data *d)
215 {
216 unsigned long flags = hard_local_irq_save();
217 unsigned int sid = SIC_SYSIRQ(d->irq);
218
219 bfin_write_SEC_SCI(0, SEC_CSID, sid);
220
221 hard_local_irq_restore(flags);
222 }
223
224 static void bfin_sec_unmask_irq(struct irq_data *d)
225 {
226 unsigned long flags = hard_local_irq_save();
227 unsigned int sid = SIC_SYSIRQ(d->irq);
228
229 bfin_write32(SEC_END, sid);
230
231 hard_local_irq_restore(flags);
232 }
233
234 static void bfin_sec_enable_ssi(unsigned int sid)
235 {
236 unsigned long flags = hard_local_irq_save();
237 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
238
239 reg_sctl |= SEC_SCTL_SRC_EN;
240 bfin_write_SEC_SCTL(sid, reg_sctl);
241
242 hard_local_irq_restore(flags);
243 }
244
245 static void bfin_sec_disable_ssi(unsigned int sid)
246 {
247 unsigned long flags = hard_local_irq_save();
248 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
249
250 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
251 bfin_write_SEC_SCTL(sid, reg_sctl);
252
253 hard_local_irq_restore(flags);
254 }
255
256 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
257 {
258 unsigned long flags = hard_local_irq_save();
259 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
260
261 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
262 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
263
264 hard_local_irq_restore(flags);
265 }
266
267 static void bfin_sec_enable_sci(unsigned int sid)
268 {
269 unsigned long flags = hard_local_irq_save();
270 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
271
272 if (sid == SIC_SYSIRQ(IRQ_WATCH0))
273 reg_sctl |= SEC_SCTL_FAULT_EN;
274 else
275 reg_sctl |= SEC_SCTL_INT_EN;
276 bfin_write_SEC_SCTL(sid, reg_sctl);
277
278 hard_local_irq_restore(flags);
279 }
280
281 static void bfin_sec_disable_sci(unsigned int sid)
282 {
283 unsigned long flags = hard_local_irq_save();
284 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
285
286 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
287 bfin_write_SEC_SCTL(sid, reg_sctl);
288
289 hard_local_irq_restore(flags);
290 }
291
292 static void bfin_sec_enable(struct irq_data *d)
293 {
294 unsigned long flags = hard_local_irq_save();
295 unsigned int sid = SIC_SYSIRQ(d->irq);
296
297 bfin_sec_enable_sci(sid);
298 bfin_sec_enable_ssi(sid);
299
300 hard_local_irq_restore(flags);
301 }
302
303 static void bfin_sec_disable(struct irq_data *d)
304 {
305 unsigned long flags = hard_local_irq_save();
306 unsigned int sid = SIC_SYSIRQ(d->irq);
307
308 bfin_sec_disable_sci(sid);
309 bfin_sec_disable_ssi(sid);
310
311 hard_local_irq_restore(flags);
312 }
313
314 static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
315 {
316 unsigned long flags = hard_local_irq_save();
317 uint32_t reg_sctl;
318 int i;
319
320 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
321
322 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
323 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
324 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
325 bfin_write_SEC_SCTL(i, reg_sctl);
326 }
327
328 hard_local_irq_restore(flags);
329 }
330
331 void bfin_sec_raise_irq(unsigned int sid)
332 {
333 unsigned long flags = hard_local_irq_save();
334
335 bfin_write32(SEC_RAISE, sid);
336
337 hard_local_irq_restore(flags);
338 }
339
340 static void init_software_driven_irq(void)
341 {
342 bfin_sec_set_ssi_coreid(34, 0);
343 bfin_sec_set_ssi_coreid(35, 1);
344 bfin_sec_set_ssi_coreid(36, 0);
345 bfin_sec_set_ssi_coreid(37, 1);
346 }
347
348 void bfin_sec_resume(void)
349 {
350 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
351 udelay(100);
352 bfin_write_SEC_GCTL(SEC_GCTL_EN);
353 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
354 }
355
356 void handle_sec_sfi_fault(uint32_t gstat)
357 {
358
359 }
360
361 void handle_sec_sci_fault(uint32_t gstat)
362 {
363 uint32_t core_id;
364 uint32_t cstat;
365
366 core_id = gstat & SEC_GSTAT_SCI;
367 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
368 if (cstat & SEC_CSTAT_ERR) {
369 switch (cstat & SEC_CSTAT_ERRC) {
370 case SEC_CSTAT_ACKERR:
371 printk(KERN_DEBUG "sec ack err\n");
372 break;
373 default:
374 printk(KERN_DEBUG "sec sci unknow err\n");
375 }
376 }
377
378 }
379
380 void handle_sec_ssi_fault(uint32_t gstat)
381 {
382 uint32_t sid;
383 uint32_t sstat;
384
385 sid = gstat & SEC_GSTAT_SID;
386 sstat = bfin_read_SEC_SSTAT(sid);
387
388 }
389
390 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
391 {
392 uint32_t sec_gstat;
393
394 raw_spin_lock(&desc->lock);
395
396 sec_gstat = bfin_read32(SEC_GSTAT);
397 if (sec_gstat & SEC_GSTAT_ERR) {
398
399 switch (sec_gstat & SEC_GSTAT_ERRC) {
400 case 0:
401 handle_sec_sfi_fault(sec_gstat);
402 break;
403 case SEC_GSTAT_SCIERR:
404 handle_sec_sci_fault(sec_gstat);
405 break;
406 case SEC_GSTAT_SSIERR:
407 handle_sec_ssi_fault(sec_gstat);
408 break;
409 }
410
411
412 }
413
414 raw_spin_unlock(&desc->lock);
415 }
416
417 void handle_core_fault(unsigned int irq, struct irq_desc *desc)
418 {
419 struct pt_regs *fp = get_irq_regs();
420
421 raw_spin_lock(&desc->lock);
422
423 switch (irq) {
424 case IRQ_C0_DBL_FAULT:
425 double_fault_c(fp);
426 break;
427 case IRQ_C0_HW_ERR:
428 dump_bfin_process(fp);
429 dump_bfin_mem(fp);
430 show_regs(fp);
431 printk(KERN_NOTICE "Kernel Stack\n");
432 show_stack(current, NULL);
433 print_modules();
434 panic("Kernel core hardware error");
435 break;
436 case IRQ_C0_NMI_L1_PARITY_ERR:
437 panic("NMI occurs unexpectedly");
438 break;
439 default:
440 panic("Core 1 fault occurs unexpectedly");
441 }
442
443 raw_spin_unlock(&desc->lock);
444 }
445 #endif
446
447 #ifdef CONFIG_SMP
448 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
449 {
450 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
451 }
452
453 static int bfin_internal_set_affinity(struct irq_data *d,
454 const struct cpumask *mask, bool force)
455 {
456 bfin_internal_mask_irq(d->irq);
457 bfin_internal_unmask_irq_affinity(d->irq, mask);
458
459 return 0;
460 }
461 #else
462 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
463 {
464 bfin_internal_unmask_irq(d->irq);
465 }
466 #endif
467
468 #if defined(CONFIG_PM) && !defined(SEC_GCTL)
469 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
470 {
471 u32 bank, bit, wakeup = 0;
472 unsigned long flags;
473 bank = SIC_SYSIRQ(irq) / 32;
474 bit = SIC_SYSIRQ(irq) % 32;
475
476 switch (irq) {
477 #ifdef IRQ_RTC
478 case IRQ_RTC:
479 wakeup |= WAKE;
480 break;
481 #endif
482 #ifdef IRQ_CAN0_RX
483 case IRQ_CAN0_RX:
484 wakeup |= CANWE;
485 break;
486 #endif
487 #ifdef IRQ_CAN1_RX
488 case IRQ_CAN1_RX:
489 wakeup |= CANWE;
490 break;
491 #endif
492 #ifdef IRQ_USB_INT0
493 case IRQ_USB_INT0:
494 wakeup |= USBWE;
495 break;
496 #endif
497 #ifdef CONFIG_BF54x
498 case IRQ_CNT:
499 wakeup |= ROTWE;
500 break;
501 #endif
502 default:
503 break;
504 }
505
506 flags = hard_local_irq_save();
507
508 if (state) {
509 bfin_sic_iwr[bank] |= (1 << bit);
510 vr_wakeup |= wakeup;
511
512 } else {
513 bfin_sic_iwr[bank] &= ~(1 << bit);
514 vr_wakeup &= ~wakeup;
515 }
516
517 hard_local_irq_restore(flags);
518
519 return 0;
520 }
521
522 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
523 {
524 return bfin_internal_set_wake(d->irq, state);
525 }
526 #else
527 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
528 {
529 return 0;
530 }
531 # define bfin_internal_set_wake_chip NULL
532 #endif
533
534 static struct irq_chip bfin_core_irqchip = {
535 .name = "CORE",
536 .irq_mask = bfin_core_mask_irq,
537 .irq_unmask = bfin_core_unmask_irq,
538 };
539
540 static struct irq_chip bfin_internal_irqchip = {
541 .name = "INTN",
542 .irq_mask = bfin_internal_mask_irq_chip,
543 .irq_unmask = bfin_internal_unmask_irq_chip,
544 .irq_disable = bfin_internal_mask_irq_chip,
545 .irq_enable = bfin_internal_unmask_irq_chip,
546 #ifdef CONFIG_SMP
547 .irq_set_affinity = bfin_internal_set_affinity,
548 #endif
549 .irq_set_wake = bfin_internal_set_wake_chip,
550 };
551
552 #ifdef SEC_GCTL
553 static struct irq_chip bfin_sec_irqchip = {
554 .name = "SEC",
555 .irq_mask_ack = bfin_sec_mask_ack_irq,
556 .irq_mask = bfin_sec_mask_ack_irq,
557 .irq_unmask = bfin_sec_unmask_irq,
558 .irq_eoi = bfin_sec_unmask_irq,
559 .irq_disable = bfin_sec_disable,
560 .irq_enable = bfin_sec_enable,
561 };
562 #endif
563
564 void bfin_handle_irq(unsigned irq)
565 {
566 #ifdef CONFIG_IPIPE
567 struct pt_regs regs; /* Contents not used. */
568 ipipe_trace_irq_entry(irq);
569 __ipipe_handle_irq(irq, &regs);
570 ipipe_trace_irq_exit(irq);
571 #else /* !CONFIG_IPIPE */
572 generic_handle_irq(irq);
573 #endif /* !CONFIG_IPIPE */
574 }
575
576 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
577 static int mac_stat_int_mask;
578
579 static void bfin_mac_status_ack_irq(unsigned int irq)
580 {
581 switch (irq) {
582 case IRQ_MAC_MMCINT:
583 bfin_write_EMAC_MMC_TIRQS(
584 bfin_read_EMAC_MMC_TIRQE() &
585 bfin_read_EMAC_MMC_TIRQS());
586 bfin_write_EMAC_MMC_RIRQS(
587 bfin_read_EMAC_MMC_RIRQE() &
588 bfin_read_EMAC_MMC_RIRQS());
589 break;
590 case IRQ_MAC_RXFSINT:
591 bfin_write_EMAC_RX_STKY(
592 bfin_read_EMAC_RX_IRQE() &
593 bfin_read_EMAC_RX_STKY());
594 break;
595 case IRQ_MAC_TXFSINT:
596 bfin_write_EMAC_TX_STKY(
597 bfin_read_EMAC_TX_IRQE() &
598 bfin_read_EMAC_TX_STKY());
599 break;
600 case IRQ_MAC_WAKEDET:
601 bfin_write_EMAC_WKUP_CTL(
602 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
603 break;
604 default:
605 /* These bits are W1C */
606 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
607 break;
608 }
609 }
610
611 static void bfin_mac_status_mask_irq(struct irq_data *d)
612 {
613 unsigned int irq = d->irq;
614
615 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
616 #ifdef BF537_FAMILY
617 switch (irq) {
618 case IRQ_MAC_PHYINT:
619 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
620 break;
621 default:
622 break;
623 }
624 #else
625 if (!mac_stat_int_mask)
626 bfin_internal_mask_irq(IRQ_MAC_ERROR);
627 #endif
628 bfin_mac_status_ack_irq(irq);
629 }
630
631 static void bfin_mac_status_unmask_irq(struct irq_data *d)
632 {
633 unsigned int irq = d->irq;
634
635 #ifdef BF537_FAMILY
636 switch (irq) {
637 case IRQ_MAC_PHYINT:
638 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
639 break;
640 default:
641 break;
642 }
643 #else
644 if (!mac_stat_int_mask)
645 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
646 #endif
647 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
648 }
649
650 #ifdef CONFIG_PM
651 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
652 {
653 #ifdef BF537_FAMILY
654 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
655 #else
656 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
657 #endif
658 }
659 #else
660 # define bfin_mac_status_set_wake NULL
661 #endif
662
663 static struct irq_chip bfin_mac_status_irqchip = {
664 .name = "MACST",
665 .irq_mask = bfin_mac_status_mask_irq,
666 .irq_unmask = bfin_mac_status_unmask_irq,
667 .irq_set_wake = bfin_mac_status_set_wake,
668 };
669
670 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
671 struct irq_desc *inta_desc)
672 {
673 int i, irq = 0;
674 u32 status = bfin_read_EMAC_SYSTAT();
675
676 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
677 if (status & (1L << i)) {
678 irq = IRQ_MAC_PHYINT + i;
679 break;
680 }
681
682 if (irq) {
683 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
684 bfin_handle_irq(irq);
685 } else {
686 bfin_mac_status_ack_irq(irq);
687 pr_debug("IRQ %d:"
688 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
689 irq);
690 }
691 } else
692 printk(KERN_ERR
693 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
694 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
695 "(EMAC_SYSTAT=0x%X)\n",
696 __func__, __FILE__, __LINE__, status);
697 }
698 #endif
699
700 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
701 {
702 #ifdef CONFIG_IPIPE
703 handle = handle_level_irq;
704 #endif
705 __irq_set_handler_locked(irq, handle);
706 }
707
708 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
709 extern void bfin_gpio_irq_prepare(unsigned gpio);
710
711 #if !BFIN_GPIO_PINT
712
713 static void bfin_gpio_ack_irq(struct irq_data *d)
714 {
715 /* AFAIK ack_irq in case mask_ack is provided
716 * get's only called for edge sense irqs
717 */
718 set_gpio_data(irq_to_gpio(d->irq), 0);
719 }
720
721 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
722 {
723 unsigned int irq = d->irq;
724 u32 gpionr = irq_to_gpio(irq);
725
726 if (!irqd_is_level_type(d))
727 set_gpio_data(gpionr, 0);
728
729 set_gpio_maska(gpionr, 0);
730 }
731
732 static void bfin_gpio_mask_irq(struct irq_data *d)
733 {
734 set_gpio_maska(irq_to_gpio(d->irq), 0);
735 }
736
737 static void bfin_gpio_unmask_irq(struct irq_data *d)
738 {
739 set_gpio_maska(irq_to_gpio(d->irq), 1);
740 }
741
742 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
743 {
744 u32 gpionr = irq_to_gpio(d->irq);
745
746 if (__test_and_set_bit(gpionr, gpio_enabled))
747 bfin_gpio_irq_prepare(gpionr);
748
749 bfin_gpio_unmask_irq(d);
750
751 return 0;
752 }
753
754 static void bfin_gpio_irq_shutdown(struct irq_data *d)
755 {
756 u32 gpionr = irq_to_gpio(d->irq);
757
758 bfin_gpio_mask_irq(d);
759 __clear_bit(gpionr, gpio_enabled);
760 bfin_gpio_irq_free(gpionr);
761 }
762
763 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
764 {
765 unsigned int irq = d->irq;
766 int ret;
767 char buf[16];
768 u32 gpionr = irq_to_gpio(irq);
769
770 if (type == IRQ_TYPE_PROBE) {
771 /* only probe unenabled GPIO interrupt lines */
772 if (test_bit(gpionr, gpio_enabled))
773 return 0;
774 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
775 }
776
777 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
778 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
779
780 snprintf(buf, 16, "gpio-irq%d", irq);
781 ret = bfin_gpio_irq_request(gpionr, buf);
782 if (ret)
783 return ret;
784
785 if (__test_and_set_bit(gpionr, gpio_enabled))
786 bfin_gpio_irq_prepare(gpionr);
787
788 } else {
789 __clear_bit(gpionr, gpio_enabled);
790 return 0;
791 }
792
793 set_gpio_inen(gpionr, 0);
794 set_gpio_dir(gpionr, 0);
795
796 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
797 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
798 set_gpio_both(gpionr, 1);
799 else
800 set_gpio_both(gpionr, 0);
801
802 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
803 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
804 else
805 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
806
807 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
808 set_gpio_edge(gpionr, 1);
809 set_gpio_inen(gpionr, 1);
810 set_gpio_data(gpionr, 0);
811
812 } else {
813 set_gpio_edge(gpionr, 0);
814 set_gpio_inen(gpionr, 1);
815 }
816
817 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
818 bfin_set_irq_handler(irq, handle_edge_irq);
819 else
820 bfin_set_irq_handler(irq, handle_level_irq);
821
822 return 0;
823 }
824
825 #ifdef CONFIG_PM
826 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
827 {
828 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
829 }
830 #else
831 # define bfin_gpio_set_wake NULL
832 #endif
833
834 static void bfin_demux_gpio_block(unsigned int irq)
835 {
836 unsigned int gpio, mask;
837
838 gpio = irq_to_gpio(irq);
839 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
840
841 while (mask) {
842 if (mask & 1)
843 bfin_handle_irq(irq);
844 irq++;
845 mask >>= 1;
846 }
847 }
848
849 void bfin_demux_gpio_irq(unsigned int inta_irq,
850 struct irq_desc *desc)
851 {
852 unsigned int irq;
853
854 switch (inta_irq) {
855 #if defined(BF537_FAMILY)
856 case IRQ_PF_INTA_PG_INTA:
857 bfin_demux_gpio_block(IRQ_PF0);
858 irq = IRQ_PG0;
859 break;
860 case IRQ_PH_INTA_MAC_RX:
861 irq = IRQ_PH0;
862 break;
863 #elif defined(BF533_FAMILY)
864 case IRQ_PROG_INTA:
865 irq = IRQ_PF0;
866 break;
867 #elif defined(BF538_FAMILY)
868 case IRQ_PORTF_INTA:
869 irq = IRQ_PF0;
870 break;
871 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
872 case IRQ_PORTF_INTA:
873 irq = IRQ_PF0;
874 break;
875 case IRQ_PORTG_INTA:
876 irq = IRQ_PG0;
877 break;
878 case IRQ_PORTH_INTA:
879 irq = IRQ_PH0;
880 break;
881 #elif defined(CONFIG_BF561)
882 case IRQ_PROG0_INTA:
883 irq = IRQ_PF0;
884 break;
885 case IRQ_PROG1_INTA:
886 irq = IRQ_PF16;
887 break;
888 case IRQ_PROG2_INTA:
889 irq = IRQ_PF32;
890 break;
891 #endif
892 default:
893 BUG();
894 return;
895 }
896
897 bfin_demux_gpio_block(irq);
898 }
899
900 #else
901
902 #define NR_PINT_BITS 32
903 #define IRQ_NOT_AVAIL 0xFF
904
905 #define PINT_2_BANK(x) ((x) >> 5)
906 #define PINT_2_BIT(x) ((x) & 0x1F)
907 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
908
909 static unsigned char irq2pint_lut[NR_PINTS];
910 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
911
912 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
913 (struct bfin_pint_regs *)PINT0_MASK_SET,
914 (struct bfin_pint_regs *)PINT1_MASK_SET,
915 (struct bfin_pint_regs *)PINT2_MASK_SET,
916 (struct bfin_pint_regs *)PINT3_MASK_SET,
917 #ifdef CONFIG_BF60x
918 (struct bfin_pint_regs *)PINT4_MASK_SET,
919 (struct bfin_pint_regs *)PINT5_MASK_SET,
920 #endif
921 };
922
923 inline unsigned int get_irq_base(u32 bank, u8 bmap)
924 {
925 unsigned int irq_base;
926
927 #ifndef CONFIG_BF60x
928 if (bank < 2) { /*PA-PB */
929 irq_base = IRQ_PA0 + bmap * 16;
930 } else { /*PC-PJ */
931 irq_base = IRQ_PC0 + bmap * 16;
932 }
933 #else
934 irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
935 #endif
936 return irq_base;
937 }
938
939 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
940 void init_pint_lut(void)
941 {
942 u16 bank, bit, irq_base, bit_pos;
943 u32 pint_assign;
944 u8 bmap;
945
946 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
947
948 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
949
950 pint_assign = pint[bank]->assign;
951
952 for (bit = 0; bit < NR_PINT_BITS; bit++) {
953
954 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
955
956 irq_base = get_irq_base(bank, bmap);
957
958 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
959 bit_pos = bit + bank * NR_PINT_BITS;
960
961 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
962 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
963 }
964 }
965 }
966
967 static void bfin_gpio_ack_irq(struct irq_data *d)
968 {
969 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
970 u32 pintbit = PINT_BIT(pint_val);
971 u32 bank = PINT_2_BANK(pint_val);
972
973 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
974 if (pint[bank]->invert_set & pintbit)
975 pint[bank]->invert_clear = pintbit;
976 else
977 pint[bank]->invert_set = pintbit;
978 }
979 pint[bank]->request = pintbit;
980
981 }
982
983 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
984 {
985 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
986 u32 pintbit = PINT_BIT(pint_val);
987 u32 bank = PINT_2_BANK(pint_val);
988
989 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
990 if (pint[bank]->invert_set & pintbit)
991 pint[bank]->invert_clear = pintbit;
992 else
993 pint[bank]->invert_set = pintbit;
994 }
995
996 pint[bank]->request = pintbit;
997 pint[bank]->mask_clear = pintbit;
998 }
999
1000 static void bfin_gpio_mask_irq(struct irq_data *d)
1001 {
1002 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1003
1004 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
1005 }
1006
1007 static void bfin_gpio_unmask_irq(struct irq_data *d)
1008 {
1009 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1010 u32 pintbit = PINT_BIT(pint_val);
1011 u32 bank = PINT_2_BANK(pint_val);
1012
1013 pint[bank]->mask_set = pintbit;
1014 }
1015
1016 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
1017 {
1018 unsigned int irq = d->irq;
1019 u32 gpionr = irq_to_gpio(irq);
1020 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1021
1022 if (pint_val == IRQ_NOT_AVAIL) {
1023 printk(KERN_ERR
1024 "GPIO IRQ %d :Not in PINT Assign table "
1025 "Reconfigure Interrupt to Port Assignemt\n", irq);
1026 return -ENODEV;
1027 }
1028
1029 if (__test_and_set_bit(gpionr, gpio_enabled))
1030 bfin_gpio_irq_prepare(gpionr);
1031
1032 bfin_gpio_unmask_irq(d);
1033
1034 return 0;
1035 }
1036
1037 static void bfin_gpio_irq_shutdown(struct irq_data *d)
1038 {
1039 u32 gpionr = irq_to_gpio(d->irq);
1040
1041 bfin_gpio_mask_irq(d);
1042 __clear_bit(gpionr, gpio_enabled);
1043 bfin_gpio_irq_free(gpionr);
1044 }
1045
1046 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1047 {
1048 unsigned int irq = d->irq;
1049 int ret;
1050 char buf[16];
1051 u32 gpionr = irq_to_gpio(irq);
1052 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1053 u32 pintbit = PINT_BIT(pint_val);
1054 u32 bank = PINT_2_BANK(pint_val);
1055
1056 if (pint_val == IRQ_NOT_AVAIL)
1057 return -ENODEV;
1058
1059 if (type == IRQ_TYPE_PROBE) {
1060 /* only probe unenabled GPIO interrupt lines */
1061 if (test_bit(gpionr, gpio_enabled))
1062 return 0;
1063 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1064 }
1065
1066 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1067 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1068
1069 snprintf(buf, 16, "gpio-irq%d", irq);
1070 ret = bfin_gpio_irq_request(gpionr, buf);
1071 if (ret)
1072 return ret;
1073
1074 if (__test_and_set_bit(gpionr, gpio_enabled))
1075 bfin_gpio_irq_prepare(gpionr);
1076
1077 } else {
1078 __clear_bit(gpionr, gpio_enabled);
1079 return 0;
1080 }
1081
1082 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1083 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
1084 else
1085 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
1086
1087 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1088 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1089 if (gpio_get_value(gpionr))
1090 pint[bank]->invert_set = pintbit;
1091 else
1092 pint[bank]->invert_clear = pintbit;
1093 }
1094
1095 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1096 pint[bank]->edge_set = pintbit;
1097 bfin_set_irq_handler(irq, handle_edge_irq);
1098 } else {
1099 pint[bank]->edge_clear = pintbit;
1100 bfin_set_irq_handler(irq, handle_level_irq);
1101 }
1102
1103 return 0;
1104 }
1105
1106 #ifdef CONFIG_PM
1107 static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1108 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1109
1110 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1111 {
1112 u32 pint_irq;
1113 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1114 u32 bank = PINT_2_BANK(pint_val);
1115
1116 switch (bank) {
1117 case 0:
1118 pint_irq = IRQ_PINT0;
1119 break;
1120 case 2:
1121 pint_irq = IRQ_PINT2;
1122 break;
1123 case 3:
1124 pint_irq = IRQ_PINT3;
1125 break;
1126 case 1:
1127 pint_irq = IRQ_PINT1;
1128 break;
1129 #ifdef CONFIG_BF60x
1130 case 4:
1131 pint_irq = IRQ_PINT4;
1132 break;
1133 case 5:
1134 pint_irq = IRQ_PINT5;
1135 break;
1136 #endif
1137 default:
1138 return -EINVAL;
1139 }
1140
1141 bfin_internal_set_wake(pint_irq, state);
1142
1143 return 0;
1144 }
1145
1146 void bfin_pint_suspend(void)
1147 {
1148 u32 bank;
1149
1150 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1151 save_pint_reg[bank].mask_set = pint[bank]->mask_set;
1152 save_pint_reg[bank].assign = pint[bank]->assign;
1153 save_pint_reg[bank].edge_set = pint[bank]->edge_set;
1154 save_pint_reg[bank].invert_set = pint[bank]->invert_set;
1155 }
1156 }
1157
1158 void bfin_pint_resume(void)
1159 {
1160 u32 bank;
1161
1162 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1163 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1164 pint[bank]->assign = save_pint_reg[bank].assign;
1165 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1166 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1167 }
1168 }
1169
1170 #ifdef SEC_GCTL
1171 static int sec_suspend(void)
1172 {
1173 u32 bank;
1174
1175 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1176 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
1177 return 0;
1178 }
1179
1180 static void sec_resume(void)
1181 {
1182 u32 bank;
1183
1184 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1185 udelay(100);
1186 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1187 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1188
1189 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1190 bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
1191 }
1192
1193 static struct syscore_ops sec_pm_syscore_ops = {
1194 .suspend = sec_suspend,
1195 .resume = sec_resume,
1196 };
1197 #endif
1198 #else
1199 # define bfin_gpio_set_wake NULL
1200 #endif
1201
1202 void bfin_demux_gpio_irq(unsigned int inta_irq,
1203 struct irq_desc *desc)
1204 {
1205 u32 bank, pint_val;
1206 u32 request, irq;
1207 u32 level_mask;
1208 int umask = 0;
1209 struct irq_chip *chip = irq_desc_get_chip(desc);
1210
1211 if (chip->irq_mask_ack) {
1212 chip->irq_mask_ack(&desc->irq_data);
1213 } else {
1214 chip->irq_mask(&desc->irq_data);
1215 if (chip->irq_ack)
1216 chip->irq_ack(&desc->irq_data);
1217 }
1218
1219 switch (inta_irq) {
1220 case IRQ_PINT0:
1221 bank = 0;
1222 break;
1223 case IRQ_PINT2:
1224 bank = 2;
1225 break;
1226 case IRQ_PINT3:
1227 bank = 3;
1228 break;
1229 case IRQ_PINT1:
1230 bank = 1;
1231 break;
1232 #ifdef CONFIG_BF60x
1233 case IRQ_PINT4:
1234 bank = 4;
1235 break;
1236 case IRQ_PINT5:
1237 bank = 5;
1238 break;
1239 #endif
1240 default:
1241 return;
1242 }
1243
1244 pint_val = bank * NR_PINT_BITS;
1245
1246 request = pint[bank]->request;
1247
1248 level_mask = pint[bank]->edge_set & request;
1249
1250 while (request) {
1251 if (request & 1) {
1252 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1253 if (level_mask & PINT_BIT(pint_val)) {
1254 umask = 1;
1255 chip->irq_unmask(&desc->irq_data);
1256 }
1257 bfin_handle_irq(irq);
1258 }
1259 pint_val++;
1260 request >>= 1;
1261 }
1262
1263 if (!umask)
1264 chip->irq_unmask(&desc->irq_data);
1265 }
1266 #endif
1267
1268 static struct irq_chip bfin_gpio_irqchip = {
1269 .name = "GPIO",
1270 .irq_ack = bfin_gpio_ack_irq,
1271 .irq_mask = bfin_gpio_mask_irq,
1272 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1273 .irq_unmask = bfin_gpio_unmask_irq,
1274 .irq_disable = bfin_gpio_mask_irq,
1275 .irq_enable = bfin_gpio_unmask_irq,
1276 .irq_set_type = bfin_gpio_irq_type,
1277 .irq_startup = bfin_gpio_irq_startup,
1278 .irq_shutdown = bfin_gpio_irq_shutdown,
1279 .irq_set_wake = bfin_gpio_set_wake,
1280 };
1281
1282 void __cpuinit init_exception_vectors(void)
1283 {
1284 /* cannot program in software:
1285 * evt0 - emulation (jtag)
1286 * evt1 - reset
1287 */
1288 bfin_write_EVT2(evt_nmi);
1289 bfin_write_EVT3(trap);
1290 bfin_write_EVT5(evt_ivhw);
1291 bfin_write_EVT6(evt_timer);
1292 bfin_write_EVT7(evt_evt7);
1293 bfin_write_EVT8(evt_evt8);
1294 bfin_write_EVT9(evt_evt9);
1295 bfin_write_EVT10(evt_evt10);
1296 bfin_write_EVT11(evt_evt11);
1297 bfin_write_EVT12(evt_evt12);
1298 bfin_write_EVT13(evt_evt13);
1299 bfin_write_EVT14(evt_evt14);
1300 bfin_write_EVT15(evt_system_call);
1301 CSYNC();
1302 }
1303
1304 #ifndef SEC_GCTL
1305 /*
1306 * This function should be called during kernel startup to initialize
1307 * the BFin IRQ handling routines.
1308 */
1309
1310 int __init init_arch_irq(void)
1311 {
1312 int irq;
1313 unsigned long ilat = 0;
1314
1315 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1316 #ifdef SIC_IMASK0
1317 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1318 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1319 # ifdef SIC_IMASK2
1320 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1321 # endif
1322 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1323 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1324 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1325 # endif
1326 #else
1327 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1328 #endif
1329
1330 local_irq_disable();
1331
1332 #if BFIN_GPIO_PINT
1333 # ifdef CONFIG_PINTx_REASSIGN
1334 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1335 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1336 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1337 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1338 # endif
1339 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1340 init_pint_lut();
1341 #endif
1342
1343 for (irq = 0; irq <= SYS_IRQS; irq++) {
1344 if (irq <= IRQ_CORETMR)
1345 irq_set_chip(irq, &bfin_core_irqchip);
1346 else
1347 irq_set_chip(irq, &bfin_internal_irqchip);
1348
1349 switch (irq) {
1350 #if BFIN_GPIO_PINT
1351 case IRQ_PINT0:
1352 case IRQ_PINT1:
1353 case IRQ_PINT2:
1354 case IRQ_PINT3:
1355 #elif defined(BF537_FAMILY)
1356 case IRQ_PH_INTA_MAC_RX:
1357 case IRQ_PF_INTA_PG_INTA:
1358 #elif defined(BF533_FAMILY)
1359 case IRQ_PROG_INTA:
1360 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1361 case IRQ_PORTF_INTA:
1362 case IRQ_PORTG_INTA:
1363 case IRQ_PORTH_INTA:
1364 #elif defined(CONFIG_BF561)
1365 case IRQ_PROG0_INTA:
1366 case IRQ_PROG1_INTA:
1367 case IRQ_PROG2_INTA:
1368 #elif defined(BF538_FAMILY)
1369 case IRQ_PORTF_INTA:
1370 #endif
1371 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1372 break;
1373 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1374 case IRQ_MAC_ERROR:
1375 irq_set_chained_handler(irq,
1376 bfin_demux_mac_status_irq);
1377 break;
1378 #endif
1379 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1380 case IRQ_SUPPLE_0:
1381 case IRQ_SUPPLE_1:
1382 irq_set_handler(irq, handle_percpu_irq);
1383 break;
1384 #endif
1385
1386 #ifdef CONFIG_TICKSOURCE_CORETMR
1387 case IRQ_CORETMR:
1388 # ifdef CONFIG_SMP
1389 irq_set_handler(irq, handle_percpu_irq);
1390 # else
1391 irq_set_handler(irq, handle_simple_irq);
1392 # endif
1393 break;
1394 #endif
1395
1396 #ifdef CONFIG_TICKSOURCE_GPTMR0
1397 case IRQ_TIMER0:
1398 irq_set_handler(irq, handle_simple_irq);
1399 break;
1400 #endif
1401
1402 default:
1403 #ifdef CONFIG_IPIPE
1404 irq_set_handler(irq, handle_level_irq);
1405 #else
1406 irq_set_handler(irq, handle_simple_irq);
1407 #endif
1408 break;
1409 }
1410 }
1411
1412 init_mach_irq();
1413
1414 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1415 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1416 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1417 handle_level_irq);
1418 #endif
1419 /* if configured as edge, then will be changed to do_edge_IRQ */
1420 for (irq = GPIO_IRQ_BASE;
1421 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1422 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1423 handle_level_irq);
1424 bfin_write_IMASK(0);
1425 CSYNC();
1426 ilat = bfin_read_ILAT();
1427 CSYNC();
1428 bfin_write_ILAT(ilat);
1429 CSYNC();
1430
1431 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1432 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1433 * local_irq_enable()
1434 */
1435 program_IAR();
1436 /* Therefore it's better to setup IARs before interrupts enabled */
1437 search_IAR();
1438
1439 /* Enable interrupts IVG7-15 */
1440 bfin_irq_flags |= IMASK_IVG15 |
1441 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1442 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1443
1444
1445 /* This implicitly covers ANOMALY_05000171
1446 * Boot-ROM code modifies SICA_IWRx wakeup registers
1447 */
1448 #ifdef SIC_IWR0
1449 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1450 # ifdef SIC_IWR1
1451 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1452 * will screw up the bootrom as it relies on MDMA0/1 waking it
1453 * up from IDLE instructions. See this report for more info:
1454 * http://blackfin.uclinux.org/gf/tracker/4323
1455 */
1456 if (ANOMALY_05000435)
1457 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1458 else
1459 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1460 # endif
1461 # ifdef SIC_IWR2
1462 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1463 # endif
1464 #else
1465 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1466 #endif
1467 return 0;
1468 }
1469
1470 #ifdef CONFIG_DO_IRQ_L1
1471 __attribute__((l1_text))
1472 #endif
1473 static int vec_to_irq(int vec)
1474 {
1475 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1476 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1477 unsigned long sic_status[3];
1478 if (likely(vec == EVT_IVTMR_P))
1479 return IRQ_CORETMR;
1480 #ifdef SIC_ISR
1481 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1482 #else
1483 if (smp_processor_id()) {
1484 # ifdef SICB_ISR0
1485 /* This will be optimized out in UP mode. */
1486 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1487 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1488 # endif
1489 } else {
1490 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1491 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1492 }
1493 #endif
1494 #ifdef SIC_ISR2
1495 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1496 #endif
1497
1498 for (;; ivg++) {
1499 if (ivg >= ivg_stop)
1500 return -1;
1501 #ifdef SIC_ISR
1502 if (sic_status[0] & ivg->isrflag)
1503 #else
1504 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1505 #endif
1506 return ivg->irqno;
1507 }
1508 }
1509
1510 #else /* SEC_GCTL */
1511
1512 /*
1513 * This function should be called during kernel startup to initialize
1514 * the BFin IRQ handling routines.
1515 */
1516
1517 int __init init_arch_irq(void)
1518 {
1519 int irq;
1520 unsigned long ilat = 0;
1521
1522 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1523
1524 local_irq_disable();
1525
1526 #if BFIN_GPIO_PINT
1527 # ifdef CONFIG_PINTx_REASSIGN
1528 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1529 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1530 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1531 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1532 pint[4]->assign = CONFIG_PINT4_ASSIGN;
1533 pint[5]->assign = CONFIG_PINT5_ASSIGN;
1534 # endif
1535 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1536 init_pint_lut();
1537 #endif
1538
1539 for (irq = 0; irq <= SYS_IRQS; irq++) {
1540 if (irq <= IRQ_CORETMR) {
1541 irq_set_chip(irq, &bfin_core_irqchip);
1542 #ifdef CONFIG_TICKSOURCE_CORETMR
1543 if (irq == IRQ_CORETMR)
1544 # ifdef CONFIG_SMP
1545 irq_set_handler(irq, handle_percpu_irq);
1546 # else
1547 irq_set_handler(irq, handle_simple_irq);
1548 # endif
1549 #endif
1550 } else if (irq < BFIN_IRQ(0)) {
1551 irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
1552 handle_simple_irq);
1553 } else if (irq == IRQ_SEC_ERR) {
1554 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1555 handle_sec_fault);
1556 } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) {
1557 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1558 handle_core_fault);
1559 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1560 irq_set_chip(irq, &bfin_sec_irqchip);
1561 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1562 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1563 irq_set_chip(irq, &bfin_sec_irqchip);
1564 irq_set_handler(irq, handle_percpu_irq);
1565 } else {
1566 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1567 handle_fasteoi_irq);
1568 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1569 }
1570 }
1571 for (irq = GPIO_IRQ_BASE;
1572 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1573 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1574 handle_level_irq);
1575
1576 bfin_write_IMASK(0);
1577 CSYNC();
1578 ilat = bfin_read_ILAT();
1579 CSYNC();
1580 bfin_write_ILAT(ilat);
1581 CSYNC();
1582
1583 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1584
1585 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1586
1587 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1588
1589 /* Enable interrupts IVG7-15 */
1590 bfin_irq_flags |= IMASK_IVG15 |
1591 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1592 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1593
1594
1595 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1596 bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1597 bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1598 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1599 udelay(100);
1600 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1601 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1602 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1603
1604 init_software_driven_irq();
1605 register_syscore_ops(&sec_pm_syscore_ops);
1606
1607 return 0;
1608 }
1609
1610 #ifdef CONFIG_DO_IRQ_L1
1611 __attribute__((l1_text))
1612 #endif
1613 static int vec_to_irq(int vec)
1614 {
1615 if (likely(vec == EVT_IVTMR_P))
1616 return IRQ_CORETMR;
1617
1618 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1619 }
1620 #endif /* SEC_GCTL */
1621
1622 #ifdef CONFIG_DO_IRQ_L1
1623 __attribute__((l1_text))
1624 #endif
1625 void do_irq(int vec, struct pt_regs *fp)
1626 {
1627 int irq = vec_to_irq(vec);
1628 if (irq == -1)
1629 return;
1630 asm_do_IRQ(irq, fp);
1631 }
1632
1633 #ifdef CONFIG_IPIPE
1634
1635 int __ipipe_get_irq_priority(unsigned irq)
1636 {
1637 int ient, prio;
1638
1639 if (irq <= IRQ_CORETMR)
1640 return irq;
1641
1642 #ifdef SEC_GCTL
1643 if (irq >= BFIN_IRQ(0))
1644 return IVG11;
1645 #else
1646 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1647 struct ivgx *ivg = ivg_table + ient;
1648 if (ivg->irqno == irq) {
1649 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1650 if (ivg7_13[prio].ifirst <= ivg &&
1651 ivg7_13[prio].istop > ivg)
1652 return IVG7 + prio;
1653 }
1654 }
1655 }
1656 #endif
1657
1658 return IVG15;
1659 }
1660
1661 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1662 #ifdef CONFIG_DO_IRQ_L1
1663 __attribute__((l1_text))
1664 #endif
1665 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1666 {
1667 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1668 struct ipipe_domain *this_domain = __ipipe_current_domain;
1669 int irq, s = 0;
1670
1671 irq = vec_to_irq(vec);
1672 if (irq == -1)
1673 return 0;
1674
1675 if (irq == IRQ_SYSTMR) {
1676 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1677 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1678 #endif
1679 /* This is basically what we need from the register frame. */
1680 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1681 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1682 if (this_domain != ipipe_root_domain)
1683 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1684 else
1685 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1686 }
1687
1688 /*
1689 * We don't want Linux interrupt handlers to run at the
1690 * current core priority level (i.e. < EVT15), since this
1691 * might delay other interrupts handled by a high priority
1692 * domain. Here is what we do instead:
1693 *
1694 * - we raise the SYNCDEFER bit to prevent
1695 * __ipipe_handle_irq() to sync the pipeline for the root
1696 * stage for the incoming interrupt. Upon return, that IRQ is
1697 * pending in the interrupt log.
1698 *
1699 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1700 * that _schedule_and_signal_from_int will eventually sync the
1701 * pipeline from EVT15.
1702 */
1703 if (this_domain == ipipe_root_domain) {
1704 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1705 barrier();
1706 }
1707
1708 ipipe_trace_irq_entry(irq);
1709 __ipipe_handle_irq(irq, regs);
1710 ipipe_trace_irq_exit(irq);
1711
1712 if (user_mode(regs) &&
1713 !ipipe_test_foreign_stack() &&
1714 (current->ipipe_flags & PF_EVTRET) != 0) {
1715 /*
1716 * Testing for user_regs() does NOT fully eliminate
1717 * foreign stack contexts, because of the forged
1718 * interrupt returns we do through
1719 * __ipipe_call_irqtail. In that case, we might have
1720 * preempted a foreign stack context in a high
1721 * priority domain, with a single interrupt level now
1722 * pending after the irqtail unwinding is done. In
1723 * which case user_mode() is now true, and the event
1724 * gets dispatched spuriously.
1725 */
1726 current->ipipe_flags &= ~PF_EVTRET;
1727 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1728 }
1729
1730 if (this_domain == ipipe_root_domain) {
1731 set_thread_flag(TIF_IRQ_SYNC);
1732 if (!s) {
1733 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1734 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1735 }
1736 }
1737
1738 return 0;
1739 }
1740
1741 #endif /* CONFIG_IPIPE */
Linux kernel - Deliverables
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