arch/cris/arch-v32/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v32/kernel/time.c
   3  *
   4  *  Copyright (C) 2003-2010 Axis Communications AB
   5  *
   6  */
   7
   8 #include <linux/timex.h>
   9 #include <linux/time.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/swap.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/threads.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/mm.h>
  18 #include <asm/types.h>
  19 #include <asm/signal.h>
  20 #include <asm/io.h>
  21 #include <asm/delay.h>
  22 #include <asm/irq.h>
  23 #include <asm/irq_regs.h>
  24
  25 #include <hwregs/reg_map.h>
  26 #include <hwregs/reg_rdwr.h>
  27 #include <hwregs/timer_defs.h>
  28 #include <hwregs/intr_vect_defs.h>
  29 #ifdef CONFIG_CRIS_MACH_ARTPEC3
  30 #include <hwregs/clkgen_defs.h>
  31 #endif
  32
  33 /* Watchdog defines */
  34 #define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
  35 #define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
  36 /* Number of 763 counts before watchdog bites */
  37 #define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
  38
  39 /* Register the continuos readonly timer available in FS and ARTPEC-3.  */
  40 static cycle_t read_cont_rotime(struct clocksource *cs)
  41 {
  42         return (u32)REG_RD(timer, regi_timer0, r_time);
  43 }
  44
  45 static struct clocksource cont_rotime = {
  46         .name   = "crisv32_rotime",
  47         .rating = 300,
  48         .read   = read_cont_rotime,
  49         .mask   = CLOCKSOURCE_MASK(32),
  50         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
  51 };
  52
  53 static int __init etrax_init_cont_rotime(void)
  54 {
  55         clocksource_register_khz(&cont_rotime, 100000);
  56         return 0;
  57 }
  58 arch_initcall(etrax_init_cont_rotime);
  59
  60 unsigned long timer_regs[NR_CPUS] =
  61 {
  62         regi_timer0,
  63 #ifdef CONFIG_SMP
  64         regi_timer2
  65 #endif
  66 };
  67
  68 extern int set_rtc_mmss(unsigned long nowtime);
  69
  70 #ifdef CONFIG_CPU_FREQ
  71 static int cris_time_freq_notifier(struct notifier_block *nb,
  72                                    unsigned long val, void *data);
  73
  74 static struct notifier_block cris_time_freq_notifier_block = {
  75         .notifier_call = cris_time_freq_notifier,
  76 };
  77 #endif
  78
  79 unsigned long get_ns_in_jiffie(void)
  80 {
  81         reg_timer_r_tmr0_data data;
  82         unsigned long ns;
  83
  84         data = REG_RD(timer, regi_timer0, r_tmr0_data);
  85         ns = (TIMER0_DIV - data) * 10;
  86         return ns;
  87 }
  88
  89 /* From timer MDS describing the hardware watchdog:
  90  * 4.3.1 Watchdog Operation
  91  * The watchdog timer is an 8-bit timer with a configurable start value.
  92  * Once started the watchdog counts downwards with a frequency of 763 Hz
  93  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
  94  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
  95  * chip.
  96  */
  97 /* This gives us 1.3 ms to do something useful when the NMI comes */
  98
  99 /* Right now, starting the watchdog is the same as resetting it */
 100 #define start_watchdog reset_watchdog
 101
 102 #if defined(CONFIG_ETRAX_WATCHDOG)
 103 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 104 #endif
 105
 106 /* Number of pages to consider "out of memory". It is normal that the memory
 107  * is used though, so set this really low. */
 108 #define WATCHDOG_MIN_FREE_PAGES 8
 109
 110 /* for reliable NICE_DOGGY behaviour */
 111 static int bite_in_progress;
 112
 113 void reset_watchdog(void)
 114 {
 115 #if defined(CONFIG_ETRAX_WATCHDOG)
 116         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 117
 118 #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
 119         if (unlikely(bite_in_progress))
 120                 return;
 121 #endif
 122         /* Only keep watchdog happy as long as we have memory left! */
 123         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 124                 /* Reset the watchdog with the inverse of the old key */
 125                 /* Invert key, which is 7 bits */
 126                 watchdog_key ^= ETRAX_WD_KEY_MASK;
 127                 wd_ctrl.cnt = ETRAX_WD_CNT;
 128                 wd_ctrl.cmd = regk_timer_start;
 129                 wd_ctrl.key = watchdog_key;
 130                 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 131         }
 132 #endif
 133 }
 134
 135 /* stop the watchdog - we still need the correct key */
 136
 137 void stop_watchdog(void)
 138 {
 139 #if defined(CONFIG_ETRAX_WATCHDOG)
 140         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 141         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 142         wd_ctrl.cnt = ETRAX_WD_CNT;
 143         wd_ctrl.cmd = regk_timer_stop;
 144         wd_ctrl.key = watchdog_key;
 145         REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 146 #endif
 147 }
 148
 149 extern void show_registers(struct pt_regs *regs);
 150
 151 void handle_watchdog_bite(struct pt_regs *regs)
 152 {
 153 #if defined(CONFIG_ETRAX_WATCHDOG)
 154         extern int cause_of_death;
 155
 156         nmi_enter();
 157         oops_in_progress = 1;
 158         bite_in_progress = 1;
 159         printk(KERN_WARNING "Watchdog bite\n");
 160
 161         /* Check if forced restart or unexpected watchdog */
 162         if (cause_of_death == 0xbedead) {
 163 #ifdef CONFIG_CRIS_MACH_ARTPEC3
 164                 /* There is a bug in Artpec-3 (voodoo TR 78) that requires
 165                  * us to go to lower frequency for the reset to be reliable
 166                  */
 167                 reg_clkgen_rw_clk_ctrl ctrl =
 168                         REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
 169                 ctrl.pll = 0;
 170                 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
 171 #endif
 172                 while(1);
 173         }
 174
 175         /* Unexpected watchdog, stop the watchdog and dump registers. */
 176         stop_watchdog();
 177         printk(KERN_WARNING "Oops: bitten by watchdog\n");
 178         show_registers(regs);
 179         oops_in_progress = 0;
 180         printk("\n"); /* Flush mtdoops.  */
 181 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
 182         reset_watchdog();
 183 #endif
 184         while(1) /* nothing */;
 185 #endif
 186 }
 187
 188 /*
 189  * timer_interrupt() needs to keep up the real-time clock,
 190  * as well as call the "xtime_update()" routine every clocktick.
 191  */
 192 extern void cris_do_profile(struct pt_regs *regs);
 193
 194 static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
 195 {
 196         struct pt_regs *regs = get_irq_regs();
 197         int cpu = smp_processor_id();
 198         reg_timer_r_masked_intr masked_intr;
 199         reg_timer_rw_ack_intr ack_intr = { 0 };
 200
 201         /* Check if the timer interrupt is for us (a tmr0 int) */
 202         masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
 203         if (!masked_intr.tmr0)
 204                 return IRQ_NONE;
 205
 206         /* Acknowledge the timer irq. */
 207         ack_intr.tmr0 = 1;
 208         REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
 209
 210         /* Reset watchdog otherwise it resets us! */
 211         reset_watchdog();
 212
 213         /* Update statistics. */
 214         update_process_times(user_mode(regs));
 215
 216         cris_do_profile(regs); /* Save profiling information */
 217
 218         /* The master CPU is responsible for the time keeping. */
 219         if (cpu != 0)
 220                 return IRQ_HANDLED;
 221
 222         /* Call the real timer interrupt handler */
 223         xtime_update(1);
 224         return IRQ_HANDLED;
 225 }
 226
 227 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
 228 static struct irqaction irq_timer = {
 229         .handler = timer_interrupt,
 230         .flags = IRQF_SHARED,
 231         .name = "timer"
 232 };
 233
 234 void __init cris_timer_init(void)
 235 {
 236         int cpu = smp_processor_id();
 237         reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
 238         reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
 239         reg_timer_rw_intr_mask timer_intr_mask;
 240
 241         /* Setup the etrax timers.
 242          * Base frequency is 100MHz, divider 1000000 -> 100 HZ
 243          * We use timer0, so timer1 is free.
 244          * The trig timer is used by the fasttimer API if enabled.
 245          */
 246
 247         tmr0_ctrl.op = regk_timer_ld;
 248         tmr0_ctrl.freq = regk_timer_f100;
 249         REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
 250         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
 251         tmr0_ctrl.op = regk_timer_run;
 252         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
 253
 254         /* Enable the timer irq. */
 255         timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
 256         timer_intr_mask.tmr0 = 1;
 257         REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
 258 }
 259
 260 void __init time_init(void)
 261 {
 262         reg_intr_vect_rw_mask intr_mask;
 263
 264         /* Probe for the RTC and read it if it exists.
 265          * Before the RTC can be probed the loops_per_usec variable needs
 266          * to be initialized to make usleep work. A better value for
 267          * loops_per_usec is calculated by the kernel later once the
 268          * clock has started.
 269          */
 270         loops_per_usec = 50;
 271
 272         /* Start CPU local timer. */
 273         cris_timer_init();
 274
 275         /* Enable the timer irq in global config. */
 276         intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
 277         intr_mask.timer0 = 1;
 278         REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
 279
 280         /* Now actually register the timer irq handler that calls
 281          * timer_interrupt(). */
 282         setup_irq(TIMER0_INTR_VECT, &irq_timer);
 283
 284         /* Enable watchdog if we should use one. */
 285
 286 #if defined(CONFIG_ETRAX_WATCHDOG)
 287         printk(KERN_INFO "Enabling watchdog...\n");
 288         start_watchdog();
 289
 290         /* If we use the hardware watchdog, we want to trap it as an NMI
 291          * and dump registers before it resets us.  For this to happen, we
 292          * must set the "m" NMI enable flag (which once set, is unset only
 293          * when an NMI is taken). */
 294         {
 295                 unsigned long flags;
 296                 local_save_flags(flags);
 297                 flags |= (1<<30); /* NMI M flag is at bit 30 */
 298                 local_irq_restore(flags);
 299         }
 300 #endif
 301
 302 #ifdef CONFIG_CPU_FREQ
 303         cpufreq_register_notifier(&cris_time_freq_notifier_block,
 304                                   CPUFREQ_TRANSITION_NOTIFIER);
 305 #endif
 306 }
 307
 308 #ifdef CONFIG_CPU_FREQ
 309 static int cris_time_freq_notifier(struct notifier_block *nb,
 310                                    unsigned long val, void *data)
 311 {
 312         struct cpufreq_freqs *freqs = data;
 313         if (val == CPUFREQ_POSTCHANGE) {
 314                 reg_timer_r_tmr0_data data;
 315                 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
 316                 do {
 317                         data = REG_RD(timer, timer_regs[freqs->cpu],
 318                                 r_tmr0_data);
 319                 } while (data > 20);
 320                 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
 321         }
 322         return 0;
 323 }
 324 #endif