arch/h8300/platform/h8s/generic/crt0_rom.S

   1 /*
   2  *  linux/arch/h8300/platform/h8s/generic/crt0_rom.S
   3  *
   4  *  Yoshinori Sato <ysato@users.sourceforge.jp>
   5  *
   6  *  Platform depend startup
   7  *  Target Archtecture: generic
   8  *  Memory Layout     : ROM
   9  */
  10
  11 #define ASSEMBLY
  12
  13 #include <asm/linkage.h>
  14 #include <asm/regs267x.h>
  15
  16         .global __start
  17         .global __command_line
  18         .global __platform_gpio_table
  19         .global __target_name
  20
  21         .h8300s
  22         .section .text
  23         .file   "crt0_rom.S"
  24
  25         /* CPU Reset entry */
  26 __start:
  27         mov.l   #__ramend,sp
  28         ldc     #0x80,ccr
  29         ldc     #0,exr
  30         bclr    #4,@INTCR:8
  31         bset    #5,@INTCR:8     /* Interrupt mode 2 */
  32
  33         /* Peripheral Setup */
  34
  35         /* copy .data */
  36 #if !defined(CONFIG_H8S_SIM)
  37         mov.l   #__begin_data,er5
  38         mov.l   #__sdata,er6
  39         mov.l   #__edata,er4
  40         sub.l   er6,er4
  41         shlr.l  #2,er4
  42 1:
  43         mov.l   @er5+,er0
  44         mov.l   er0,@er6
  45         adds    #4,er6
  46         dec.l   #1,er4
  47         bne     1b
  48 #endif
  49
  50         /* .bss clear */
  51         mov.l   #__sbss,er5
  52         mov.l   #__ebss,er4
  53         sub.l   er5,er4
  54         shlr.l  #2,er4
  55         sub.l   er0,er0
  56 1:
  57         mov.l   er0,@er5
  58         adds    #4,er5
  59         dec.l   #1,er4
  60         bne     1b
  61
  62         /* linux kernel start */
  63         ldc     #0x90,ccr       /* running kernel */
  64         mov.l   #_init_thread_union,sp
  65         add.l   #0x2000,sp
  66         jsr     @_start_kernel
  67 _exit:
  68
  69         jmp     _exit
  70
  71         rts
  72
  73         /* I/O port assign information */
  74 __platform_gpio_table:
  75         mov.l   #gpio_table,er0
  76         rts
  77
  78 gpio_table:
  79         ;; P1DDR
  80         .byte   0x00,0x00
  81         ;; P2DDR
  82         .byte   0x00,0x00
  83         ;; P3DDR
  84         .byte   0x00,0x00
  85         ;; P4DDR
  86         .byte   0x00,0x00
  87         ;; P5DDR
  88         .byte   0x00,0x00
  89         ;; P6DDR
  90         .byte   0x00,0x00
  91         ;; dummy
  92         .byte   0x00,0x00
  93         ;; P8DDR
  94         .byte   0x00,0x00
  95         ;; PADDR
  96         .byte   0x00,0x00
  97         ;; PBDDR
  98         .byte   0x00,0x00
  99         ;; PCDDR
 100         .byte   0x00,0x00
 101         ;; PDDDR
 102         .byte   0x00,0x00
 103         ;; PEDDR
 104         .byte   0x00,0x00
 105         ;; PFDDR
 106         .byte   0x00,0x00
 107         ;; PGDDR
 108         .byte   0x00,0x00
 109         ;; PHDDR
 110         .byte   0x00,0x00
 111
 112         .section .rodata
 113 __target_name:
 114         .asciz  "generic"
 115
 116         .section .bss
 117 __command_line:
 118         .space  512
 119
 120         /* interrupt vector */
 121         .section .vectors,"ax"
 122         .long   __start
 123         .long   __start
 124 vector  =       2
 125         .rept   126-1
 126         .long   _interrupt_redirect_table+vector*4
 127 vector  =       vector + 1
 128         .endr