2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/sysdev.h>
39 #include <asm/timer.h>
41 #include <mach_apic.h>
45 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
46 atomic_t irq_mis_count
;
48 static DEFINE_SPINLOCK(ioapic_lock
);
51 * Is the SiS APIC rmw bug present ?
52 * -1 = don't know, 0 = no, 1 = yes
54 int sis_apic_bug
= -1;
57 * # of IRQ routing registers
59 int nr_ioapic_registers
[MAX_IO_APICS
];
62 * Rough estimation of how many shared IRQs there are, can
65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
69 * This is performance-critical, we want to do it O(1)
71 * the indexing order of this array favors 1:1 mappings
72 * between pins and IRQs.
75 static struct irq_pin_list
{
77 } irq_2_pin
[PIN_MAP_SIZE
];
79 int vector_irq
[NR_VECTORS
] = { [0 ... NR_VECTORS
- 1] = -1};
81 #define vector_to_irq(vector) \
82 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
84 #define vector_to_irq(vector) (vector)
88 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
89 * shared ISA-space IRQs, so we have to support them. We are super
90 * fast in the common case, and fast for shared ISA-space IRQs.
92 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
94 static int first_free_entry
= NR_IRQS
;
95 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
98 entry
= irq_2_pin
+ entry
->next
;
100 if (entry
->pin
!= -1) {
101 entry
->next
= first_free_entry
;
102 entry
= irq_2_pin
+ entry
->next
;
103 if (++first_free_entry
>= PIN_MAP_SIZE
)
104 panic("io_apic.c: whoops");
111 * Reroute an IRQ to a different pin.
113 static void __init
replace_pin_at_irq(unsigned int irq
,
114 int oldapic
, int oldpin
,
115 int newapic
, int newpin
)
117 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
120 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
121 entry
->apic
= newapic
;
126 entry
= irq_2_pin
+ entry
->next
;
130 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
132 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
133 unsigned int pin
, reg
;
139 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
142 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
145 entry
= irq_2_pin
+ entry
->next
;
150 static void __mask_IO_APIC_irq (unsigned int irq
)
152 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
156 static void __unmask_IO_APIC_irq (unsigned int irq
)
158 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
161 /* mask = 1, trigger = 0 */
162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
164 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
167 /* mask = 0, trigger = 1 */
168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
170 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
173 static void mask_IO_APIC_irq (unsigned int irq
)
177 spin_lock_irqsave(&ioapic_lock
, flags
);
178 __mask_IO_APIC_irq(irq
);
179 spin_unlock_irqrestore(&ioapic_lock
, flags
);
182 static void unmask_IO_APIC_irq (unsigned int irq
)
186 spin_lock_irqsave(&ioapic_lock
, flags
);
187 __unmask_IO_APIC_irq(irq
);
188 spin_unlock_irqrestore(&ioapic_lock
, flags
);
191 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
193 struct IO_APIC_route_entry entry
;
196 /* Check delivery_mode to be sure we're not clearing an SMI pin */
197 spin_lock_irqsave(&ioapic_lock
, flags
);
198 *(((int*)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
199 *(((int*)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
200 spin_unlock_irqrestore(&ioapic_lock
, flags
);
201 if (entry
.delivery_mode
== dest_SMI
)
205 * Disable it in the IO-APIC irq-routing table:
207 memset(&entry
, 0, sizeof(entry
));
209 spin_lock_irqsave(&ioapic_lock
, flags
);
210 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
211 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
212 spin_unlock_irqrestore(&ioapic_lock
, flags
);
215 static void clear_IO_APIC (void)
219 for (apic
= 0; apic
< nr_ioapics
; apic
++)
220 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
221 clear_IO_APIC_pin(apic
, pin
);
224 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
228 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
229 unsigned int apicid_value
;
231 apicid_value
= cpu_mask_to_apicid(cpumask
);
232 /* Prepare to do the io_apic_write */
233 apicid_value
= apicid_value
<< 24;
234 spin_lock_irqsave(&ioapic_lock
, flags
);
239 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
242 entry
= irq_2_pin
+ entry
->next
;
244 spin_unlock_irqrestore(&ioapic_lock
, flags
);
247 #if defined(CONFIG_IRQBALANCE)
248 # include <asm/processor.h> /* kernel_thread() */
249 # include <linux/kernel_stat.h> /* kstat */
250 # include <linux/slab.h> /* kmalloc() */
251 # include <linux/timer.h> /* time_after() */
253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
254 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
255 # define Dprintk(x...) do { TDprintk(x); } while (0)
257 # define TDprintk(x...)
258 # define Dprintk(x...)
261 cpumask_t __cacheline_aligned pending_irq_balance_cpumask
[NR_IRQS
];
263 #define IRQBALANCE_CHECK_ARCH -999
264 static int irqbalance_disabled
= IRQBALANCE_CHECK_ARCH
;
265 static int physical_balance
= 0;
267 static struct irq_cpu_info
{
268 unsigned long * last_irq
;
269 unsigned long * irq_delta
;
271 } irq_cpu_data
[NR_CPUS
];
273 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
274 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
275 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
277 #define IDLE_ENOUGH(cpu,now) \
278 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
280 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
282 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
284 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
285 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
286 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
287 #define BALANCED_IRQ_LESS_DELTA (HZ)
289 static long balanced_irq_interval
= MAX_BALANCED_IRQ_INTERVAL
;
291 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
292 unsigned long now
, int direction
)
300 if (unlikely(cpu
== curr_cpu
))
303 if (direction
== 1) {
312 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
313 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
318 static inline void balance_irq(int cpu
, int irq
)
320 unsigned long now
= jiffies
;
321 cpumask_t allowed_mask
;
322 unsigned int new_cpu
;
324 if (irqbalance_disabled
)
327 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[irq
]);
328 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
329 if (cpu
!= new_cpu
) {
330 irq_desc_t
*desc
= irq_desc
+ irq
;
333 spin_lock_irqsave(&desc
->lock
, flags
);
334 pending_irq_balance_cpumask
[irq
] = cpumask_of_cpu(new_cpu
);
335 spin_unlock_irqrestore(&desc
->lock
, flags
);
339 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
342 Dprintk("Rotating IRQs among CPUs.\n");
343 for (i
= 0; i
< NR_CPUS
; i
++) {
344 for (j
= 0; cpu_online(i
) && (j
< NR_IRQS
); j
++) {
345 if (!irq_desc
[j
].action
)
347 /* Is it a significant load ? */
348 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
349 useful_load_threshold
)
354 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
355 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
359 static void do_irq_balance(void)
362 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
363 unsigned long move_this_load
= 0;
364 int max_loaded
= 0, min_loaded
= 0;
366 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
368 int tmp_loaded
, first_attempt
= 1;
369 unsigned long tmp_cpu_irq
;
370 unsigned long imbalance
= 0;
371 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
373 for (i
= 0; i
< NR_CPUS
; i
++) {
378 package_index
= CPU_TO_PACKAGEINDEX(i
);
379 for (j
= 0; j
< NR_IRQS
; j
++) {
380 unsigned long value_now
, delta
;
381 /* Is this an active IRQ? */
382 if (!irq_desc
[j
].action
)
384 if ( package_index
== i
)
385 IRQ_DELTA(package_index
,j
) = 0;
386 /* Determine the total count per processor per IRQ */
387 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
389 /* Determine the activity per processor per IRQ */
390 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
392 /* Update last_cpu_irq[][] for the next time */
393 LAST_CPU_IRQ(i
,j
) = value_now
;
395 /* Ignore IRQs whose rate is less than the clock */
396 if (delta
< useful_load_threshold
)
398 /* update the load for the processor or package total */
399 IRQ_DELTA(package_index
,j
) += delta
;
401 /* Keep track of the higher numbered sibling as well */
402 if (i
!= package_index
)
405 * We have sibling A and sibling B in the package
407 * cpu_irq[A] = load for cpu A + load for cpu B
408 * cpu_irq[B] = load for cpu B
410 CPU_IRQ(package_index
) += delta
;
413 /* Find the least loaded processor package */
414 for (i
= 0; i
< NR_CPUS
; i
++) {
417 if (i
!= CPU_TO_PACKAGEINDEX(i
))
419 if (min_cpu_irq
> CPU_IRQ(i
)) {
420 min_cpu_irq
= CPU_IRQ(i
);
424 max_cpu_irq
= ULONG_MAX
;
427 /* Look for heaviest loaded processor.
428 * We may come back to get the next heaviest loaded processor.
429 * Skip processors with trivial loads.
433 for (i
= 0; i
< NR_CPUS
; i
++) {
436 if (i
!= CPU_TO_PACKAGEINDEX(i
))
438 if (max_cpu_irq
<= CPU_IRQ(i
))
440 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
441 tmp_cpu_irq
= CPU_IRQ(i
);
446 if (tmp_loaded
== -1) {
447 /* In the case of small number of heavy interrupt sources,
448 * loading some of the cpus too much. We use Ingo's original
449 * approach to rotate them around.
451 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
452 rotate_irqs_among_cpus(useful_load_threshold
);
455 goto not_worth_the_effort
;
458 first_attempt
= 0; /* heaviest search */
459 max_cpu_irq
= tmp_cpu_irq
; /* load */
460 max_loaded
= tmp_loaded
; /* processor */
461 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
463 Dprintk("max_loaded cpu = %d\n", max_loaded
);
464 Dprintk("min_loaded cpu = %d\n", min_loaded
);
465 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
466 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
467 Dprintk("load imbalance = %lu\n", imbalance
);
469 /* if imbalance is less than approx 10% of max load, then
470 * observe diminishing returns action. - quit
472 if (imbalance
< (max_cpu_irq
>> 3)) {
473 Dprintk("Imbalance too trivial\n");
474 goto not_worth_the_effort
;
478 /* if we select an IRQ to move that can't go where we want, then
479 * see if there is another one to try.
483 for (j
= 0; j
< NR_IRQS
; j
++) {
484 /* Is this an active IRQ? */
485 if (!irq_desc
[j
].action
)
487 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
489 /* Try to find the IRQ that is closest to the imbalance
490 * without going over.
492 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
493 move_this_load
= IRQ_DELTA(max_loaded
,j
);
497 if (selected_irq
== -1) {
501 imbalance
= move_this_load
;
503 /* For physical_balance case, we accumlated both load
504 * values in the one of the siblings cpu_irq[],
505 * to use the same code for physical and logical processors
506 * as much as possible.
508 * NOTE: the cpu_irq[] array holds the sum of the load for
509 * sibling A and sibling B in the slot for the lowest numbered
510 * sibling (A), _AND_ the load for sibling B in the slot for
511 * the higher numbered sibling.
513 * We seek the least loaded sibling by making the comparison
516 load
= CPU_IRQ(min_loaded
) >> 1;
517 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
518 if (load
> CPU_IRQ(j
)) {
519 /* This won't change cpu_sibling_map[min_loaded] */
525 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[selected_irq
]);
526 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
527 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
529 if (!cpus_empty(tmp
)) {
530 irq_desc_t
*desc
= irq_desc
+ selected_irq
;
533 Dprintk("irq = %d moved to cpu = %d\n",
534 selected_irq
, min_loaded
);
535 /* mark for change destination */
536 spin_lock_irqsave(&desc
->lock
, flags
);
537 pending_irq_balance_cpumask
[selected_irq
] =
538 cpumask_of_cpu(min_loaded
);
539 spin_unlock_irqrestore(&desc
->lock
, flags
);
540 /* Since we made a change, come back sooner to
541 * check for more variation.
543 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
544 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
549 not_worth_the_effort
:
551 * if we did not find an IRQ to move, then adjust the time interval
554 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
555 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
556 Dprintk("IRQ worth rotating not found\n");
560 static int balanced_irq(void *unused
)
563 unsigned long prev_balance_time
= jiffies
;
564 long time_remaining
= balanced_irq_interval
;
568 /* push everything to CPU 0 to give us a starting point. */
569 for (i
= 0 ; i
< NR_IRQS
; i
++) {
570 pending_irq_balance_cpumask
[i
] = cpumask_of_cpu(0);
574 set_current_state(TASK_INTERRUPTIBLE
);
575 time_remaining
= schedule_timeout(time_remaining
);
576 try_to_freeze(PF_FREEZE
);
577 if (time_after(jiffies
,
578 prev_balance_time
+balanced_irq_interval
)) {
581 prev_balance_time
= jiffies
;
582 time_remaining
= balanced_irq_interval
;
589 static int __init
balanced_irq_init(void)
592 struct cpuinfo_x86
*c
;
595 cpus_shift_right(tmp
, cpu_online_map
, 2);
597 /* When not overwritten by the command line ask subarchitecture. */
598 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
599 irqbalance_disabled
= NO_BALANCE_IRQ
;
600 if (irqbalance_disabled
)
603 /* disable irqbalance completely if there is only one processor online */
604 if (num_online_cpus() < 2) {
605 irqbalance_disabled
= 1;
609 * Enable physical balance only if more than 1 physical processor
612 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
613 physical_balance
= 1;
615 for (i
= 0; i
< NR_CPUS
; i
++) {
618 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
619 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
620 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
621 printk(KERN_ERR
"balanced_irq_init: out of memory");
624 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
625 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
628 printk(KERN_INFO
"Starting balanced_irq\n");
629 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
632 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
634 for (i
= 0; i
< NR_CPUS
; i
++) {
635 if(irq_cpu_data
[i
].irq_delta
)
636 kfree(irq_cpu_data
[i
].irq_delta
);
637 if(irq_cpu_data
[i
].last_irq
)
638 kfree(irq_cpu_data
[i
].last_irq
);
643 int __init
irqbalance_disable(char *str
)
645 irqbalance_disabled
= 1;
649 __setup("noirqbalance", irqbalance_disable
);
651 static inline void move_irq(int irq
)
653 /* note - we hold the desc->lock */
654 if (unlikely(!cpus_empty(pending_irq_balance_cpumask
[irq
]))) {
655 set_ioapic_affinity_irq(irq
, pending_irq_balance_cpumask
[irq
]);
656 cpus_clear(pending_irq_balance_cpumask
[irq
]);
660 late_initcall(balanced_irq_init
);
662 #else /* !CONFIG_IRQBALANCE */
663 static inline void move_irq(int irq
) { }
664 #endif /* CONFIG_IRQBALANCE */
667 void fastcall
send_IPI_self(int vector
)
674 apic_wait_icr_idle();
675 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
677 * Send the IPI. The write to APIC_ICR fires this off.
679 apic_write_around(APIC_ICR
, cfg
);
681 #endif /* !CONFIG_SMP */
685 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
686 * specific CPU-side IRQs.
690 static int pirq_entries
[MAX_PIRQS
];
691 static int pirqs_enabled
;
692 int skip_ioapic_setup
;
694 static int __init
ioapic_setup(char *str
)
696 skip_ioapic_setup
= 1;
700 __setup("noapic", ioapic_setup
);
702 static int __init
ioapic_pirq_setup(char *str
)
705 int ints
[MAX_PIRQS
+1];
707 get_options(str
, ARRAY_SIZE(ints
), ints
);
709 for (i
= 0; i
< MAX_PIRQS
; i
++)
710 pirq_entries
[i
] = -1;
713 apic_printk(APIC_VERBOSE
, KERN_INFO
714 "PIRQ redirection, working around broken MP-BIOS.\n");
716 if (ints
[0] < MAX_PIRQS
)
719 for (i
= 0; i
< max
; i
++) {
720 apic_printk(APIC_VERBOSE
, KERN_DEBUG
721 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
723 * PIRQs are mapped upside down, usually.
725 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
730 __setup("pirq=", ioapic_pirq_setup
);
733 * Find the IRQ entry number of a certain pin.
735 static int find_irq_entry(int apic
, int pin
, int type
)
739 for (i
= 0; i
< mp_irq_entries
; i
++)
740 if (mp_irqs
[i
].mpc_irqtype
== type
&&
741 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
742 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
743 mp_irqs
[i
].mpc_dstirq
== pin
)
750 * Find the pin to which IRQ[irq] (ISA) is connected
752 static int find_isa_irq_pin(int irq
, int type
)
756 for (i
= 0; i
< mp_irq_entries
; i
++) {
757 int lbus
= mp_irqs
[i
].mpc_srcbus
;
759 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
760 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
761 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
762 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
764 (mp_irqs
[i
].mpc_irqtype
== type
) &&
765 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
767 return mp_irqs
[i
].mpc_dstirq
;
773 * Find a specific PCI IRQ entry.
774 * Not an __init, possibly needed by modules
776 static int pin_2_irq(int idx
, int apic
, int pin
);
778 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
780 int apic
, i
, best_guess
= -1;
782 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
783 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
784 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
785 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
788 for (i
= 0; i
< mp_irq_entries
; i
++) {
789 int lbus
= mp_irqs
[i
].mpc_srcbus
;
791 for (apic
= 0; apic
< nr_ioapics
; apic
++)
792 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
793 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
796 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
797 !mp_irqs
[i
].mpc_irqtype
&&
799 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
800 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
802 if (!(apic
|| IO_APIC_IRQ(irq
)))
805 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
808 * Use the first all-but-pin matching entry as a
809 * best-guess fuzzy result for broken mptables.
817 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
820 * This function currently is only a helper for the i386 smp boot process where
821 * we need to reprogram the ioredtbls to cater for the cpus which have come online
822 * so mask in all cases should simply be TARGET_CPUS
824 void __init
setup_ioapic_dest(void)
826 int pin
, ioapic
, irq
, irq_entry
;
828 if (skip_ioapic_setup
== 1)
831 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
832 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
833 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
836 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
837 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
844 * EISA Edge/Level control register, ELCR
846 static int EISA_ELCR(unsigned int irq
)
849 unsigned int port
= 0x4d0 + (irq
>> 3);
850 return (inb(port
) >> (irq
& 7)) & 1;
852 apic_printk(APIC_VERBOSE
, KERN_INFO
853 "Broken MPtable reports ISA irq %d\n", irq
);
857 /* EISA interrupts are always polarity zero and can be edge or level
858 * trigger depending on the ELCR value. If an interrupt is listed as
859 * EISA conforming in the MP table, that means its trigger type must
860 * be read in from the ELCR */
862 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
863 #define default_EISA_polarity(idx) (0)
865 /* ISA interrupts are always polarity zero edge triggered,
866 * when listed as conforming in the MP table. */
868 #define default_ISA_trigger(idx) (0)
869 #define default_ISA_polarity(idx) (0)
871 /* PCI interrupts are always polarity one level triggered,
872 * when listed as conforming in the MP table. */
874 #define default_PCI_trigger(idx) (1)
875 #define default_PCI_polarity(idx) (1)
877 /* MCA interrupts are always polarity zero level triggered,
878 * when listed as conforming in the MP table. */
880 #define default_MCA_trigger(idx) (1)
881 #define default_MCA_polarity(idx) (0)
883 /* NEC98 interrupts are always polarity zero edge triggered,
884 * when listed as conforming in the MP table. */
886 #define default_NEC98_trigger(idx) (0)
887 #define default_NEC98_polarity(idx) (0)
889 static int __init
MPBIOS_polarity(int idx
)
891 int bus
= mp_irqs
[idx
].mpc_srcbus
;
895 * Determine IRQ line polarity (high active or low active):
897 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
899 case 0: /* conforms, ie. bus-type dependent polarity */
901 switch (mp_bus_id_to_type
[bus
])
903 case MP_BUS_ISA
: /* ISA pin */
905 polarity
= default_ISA_polarity(idx
);
908 case MP_BUS_EISA
: /* EISA pin */
910 polarity
= default_EISA_polarity(idx
);
913 case MP_BUS_PCI
: /* PCI pin */
915 polarity
= default_PCI_polarity(idx
);
918 case MP_BUS_MCA
: /* MCA pin */
920 polarity
= default_MCA_polarity(idx
);
923 case MP_BUS_NEC98
: /* NEC 98 pin */
925 polarity
= default_NEC98_polarity(idx
);
930 printk(KERN_WARNING
"broken BIOS!!\n");
937 case 1: /* high active */
942 case 2: /* reserved */
944 printk(KERN_WARNING
"broken BIOS!!\n");
948 case 3: /* low active */
953 default: /* invalid */
955 printk(KERN_WARNING
"broken BIOS!!\n");
963 static int MPBIOS_trigger(int idx
)
965 int bus
= mp_irqs
[idx
].mpc_srcbus
;
969 * Determine IRQ trigger mode (edge or level sensitive):
971 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
973 case 0: /* conforms, ie. bus-type dependent */
975 switch (mp_bus_id_to_type
[bus
])
977 case MP_BUS_ISA
: /* ISA pin */
979 trigger
= default_ISA_trigger(idx
);
982 case MP_BUS_EISA
: /* EISA pin */
984 trigger
= default_EISA_trigger(idx
);
987 case MP_BUS_PCI
: /* PCI pin */
989 trigger
= default_PCI_trigger(idx
);
992 case MP_BUS_MCA
: /* MCA pin */
994 trigger
= default_MCA_trigger(idx
);
997 case MP_BUS_NEC98
: /* NEC 98 pin */
999 trigger
= default_NEC98_trigger(idx
);
1004 printk(KERN_WARNING
"broken BIOS!!\n");
1016 case 2: /* reserved */
1018 printk(KERN_WARNING
"broken BIOS!!\n");
1027 default: /* invalid */
1029 printk(KERN_WARNING
"broken BIOS!!\n");
1037 static inline int irq_polarity(int idx
)
1039 return MPBIOS_polarity(idx
);
1042 static inline int irq_trigger(int idx
)
1044 return MPBIOS_trigger(idx
);
1047 static int pin_2_irq(int idx
, int apic
, int pin
)
1050 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1053 * Debugging check, we are in big trouble if this message pops up!
1055 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1056 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1058 switch (mp_bus_id_to_type
[bus
])
1060 case MP_BUS_ISA
: /* ISA pin */
1065 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1068 case MP_BUS_PCI
: /* PCI pin */
1071 * PCI IRQs are mapped in order
1075 irq
+= nr_ioapic_registers
[i
++];
1079 * For MPS mode, so far only needed by ES7000 platform
1081 if (ioapic_renumber_irq
)
1082 irq
= ioapic_renumber_irq(apic
, irq
);
1088 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1095 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1097 if ((pin
>= 16) && (pin
<= 23)) {
1098 if (pirq_entries
[pin
-16] != -1) {
1099 if (!pirq_entries
[pin
-16]) {
1100 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1101 "disabling PIRQ%d\n", pin
-16);
1103 irq
= pirq_entries
[pin
-16];
1104 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1105 "using PIRQ%d -> IRQ %d\n",
1113 static inline int IO_APIC_irq_trigger(int irq
)
1117 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1118 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1119 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1120 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1121 return irq_trigger(idx
);
1125 * nonexistent IRQs are edge default
1130 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1131 u8 irq_vector
[NR_IRQ_VECTORS
] = { FIRST_DEVICE_VECTOR
, 0 };
1133 int assign_irq_vector(int irq
)
1135 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1137 BUG_ON(irq
>= NR_IRQ_VECTORS
);
1138 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0)
1139 return IO_APIC_VECTOR(irq
);
1141 current_vector
+= 8;
1142 if (current_vector
== SYSCALL_VECTOR
)
1145 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1149 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1152 vector_irq
[current_vector
] = irq
;
1153 if (irq
!= AUTO_ASSIGN
)
1154 IO_APIC_VECTOR(irq
) = current_vector
;
1156 return current_vector
;
1159 static struct hw_interrupt_type ioapic_level_type
;
1160 static struct hw_interrupt_type ioapic_edge_type
;
1162 #define IOAPIC_AUTO -1
1163 #define IOAPIC_EDGE 0
1164 #define IOAPIC_LEVEL 1
1166 static inline void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1168 if (use_pci_vector() && !platform_legacy_irq(irq
)) {
1169 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1170 trigger
== IOAPIC_LEVEL
)
1171 irq_desc
[vector
].handler
= &ioapic_level_type
;
1173 irq_desc
[vector
].handler
= &ioapic_edge_type
;
1174 set_intr_gate(vector
, interrupt
[vector
]);
1176 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1177 trigger
== IOAPIC_LEVEL
)
1178 irq_desc
[irq
].handler
= &ioapic_level_type
;
1180 irq_desc
[irq
].handler
= &ioapic_edge_type
;
1181 set_intr_gate(vector
, interrupt
[irq
]);
1185 static void __init
setup_IO_APIC_irqs(void)
1187 struct IO_APIC_route_entry entry
;
1188 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1189 unsigned long flags
;
1191 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1193 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1194 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1197 * add it to the IO-APIC irq-routing table:
1199 memset(&entry
,0,sizeof(entry
));
1201 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1202 entry
.dest_mode
= INT_DEST_MODE
;
1203 entry
.mask
= 0; /* enable IRQ */
1204 entry
.dest
.logical
.logical_dest
=
1205 cpu_mask_to_apicid(TARGET_CPUS
);
1207 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1210 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1211 " IO-APIC (apicid-pin) %d-%d",
1212 mp_ioapics
[apic
].mpc_apicid
,
1216 apic_printk(APIC_VERBOSE
, ", %d-%d",
1217 mp_ioapics
[apic
].mpc_apicid
, pin
);
1221 entry
.trigger
= irq_trigger(idx
);
1222 entry
.polarity
= irq_polarity(idx
);
1224 if (irq_trigger(idx
)) {
1229 irq
= pin_2_irq(idx
, apic
, pin
);
1231 * skip adding the timer int on secondary nodes, which causes
1232 * a small but painful rift in the time-space continuum
1234 if (multi_timer_check(apic
, irq
))
1237 add_pin_to_irq(irq
, apic
, pin
);
1239 if (!apic
&& !IO_APIC_IRQ(irq
))
1242 if (IO_APIC_IRQ(irq
)) {
1243 vector
= assign_irq_vector(irq
);
1244 entry
.vector
= vector
;
1245 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1247 if (!apic
&& (irq
< 16))
1248 disable_8259A_irq(irq
);
1250 spin_lock_irqsave(&ioapic_lock
, flags
);
1251 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1252 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1253 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1258 apic_printk(APIC_VERBOSE
, " not connected.\n");
1262 * Set up the 8259A-master output pin:
1264 static void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
1266 struct IO_APIC_route_entry entry
;
1267 unsigned long flags
;
1269 memset(&entry
,0,sizeof(entry
));
1271 disable_8259A_irq(0);
1274 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1277 * We use logical delivery to get the timer IRQ
1280 entry
.dest_mode
= INT_DEST_MODE
;
1281 entry
.mask
= 0; /* unmask IRQ now */
1282 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1283 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1286 entry
.vector
= vector
;
1289 * The timer IRQ doesn't have to know that behind the
1290 * scene we have a 8259A-master in AEOI mode ...
1292 irq_desc
[0].handler
= &ioapic_edge_type
;
1295 * Add it to the IO-APIC irq-routing table:
1297 spin_lock_irqsave(&ioapic_lock
, flags
);
1298 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
1299 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
1300 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1302 enable_8259A_irq(0);
1305 static inline void UNEXPECTED_IO_APIC(void)
1309 void __init
print_IO_APIC(void)
1312 union IO_APIC_reg_00 reg_00
;
1313 union IO_APIC_reg_01 reg_01
;
1314 union IO_APIC_reg_02 reg_02
;
1315 union IO_APIC_reg_03 reg_03
;
1316 unsigned long flags
;
1318 if (apic_verbosity
== APIC_QUIET
)
1321 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1322 for (i
= 0; i
< nr_ioapics
; i
++)
1323 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1324 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1327 * We are a bit conservative about what we expect. We have to
1328 * know about every hardware change ASAP.
1330 printk(KERN_INFO
"testing the IO APIC.......................\n");
1332 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1334 spin_lock_irqsave(&ioapic_lock
, flags
);
1335 reg_00
.raw
= io_apic_read(apic
, 0);
1336 reg_01
.raw
= io_apic_read(apic
, 1);
1337 if (reg_01
.bits
.version
>= 0x10)
1338 reg_02
.raw
= io_apic_read(apic
, 2);
1339 if (reg_01
.bits
.version
>= 0x20)
1340 reg_03
.raw
= io_apic_read(apic
, 3);
1341 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1343 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1344 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1345 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1346 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1347 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1348 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1349 UNEXPECTED_IO_APIC();
1350 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1351 UNEXPECTED_IO_APIC();
1353 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1354 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1355 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1356 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1357 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1358 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1359 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1360 (reg_01
.bits
.entries
!= 0x2E) &&
1361 (reg_01
.bits
.entries
!= 0x3F)
1363 UNEXPECTED_IO_APIC();
1365 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1366 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1367 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1368 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1369 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1370 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1371 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1373 UNEXPECTED_IO_APIC();
1374 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1375 UNEXPECTED_IO_APIC();
1378 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1379 * but the value of reg_02 is read as the previous read register
1380 * value, so ignore it if reg_02 == reg_01.
1382 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1383 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1384 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1385 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1386 UNEXPECTED_IO_APIC();
1390 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1391 * or reg_03, but the value of reg_0[23] is read as the previous read
1392 * register value, so ignore it if reg_03 == reg_0[12].
1394 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1395 reg_03
.raw
!= reg_01
.raw
) {
1396 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1397 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1398 if (reg_03
.bits
.__reserved_1
)
1399 UNEXPECTED_IO_APIC();
1402 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1404 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1405 " Stat Dest Deli Vect: \n");
1407 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1408 struct IO_APIC_route_entry entry
;
1410 spin_lock_irqsave(&ioapic_lock
, flags
);
1411 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
1412 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
1413 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1415 printk(KERN_DEBUG
" %02x %03X %02X ",
1417 entry
.dest
.logical
.logical_dest
,
1418 entry
.dest
.physical
.physical_dest
1421 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1426 entry
.delivery_status
,
1428 entry
.delivery_mode
,
1433 if (use_pci_vector())
1434 printk(KERN_INFO
"Using vector-based indexing\n");
1435 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1436 for (i
= 0; i
< NR_IRQS
; i
++) {
1437 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1440 if (use_pci_vector() && !platform_legacy_irq(i
))
1441 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1443 printk(KERN_DEBUG
"IRQ%d ", i
);
1445 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1448 entry
= irq_2_pin
+ entry
->next
;
1453 printk(KERN_INFO
".................................... done.\n");
1460 static void print_APIC_bitfield (int base
)
1465 if (apic_verbosity
== APIC_QUIET
)
1468 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1469 for (i
= 0; i
< 8; i
++) {
1470 v
= apic_read(base
+ i
*0x10);
1471 for (j
= 0; j
< 32; j
++) {
1481 void /*__init*/ print_local_APIC(void * dummy
)
1483 unsigned int v
, ver
, maxlvt
;
1485 if (apic_verbosity
== APIC_QUIET
)
1488 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1489 smp_processor_id(), hard_smp_processor_id());
1490 v
= apic_read(APIC_ID
);
1491 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1492 v
= apic_read(APIC_LVR
);
1493 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1494 ver
= GET_APIC_VERSION(v
);
1495 maxlvt
= get_maxlvt();
1497 v
= apic_read(APIC_TASKPRI
);
1498 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1500 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1501 v
= apic_read(APIC_ARBPRI
);
1502 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1503 v
& APIC_ARBPRI_MASK
);
1504 v
= apic_read(APIC_PROCPRI
);
1505 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1508 v
= apic_read(APIC_EOI
);
1509 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1510 v
= apic_read(APIC_RRR
);
1511 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1512 v
= apic_read(APIC_LDR
);
1513 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1514 v
= apic_read(APIC_DFR
);
1515 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1516 v
= apic_read(APIC_SPIV
);
1517 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1519 printk(KERN_DEBUG
"... APIC ISR field:\n");
1520 print_APIC_bitfield(APIC_ISR
);
1521 printk(KERN_DEBUG
"... APIC TMR field:\n");
1522 print_APIC_bitfield(APIC_TMR
);
1523 printk(KERN_DEBUG
"... APIC IRR field:\n");
1524 print_APIC_bitfield(APIC_IRR
);
1526 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1527 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1528 apic_write(APIC_ESR
, 0);
1529 v
= apic_read(APIC_ESR
);
1530 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1533 v
= apic_read(APIC_ICR
);
1534 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1535 v
= apic_read(APIC_ICR2
);
1536 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1538 v
= apic_read(APIC_LVTT
);
1539 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1541 if (maxlvt
> 3) { /* PC is LVT#4. */
1542 v
= apic_read(APIC_LVTPC
);
1543 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1545 v
= apic_read(APIC_LVT0
);
1546 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1547 v
= apic_read(APIC_LVT1
);
1548 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1550 if (maxlvt
> 2) { /* ERR is LVT#3. */
1551 v
= apic_read(APIC_LVTERR
);
1552 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1555 v
= apic_read(APIC_TMICT
);
1556 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1557 v
= apic_read(APIC_TMCCT
);
1558 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1559 v
= apic_read(APIC_TDCR
);
1560 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1564 void print_all_local_APICs (void)
1566 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1569 void /*__init*/ print_PIC(void)
1571 extern spinlock_t i8259A_lock
;
1573 unsigned long flags
;
1575 if (apic_verbosity
== APIC_QUIET
)
1578 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1580 spin_lock_irqsave(&i8259A_lock
, flags
);
1582 v
= inb(0xa1) << 8 | inb(0x21);
1583 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1585 v
= inb(0xa0) << 8 | inb(0x20);
1586 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1590 v
= inb(0xa0) << 8 | inb(0x20);
1594 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1596 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1598 v
= inb(0x4d1) << 8 | inb(0x4d0);
1599 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1604 static void __init
enable_IO_APIC(void)
1606 union IO_APIC_reg_01 reg_01
;
1608 unsigned long flags
;
1610 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1611 irq_2_pin
[i
].pin
= -1;
1612 irq_2_pin
[i
].next
= 0;
1615 for (i
= 0; i
< MAX_PIRQS
; i
++)
1616 pirq_entries
[i
] = -1;
1619 * The number of IO-APIC IRQ registers (== #pins):
1621 for (i
= 0; i
< nr_ioapics
; i
++) {
1622 spin_lock_irqsave(&ioapic_lock
, flags
);
1623 reg_01
.raw
= io_apic_read(i
, 1);
1624 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1625 nr_ioapic_registers
[i
] = reg_01
.bits
.entries
+1;
1629 * Do not trust the IO-APIC being empty at bootup
1635 * Not an __init, needed by the reboot code
1637 void disable_IO_APIC(void)
1641 * Clear the IO-APIC before rebooting:
1646 * If the i82559 is routed through an IOAPIC
1647 * Put that IOAPIC in virtual wire mode
1648 * so legacy interrups can be delivered.
1650 pin
= find_isa_irq_pin(0, mp_ExtINT
);
1652 struct IO_APIC_route_entry entry
;
1653 unsigned long flags
;
1655 memset(&entry
, 0, sizeof(entry
));
1656 entry
.mask
= 0; /* Enabled */
1657 entry
.trigger
= 0; /* Edge */
1659 entry
.polarity
= 0; /* High */
1660 entry
.delivery_status
= 0;
1661 entry
.dest_mode
= 0; /* Physical */
1662 entry
.delivery_mode
= 7; /* ExtInt */
1664 entry
.dest
.physical
.physical_dest
= 0;
1668 * Add it to the IO-APIC irq-routing table:
1670 spin_lock_irqsave(&ioapic_lock
, flags
);
1671 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
1672 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
1673 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1675 disconnect_bsp_APIC(pin
!= -1);
1679 * function to set the IO-APIC physical IDs based on the
1680 * values stored in the MPC table.
1682 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1685 #ifndef CONFIG_X86_NUMAQ
1686 static void __init
setup_ioapic_ids_from_mpc(void)
1688 union IO_APIC_reg_00 reg_00
;
1689 physid_mask_t phys_id_present_map
;
1692 unsigned char old_id
;
1693 unsigned long flags
;
1696 * Don't check I/O APIC IDs for xAPIC systems. They have
1697 * no meaning without the serial APIC bus.
1699 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&& boot_cpu_data
.x86
< 15))
1702 * This is broken; anything with a real cpu count has to
1703 * circumvent this idiocy regardless.
1705 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1708 * Set the IOAPIC ID to the value stored in the MPC table.
1710 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1712 /* Read the register 0 value */
1713 spin_lock_irqsave(&ioapic_lock
, flags
);
1714 reg_00
.raw
= io_apic_read(apic
, 0);
1715 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1717 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1719 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1720 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1721 apic
, mp_ioapics
[apic
].mpc_apicid
);
1722 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1724 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1728 * Sanity check, is the ID really free? Every APIC in a
1729 * system must have a unique ID or we get lots of nice
1730 * 'stuck on smp_invalidate_needed IPI wait' messages.
1732 if (check_apicid_used(phys_id_present_map
,
1733 mp_ioapics
[apic
].mpc_apicid
)) {
1734 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1735 apic
, mp_ioapics
[apic
].mpc_apicid
);
1736 for (i
= 0; i
< get_physical_broadcast(); i
++)
1737 if (!physid_isset(i
, phys_id_present_map
))
1739 if (i
>= get_physical_broadcast())
1740 panic("Max APIC ID exceeded!\n");
1741 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1743 physid_set(i
, phys_id_present_map
);
1744 mp_ioapics
[apic
].mpc_apicid
= i
;
1747 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1748 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1749 "phys_id_present_map\n",
1750 mp_ioapics
[apic
].mpc_apicid
);
1751 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1756 * We need to adjust the IRQ routing table
1757 * if the ID changed.
1759 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1760 for (i
= 0; i
< mp_irq_entries
; i
++)
1761 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1762 mp_irqs
[i
].mpc_dstapic
1763 = mp_ioapics
[apic
].mpc_apicid
;
1766 * Read the right value from the MPC table and
1767 * write it into the ID register.
1769 apic_printk(APIC_VERBOSE
, KERN_INFO
1770 "...changing IO-APIC physical APIC ID to %d ...",
1771 mp_ioapics
[apic
].mpc_apicid
);
1773 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1774 spin_lock_irqsave(&ioapic_lock
, flags
);
1775 io_apic_write(apic
, 0, reg_00
.raw
);
1776 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1781 spin_lock_irqsave(&ioapic_lock
, flags
);
1782 reg_00
.raw
= io_apic_read(apic
, 0);
1783 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1784 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1785 printk("could not set ID!\n");
1787 apic_printk(APIC_VERBOSE
, " ok.\n");
1791 static void __init
setup_ioapic_ids_from_mpc(void) { }
1795 * There is a nasty bug in some older SMP boards, their mptable lies
1796 * about the timer IRQ. We do the following to work around the situation:
1798 * - timer IRQ defaults to IO-APIC IRQ
1799 * - if this function detects that timer IRQs are defunct, then we fall
1800 * back to ISA timer IRQs
1802 static int __init
timer_irq_works(void)
1804 unsigned long t1
= jiffies
;
1807 /* Let ten ticks pass... */
1808 mdelay((10 * 1000) / HZ
);
1811 * Expect a few ticks at least, to be sure some possible
1812 * glue logic does not lock up after one or two first
1813 * ticks in a non-ExtINT mode. Also the local APIC
1814 * might have cached one ExtINT interrupt. Finally, at
1815 * least one tick may be lost due to delays.
1817 if (jiffies
- t1
> 4)
1824 * In the SMP+IOAPIC case it might happen that there are an unspecified
1825 * number of pending IRQ events unhandled. These cases are very rare,
1826 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1827 * better to do it this way as thus we do not have to be aware of
1828 * 'pending' interrupts in the IRQ path, except at this point.
1831 * Edge triggered needs to resend any interrupt
1832 * that was delayed but this is now handled in the device
1837 * Starting up a edge-triggered IO-APIC interrupt is
1838 * nasty - we need to make sure that we get the edge.
1839 * If it is already asserted for some reason, we need
1840 * return 1 to indicate that is was pending.
1842 * This is not complete - we should be able to fake
1843 * an edge even if it isn't on the 8259A...
1845 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1847 int was_pending
= 0;
1848 unsigned long flags
;
1850 spin_lock_irqsave(&ioapic_lock
, flags
);
1852 disable_8259A_irq(irq
);
1853 if (i8259A_irq_pending(irq
))
1856 __unmask_IO_APIC_irq(irq
);
1857 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1863 * Once we have recorded IRQ_PENDING already, we can mask the
1864 * interrupt for real. This prevents IRQ storms from unhandled
1867 static void ack_edge_ioapic_irq(unsigned int irq
)
1870 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1871 == (IRQ_PENDING
| IRQ_DISABLED
))
1872 mask_IO_APIC_irq(irq
);
1877 * Level triggered interrupts can just be masked,
1878 * and shutting down and starting up the interrupt
1879 * is the same as enabling and disabling them -- except
1880 * with a startup need to return a "was pending" value.
1882 * Level triggered interrupts are special because we
1883 * do not touch any IO-APIC register while handling
1884 * them. We ack the APIC in the end-IRQ handler, not
1885 * in the start-IRQ-handler. Protection against reentrance
1886 * from the same interrupt is still provided, both by the
1887 * generic IRQ layer and by the fact that an unacked local
1888 * APIC does not accept IRQs.
1890 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1892 unmask_IO_APIC_irq(irq
);
1894 return 0; /* don't check for pending */
1897 static void end_level_ioapic_irq (unsigned int irq
)
1904 * It appears there is an erratum which affects at least version 0x11
1905 * of I/O APIC (that's the 82093AA and cores integrated into various
1906 * chipsets). Under certain conditions a level-triggered interrupt is
1907 * erroneously delivered as edge-triggered one but the respective IRR
1908 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1909 * message but it will never arrive and further interrupts are blocked
1910 * from the source. The exact reason is so far unknown, but the
1911 * phenomenon was observed when two consecutive interrupt requests
1912 * from a given source get delivered to the same CPU and the source is
1913 * temporarily disabled in between.
1915 * A workaround is to simulate an EOI message manually. We achieve it
1916 * by setting the trigger mode to edge and then to level when the edge
1917 * trigger mode gets detected in the TMR of a local APIC for a
1918 * level-triggered interrupt. We mask the source for the time of the
1919 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1920 * The idea is from Manfred Spraul. --macro
1922 i
= IO_APIC_VECTOR(irq
);
1924 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1928 if (!(v
& (1 << (i
& 0x1f)))) {
1929 atomic_inc(&irq_mis_count
);
1930 spin_lock(&ioapic_lock
);
1931 __mask_and_edge_IO_APIC_irq(irq
);
1932 __unmask_and_level_IO_APIC_irq(irq
);
1933 spin_unlock(&ioapic_lock
);
1937 #ifdef CONFIG_PCI_MSI
1938 static unsigned int startup_edge_ioapic_vector(unsigned int vector
)
1940 int irq
= vector_to_irq(vector
);
1942 return startup_edge_ioapic_irq(irq
);
1945 static void ack_edge_ioapic_vector(unsigned int vector
)
1947 int irq
= vector_to_irq(vector
);
1949 ack_edge_ioapic_irq(irq
);
1952 static unsigned int startup_level_ioapic_vector (unsigned int vector
)
1954 int irq
= vector_to_irq(vector
);
1956 return startup_level_ioapic_irq (irq
);
1959 static void end_level_ioapic_vector (unsigned int vector
)
1961 int irq
= vector_to_irq(vector
);
1963 end_level_ioapic_irq(irq
);
1966 static void mask_IO_APIC_vector (unsigned int vector
)
1968 int irq
= vector_to_irq(vector
);
1970 mask_IO_APIC_irq(irq
);
1973 static void unmask_IO_APIC_vector (unsigned int vector
)
1975 int irq
= vector_to_irq(vector
);
1977 unmask_IO_APIC_irq(irq
);
1980 static void set_ioapic_affinity_vector (unsigned int vector
,
1983 int irq
= vector_to_irq(vector
);
1985 set_ioapic_affinity_irq(irq
, cpu_mask
);
1990 * Level and edge triggered IO-APIC interrupts need different handling,
1991 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1992 * handled with the level-triggered descriptor, but that one has slightly
1993 * more overhead. Level-triggered interrupts cannot be handled with the
1994 * edge-triggered handler, without risking IRQ storms and other ugly
1997 static struct hw_interrupt_type ioapic_edge_type
= {
1998 .typename
= "IO-APIC-edge",
1999 .startup
= startup_edge_ioapic
,
2000 .shutdown
= shutdown_edge_ioapic
,
2001 .enable
= enable_edge_ioapic
,
2002 .disable
= disable_edge_ioapic
,
2003 .ack
= ack_edge_ioapic
,
2004 .end
= end_edge_ioapic
,
2005 .set_affinity
= set_ioapic_affinity
,
2008 static struct hw_interrupt_type ioapic_level_type
= {
2009 .typename
= "IO-APIC-level",
2010 .startup
= startup_level_ioapic
,
2011 .shutdown
= shutdown_level_ioapic
,
2012 .enable
= enable_level_ioapic
,
2013 .disable
= disable_level_ioapic
,
2014 .ack
= mask_and_ack_level_ioapic
,
2015 .end
= end_level_ioapic
,
2016 .set_affinity
= set_ioapic_affinity
,
2019 static inline void init_IO_APIC_traps(void)
2024 * NOTE! The local APIC isn't very good at handling
2025 * multiple interrupts at the same interrupt level.
2026 * As the interrupt level is determined by taking the
2027 * vector number and shifting that right by 4, we
2028 * want to spread these out a bit so that they don't
2029 * all fall in the same interrupt level.
2031 * Also, we've got to be careful not to trash gate
2032 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2034 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2036 if (use_pci_vector()) {
2037 if (!platform_legacy_irq(tmp
))
2038 if ((tmp
= vector_to_irq(tmp
)) == -1)
2041 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
2043 * Hmm.. We don't have an entry for this,
2044 * so default to an old-fashioned 8259
2045 * interrupt if we can..
2048 make_8259A_irq(irq
);
2050 /* Strange. Oh, well.. */
2051 irq_desc
[irq
].handler
= &no_irq_type
;
2056 static void enable_lapic_irq (unsigned int irq
)
2060 v
= apic_read(APIC_LVT0
);
2061 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2064 static void disable_lapic_irq (unsigned int irq
)
2068 v
= apic_read(APIC_LVT0
);
2069 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2072 static void ack_lapic_irq (unsigned int irq
)
2077 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
2079 static struct hw_interrupt_type lapic_irq_type
= {
2080 .typename
= "local-APIC-edge",
2081 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
2082 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
2083 .enable
= enable_lapic_irq
,
2084 .disable
= disable_lapic_irq
,
2085 .ack
= ack_lapic_irq
,
2086 .end
= end_lapic_irq
2089 static void setup_nmi (void)
2092 * Dirty trick to enable the NMI watchdog ...
2093 * We put the 8259A master into AEOI mode and
2094 * unmask on all local APICs LVT0 as NMI.
2096 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2097 * is from Maciej W. Rozycki - so we do not have to EOI from
2098 * the NMI handler or the timer interrupt.
2100 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2102 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2104 apic_printk(APIC_VERBOSE
, " done.\n");
2108 * This looks a bit hackish but it's about the only one way of sending
2109 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2110 * not support the ExtINT mode, unfortunately. We need to send these
2111 * cycles as some i82489DX-based boards have glue logic that keeps the
2112 * 8259A interrupt line asserted until INTA. --macro
2114 static inline void unlock_ExtINT_logic(void)
2117 struct IO_APIC_route_entry entry0
, entry1
;
2118 unsigned char save_control
, save_freq_select
;
2119 unsigned long flags
;
2121 pin
= find_isa_irq_pin(8, mp_INT
);
2125 spin_lock_irqsave(&ioapic_lock
, flags
);
2126 *(((int *)&entry0
) + 1) = io_apic_read(0, 0x11 + 2 * pin
);
2127 *(((int *)&entry0
) + 0) = io_apic_read(0, 0x10 + 2 * pin
);
2128 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2129 clear_IO_APIC_pin(0, pin
);
2131 memset(&entry1
, 0, sizeof(entry1
));
2133 entry1
.dest_mode
= 0; /* physical delivery */
2134 entry1
.mask
= 0; /* unmask IRQ now */
2135 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2136 entry1
.delivery_mode
= dest_ExtINT
;
2137 entry1
.polarity
= entry0
.polarity
;
2141 spin_lock_irqsave(&ioapic_lock
, flags
);
2142 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
2143 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
2144 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2146 save_control
= CMOS_READ(RTC_CONTROL
);
2147 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2148 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2150 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2155 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2159 CMOS_WRITE(save_control
, RTC_CONTROL
);
2160 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2161 clear_IO_APIC_pin(0, pin
);
2163 spin_lock_irqsave(&ioapic_lock
, flags
);
2164 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
2165 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
2166 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2170 * This code may look a bit paranoid, but it's supposed to cooperate with
2171 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2172 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2173 * fanatically on his truly buggy board.
2175 static inline void check_timer(void)
2181 * get/set the timer IRQ vector:
2183 disable_8259A_irq(0);
2184 vector
= assign_irq_vector(0);
2185 set_intr_gate(vector
, interrupt
[0]);
2188 * Subtle, code in do_timer_interrupt() expects an AEOI
2189 * mode for the 8259A whenever interrupts are routed
2190 * through I/O APICs. Also IRQ0 has to be enabled in
2191 * the 8259A which implies the virtual wire has to be
2192 * disabled in the local APIC.
2194 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2197 enable_8259A_irq(0);
2199 pin1
= find_isa_irq_pin(0, mp_INT
);
2200 pin2
= find_isa_irq_pin(0, mp_ExtINT
);
2202 printk(KERN_INFO
"..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
2206 * Ok, does IRQ0 through the IOAPIC work?
2208 unmask_IO_APIC_irq(0);
2209 if (timer_irq_works()) {
2210 if (nmi_watchdog
== NMI_IO_APIC
) {
2211 disable_8259A_irq(0);
2213 enable_8259A_irq(0);
2217 clear_IO_APIC_pin(0, pin1
);
2218 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2221 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2223 printk("\n..... (found pin %d) ...", pin2
);
2225 * legacy devices should be connected to IO APIC #0
2227 setup_ExtINT_IRQ0_pin(pin2
, vector
);
2228 if (timer_irq_works()) {
2231 replace_pin_at_irq(0, 0, pin1
, 0, pin2
);
2233 add_pin_to_irq(0, 0, pin2
);
2234 if (nmi_watchdog
== NMI_IO_APIC
) {
2240 * Cleanup, just in case ...
2242 clear_IO_APIC_pin(0, pin2
);
2244 printk(" failed.\n");
2246 if (nmi_watchdog
== NMI_IO_APIC
) {
2247 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2251 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2253 disable_8259A_irq(0);
2254 irq_desc
[0].handler
= &lapic_irq_type
;
2255 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2256 enable_8259A_irq(0);
2258 if (timer_irq_works()) {
2259 printk(" works.\n");
2262 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2263 printk(" failed.\n");
2265 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2270 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2272 unlock_ExtINT_logic();
2274 if (timer_irq_works()) {
2275 printk(" works.\n");
2278 printk(" failed :(.\n");
2279 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2280 "report. Then try booting with the 'noapic' option");
2285 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2286 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2287 * Linux doesn't really care, as it's not actually used
2288 * for any interrupt handling anyway.
2290 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2292 void __init
setup_IO_APIC(void)
2297 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2299 io_apic_irqs
= ~PIC_IRQS
;
2301 printk("ENABLING IO-APIC IRQs\n");
2304 * Set up IO-APIC IRQ routing.
2307 setup_ioapic_ids_from_mpc();
2309 setup_IO_APIC_irqs();
2310 init_IO_APIC_traps();
2317 * Called after all the initialization is done. If we didnt find any
2318 * APIC bugs then we can allow the modify fast path
2321 static int __init
io_apic_bug_finalize(void)
2323 if(sis_apic_bug
== -1)
2328 late_initcall(io_apic_bug_finalize
);
2330 struct sysfs_ioapic_data
{
2331 struct sys_device dev
;
2332 struct IO_APIC_route_entry entry
[0];
2334 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2336 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2338 struct IO_APIC_route_entry
*entry
;
2339 struct sysfs_ioapic_data
*data
;
2340 unsigned long flags
;
2343 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2344 entry
= data
->entry
;
2345 spin_lock_irqsave(&ioapic_lock
, flags
);
2346 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2347 *(((int *)entry
) + 1) = io_apic_read(dev
->id
, 0x11 + 2 * i
);
2348 *(((int *)entry
) + 0) = io_apic_read(dev
->id
, 0x10 + 2 * i
);
2350 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2355 static int ioapic_resume(struct sys_device
*dev
)
2357 struct IO_APIC_route_entry
*entry
;
2358 struct sysfs_ioapic_data
*data
;
2359 unsigned long flags
;
2360 union IO_APIC_reg_00 reg_00
;
2363 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2364 entry
= data
->entry
;
2366 spin_lock_irqsave(&ioapic_lock
, flags
);
2367 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2368 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2369 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2370 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2372 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2373 io_apic_write(dev
->id
, 0x11+2*i
, *(((int *)entry
)+1));
2374 io_apic_write(dev
->id
, 0x10+2*i
, *(((int *)entry
)+0));
2376 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2381 static struct sysdev_class ioapic_sysdev_class
= {
2382 set_kset_name("ioapic"),
2383 .suspend
= ioapic_suspend
,
2384 .resume
= ioapic_resume
,
2387 static int __init
ioapic_init_sysfs(void)
2389 struct sys_device
* dev
;
2390 int i
, size
, error
= 0;
2392 error
= sysdev_class_register(&ioapic_sysdev_class
);
2396 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2397 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2398 * sizeof(struct IO_APIC_route_entry
);
2399 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2400 if (!mp_ioapic_data
[i
]) {
2401 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2404 memset(mp_ioapic_data
[i
], 0, size
);
2405 dev
= &mp_ioapic_data
[i
]->dev
;
2407 dev
->cls
= &ioapic_sysdev_class
;
2408 error
= sysdev_register(dev
);
2410 kfree(mp_ioapic_data
[i
]);
2411 mp_ioapic_data
[i
] = NULL
;
2412 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2420 device_initcall(ioapic_init_sysfs
);
2422 /* --------------------------------------------------------------------------
2423 ACPI-based IOAPIC Configuration
2424 -------------------------------------------------------------------------- */
2426 #ifdef CONFIG_ACPI_BOOT
2428 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2430 union IO_APIC_reg_00 reg_00
;
2431 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2433 unsigned long flags
;
2437 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2438 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2439 * supports up to 16 on one shared APIC bus.
2441 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2442 * advantage of new APIC bus architecture.
2445 if (physids_empty(apic_id_map
))
2446 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2448 spin_lock_irqsave(&ioapic_lock
, flags
);
2449 reg_00
.raw
= io_apic_read(ioapic
, 0);
2450 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2452 if (apic_id
>= get_physical_broadcast()) {
2453 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2454 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2455 apic_id
= reg_00
.bits
.ID
;
2459 * Every APIC in a system must have a unique ID or we get lots of nice
2460 * 'stuck on smp_invalidate_needed IPI wait' messages.
2462 if (check_apicid_used(apic_id_map
, apic_id
)) {
2464 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2465 if (!check_apicid_used(apic_id_map
, i
))
2469 if (i
== get_physical_broadcast())
2470 panic("Max apic_id exceeded!\n");
2472 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2473 "trying %d\n", ioapic
, apic_id
, i
);
2478 tmp
= apicid_to_cpu_present(apic_id
);
2479 physids_or(apic_id_map
, apic_id_map
, tmp
);
2481 if (reg_00
.bits
.ID
!= apic_id
) {
2482 reg_00
.bits
.ID
= apic_id
;
2484 spin_lock_irqsave(&ioapic_lock
, flags
);
2485 io_apic_write(ioapic
, 0, reg_00
.raw
);
2486 reg_00
.raw
= io_apic_read(ioapic
, 0);
2487 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2490 if (reg_00
.bits
.ID
!= apic_id
)
2491 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic
);
2494 apic_printk(APIC_VERBOSE
, KERN_INFO
2495 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2501 int __init
io_apic_get_version (int ioapic
)
2503 union IO_APIC_reg_01 reg_01
;
2504 unsigned long flags
;
2506 spin_lock_irqsave(&ioapic_lock
, flags
);
2507 reg_01
.raw
= io_apic_read(ioapic
, 1);
2508 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2510 return reg_01
.bits
.version
;
2514 int __init
io_apic_get_redir_entries (int ioapic
)
2516 union IO_APIC_reg_01 reg_01
;
2517 unsigned long flags
;
2519 spin_lock_irqsave(&ioapic_lock
, flags
);
2520 reg_01
.raw
= io_apic_read(ioapic
, 1);
2521 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2523 return reg_01
.bits
.entries
;
2527 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2529 struct IO_APIC_route_entry entry
;
2530 unsigned long flags
;
2532 if (!IO_APIC_IRQ(irq
)) {
2533 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2539 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2540 * Note that we mask (disable) IRQs now -- these get enabled when the
2541 * corresponding device driver registers for this IRQ.
2544 memset(&entry
,0,sizeof(entry
));
2546 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2547 entry
.dest_mode
= INT_DEST_MODE
;
2548 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2549 entry
.trigger
= edge_level
;
2550 entry
.polarity
= active_high_low
;
2554 * IRQs < 16 are already in the irq_2_pin[] map
2557 add_pin_to_irq(irq
, ioapic
, pin
);
2559 entry
.vector
= assign_irq_vector(irq
);
2561 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2562 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2563 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2564 edge_level
, active_high_low
);
2566 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2568 if (!ioapic
&& (irq
< 16))
2569 disable_8259A_irq(irq
);
2571 spin_lock_irqsave(&ioapic_lock
, flags
);
2572 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
2573 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
2574 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2579 #endif /*CONFIG_ACPI_BOOT*/