Merge branch 'upstream-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / arch / i386 / kernel / tsc.c
1 /*
2 * This code largely moved from arch/i386/kernel/timer/timer_tsc.c
3 * which was originally moved from arch/i386/kernel/time.c.
4 * See comments there for proper credits.
5 */
6
7 #include <linux/clocksource.h>
8 #include <linux/workqueue.h>
9 #include <linux/cpufreq.h>
10 #include <linux/jiffies.h>
11 #include <linux/init.h>
12 #include <linux/dmi.h>
13
14 #include <asm/delay.h>
15 #include <asm/tsc.h>
16 #include <asm/io.h>
17 #include <asm/timer.h>
18
19 #include "mach_timer.h"
20
21 /*
22 * On some systems the TSC frequency does not
23 * change with the cpu frequency. So we need
24 * an extra value to store the TSC freq
25 */
26 unsigned int tsc_khz;
27
28 int tsc_disable;
29
30 #ifdef CONFIG_X86_TSC
31 static int __init tsc_setup(char *str)
32 {
33 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
34 "cannot disable TSC.\n");
35 return 1;
36 }
37 #else
38 /*
39 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
40 * in cpu/common.c
41 */
42 static int __init tsc_setup(char *str)
43 {
44 tsc_disable = 1;
45
46 return 1;
47 }
48 #endif
49
50 __setup("notsc", tsc_setup);
51
52 /*
53 * code to mark and check if the TSC is unstable
54 * due to cpufreq or due to unsynced TSCs
55 */
56 static int tsc_unstable;
57
58 static inline int check_tsc_unstable(void)
59 {
60 return tsc_unstable;
61 }
62
63 /* Accellerators for sched_clock()
64 * convert from cycles(64bits) => nanoseconds (64bits)
65 * basic equation:
66 * ns = cycles / (freq / ns_per_sec)
67 * ns = cycles * (ns_per_sec / freq)
68 * ns = cycles * (10^9 / (cpu_khz * 10^3))
69 * ns = cycles * (10^6 / cpu_khz)
70 *
71 * Then we use scaling math (suggested by george@mvista.com) to get:
72 * ns = cycles * (10^6 * SC / cpu_khz) / SC
73 * ns = cycles * cyc2ns_scale / SC
74 *
75 * And since SC is a constant power of two, we can convert the div
76 * into a shift.
77 *
78 * We can use khz divisor instead of mhz to keep a better percision, since
79 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
80 * (mathieu.desnoyers@polymtl.ca)
81 *
82 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
83 */
84 static unsigned long cyc2ns_scale __read_mostly;
85
86 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
87
88 static inline void set_cyc2ns_scale(unsigned long cpu_khz)
89 {
90 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
91 }
92
93 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
94 {
95 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
96 }
97
98 /*
99 * Scheduler clock - returns current time in nanosec units.
100 */
101 unsigned long long sched_clock(void)
102 {
103 unsigned long long this_offset;
104
105 /*
106 * Fall back to jiffies if there's no TSC available:
107 */
108 if (tsc_unstable || unlikely(tsc_disable))
109 /* No locking but a rare wrong value is not a big deal: */
110 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
111
112 /* read the Time Stamp Counter: */
113 get_scheduled_cycles(this_offset);
114
115 /* return the value in ns */
116 return cycles_2_ns(this_offset);
117 }
118
119 unsigned long native_calculate_cpu_khz(void)
120 {
121 unsigned long long start, end;
122 unsigned long count;
123 u64 delta64;
124 int i;
125 unsigned long flags;
126
127 local_irq_save(flags);
128
129 /* run 3 times to ensure the cache is warm */
130 for (i = 0; i < 3; i++) {
131 mach_prepare_counter();
132 rdtscll(start);
133 mach_countup(&count);
134 rdtscll(end);
135 }
136 /*
137 * Error: ECTCNEVERSET
138 * The CTC wasn't reliable: we got a hit on the very first read,
139 * or the CPU was so fast/slow that the quotient wouldn't fit in
140 * 32 bits..
141 */
142 if (count <= 1)
143 goto err;
144
145 delta64 = end - start;
146
147 /* cpu freq too fast: */
148 if (delta64 > (1ULL<<32))
149 goto err;
150
151 /* cpu freq too slow: */
152 if (delta64 <= CALIBRATE_TIME_MSEC)
153 goto err;
154
155 delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
156 do_div(delta64,CALIBRATE_TIME_MSEC);
157
158 local_irq_restore(flags);
159 return (unsigned long)delta64;
160 err:
161 local_irq_restore(flags);
162 return 0;
163 }
164
165 int recalibrate_cpu_khz(void)
166 {
167 #ifndef CONFIG_SMP
168 unsigned long cpu_khz_old = cpu_khz;
169
170 if (cpu_has_tsc) {
171 cpu_khz = calculate_cpu_khz();
172 tsc_khz = cpu_khz;
173 cpu_data[0].loops_per_jiffy =
174 cpufreq_scale(cpu_data[0].loops_per_jiffy,
175 cpu_khz_old, cpu_khz);
176 return 0;
177 } else
178 return -ENODEV;
179 #else
180 return -ENODEV;
181 #endif
182 }
183
184 EXPORT_SYMBOL(recalibrate_cpu_khz);
185
186 #ifdef CONFIG_CPU_FREQ
187
188 /*
189 * if the CPU frequency is scaled, TSC-based delays will need a different
190 * loops_per_jiffy value to function properly.
191 */
192 static unsigned int ref_freq = 0;
193 static unsigned long loops_per_jiffy_ref = 0;
194 static unsigned long cpu_khz_ref = 0;
195
196 static int
197 time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
198 {
199 struct cpufreq_freqs *freq = data;
200
201 if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
202 write_seqlock_irq(&xtime_lock);
203
204 if (!ref_freq) {
205 if (!freq->old){
206 ref_freq = freq->new;
207 goto end;
208 }
209 ref_freq = freq->old;
210 loops_per_jiffy_ref = cpu_data[freq->cpu].loops_per_jiffy;
211 cpu_khz_ref = cpu_khz;
212 }
213
214 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
215 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
216 (val == CPUFREQ_RESUMECHANGE)) {
217 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
218 cpu_data[freq->cpu].loops_per_jiffy =
219 cpufreq_scale(loops_per_jiffy_ref,
220 ref_freq, freq->new);
221
222 if (cpu_khz) {
223
224 if (num_online_cpus() == 1)
225 cpu_khz = cpufreq_scale(cpu_khz_ref,
226 ref_freq, freq->new);
227 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
228 tsc_khz = cpu_khz;
229 set_cyc2ns_scale(cpu_khz);
230 /*
231 * TSC based sched_clock turns
232 * to junk w/ cpufreq
233 */
234 mark_tsc_unstable();
235 }
236 }
237 }
238 end:
239 if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
240 write_sequnlock_irq(&xtime_lock);
241
242 return 0;
243 }
244
245 static struct notifier_block time_cpufreq_notifier_block = {
246 .notifier_call = time_cpufreq_notifier
247 };
248
249 static int __init cpufreq_tsc(void)
250 {
251 return cpufreq_register_notifier(&time_cpufreq_notifier_block,
252 CPUFREQ_TRANSITION_NOTIFIER);
253 }
254 core_initcall(cpufreq_tsc);
255
256 #endif
257
258 /* clock source code */
259
260 static unsigned long current_tsc_khz = 0;
261
262 static cycle_t read_tsc(void)
263 {
264 cycle_t ret;
265
266 rdtscll(ret);
267
268 return ret;
269 }
270
271 static struct clocksource clocksource_tsc = {
272 .name = "tsc",
273 .rating = 300,
274 .read = read_tsc,
275 .mask = CLOCKSOURCE_MASK(64),
276 .mult = 0, /* to be set */
277 .shift = 22,
278 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
279 CLOCK_SOURCE_MUST_VERIFY,
280 };
281
282 void mark_tsc_unstable(void)
283 {
284 if (!tsc_unstable) {
285 tsc_unstable = 1;
286 /* Can be called before registration */
287 if (clocksource_tsc.mult)
288 clocksource_change_rating(&clocksource_tsc, 0);
289 else
290 clocksource_tsc.rating = 0;
291 }
292 }
293 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
294
295 static int __init dmi_mark_tsc_unstable(struct dmi_system_id *d)
296 {
297 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
298 d->ident);
299 tsc_unstable = 1;
300 return 0;
301 }
302
303 /* List of systems that have known TSC problems */
304 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
305 {
306 .callback = dmi_mark_tsc_unstable,
307 .ident = "IBM Thinkpad 380XD",
308 .matches = {
309 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
310 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
311 },
312 },
313 {}
314 };
315
316 /*
317 * Make an educated guess if the TSC is trustworthy and synchronized
318 * over all CPUs.
319 */
320 __cpuinit int unsynchronized_tsc(void)
321 {
322 if (!cpu_has_tsc || tsc_unstable)
323 return 1;
324 /*
325 * Intel systems are normally all synchronized.
326 * Exceptions must mark TSC as unstable:
327 */
328 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
329 /* assume multi socket systems are not synchronized: */
330 if (num_possible_cpus() > 1)
331 tsc_unstable = 1;
332 }
333 return tsc_unstable;
334 }
335
336 /*
337 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
338 */
339 #ifdef CONFIG_MGEODE_LX
340 /* RTSC counts during suspend */
341 #define RTSC_SUSP 0x100
342
343 static void __init check_geode_tsc_reliable(void)
344 {
345 unsigned long val;
346
347 rdmsrl(MSR_GEODE_BUSCONT_CONF0, val);
348 if ((val & RTSC_SUSP))
349 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
350 }
351 #else
352 static inline void check_geode_tsc_reliable(void) { }
353 #endif
354
355
356 void __init tsc_init(void)
357 {
358 if (!cpu_has_tsc || tsc_disable)
359 goto out_no_tsc;
360
361 cpu_khz = calculate_cpu_khz();
362 tsc_khz = cpu_khz;
363
364 if (!cpu_khz)
365 goto out_no_tsc;
366
367 printk("Detected %lu.%03lu MHz processor.\n",
368 (unsigned long)cpu_khz / 1000,
369 (unsigned long)cpu_khz % 1000);
370
371 set_cyc2ns_scale(cpu_khz);
372 use_tsc_delay();
373
374 /* Check and install the TSC clocksource */
375 dmi_check_system(bad_tsc_dmi_table);
376
377 unsynchronized_tsc();
378 check_geode_tsc_reliable();
379 current_tsc_khz = tsc_khz;
380 clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
381 clocksource_tsc.shift);
382 /* lower the rating if we already know its unstable: */
383 if (check_tsc_unstable()) {
384 clocksource_tsc.rating = 0;
385 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
386 }
387 clocksource_register(&clocksource_tsc);
388
389 return;
390
391 out_no_tsc:
392 /*
393 * Set the tsc_disable flag if there's no TSC support, this
394 * makes it a fast flag for the kernel to see whether it
395 * should be using the TSC.
396 */
397 tsc_disable = 1;
398 }
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