Merge branch 'for-2.6.21' of master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart
[deliverable/linux.git] / arch / i386 / kernel / tsc.c
1 /*
2 * This code largely moved from arch/i386/kernel/timer/timer_tsc.c
3 * which was originally moved from arch/i386/kernel/time.c.
4 * See comments there for proper credits.
5 */
6
7 #include <linux/clocksource.h>
8 #include <linux/workqueue.h>
9 #include <linux/cpufreq.h>
10 #include <linux/jiffies.h>
11 #include <linux/init.h>
12 #include <linux/dmi.h>
13
14 #include <asm/delay.h>
15 #include <asm/tsc.h>
16 #include <asm/io.h>
17 #include <asm/timer.h>
18
19 #include "mach_timer.h"
20
21 static int tsc_enabled;
22
23 /*
24 * On some systems the TSC frequency does not
25 * change with the cpu frequency. So we need
26 * an extra value to store the TSC freq
27 */
28 unsigned int tsc_khz;
29
30 int tsc_disable;
31
32 #ifdef CONFIG_X86_TSC
33 static int __init tsc_setup(char *str)
34 {
35 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
36 "cannot disable TSC.\n");
37 return 1;
38 }
39 #else
40 /*
41 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
42 * in cpu/common.c
43 */
44 static int __init tsc_setup(char *str)
45 {
46 tsc_disable = 1;
47
48 return 1;
49 }
50 #endif
51
52 __setup("notsc", tsc_setup);
53
54 /*
55 * code to mark and check if the TSC is unstable
56 * due to cpufreq or due to unsynced TSCs
57 */
58 static int tsc_unstable;
59
60 static inline int check_tsc_unstable(void)
61 {
62 return tsc_unstable;
63 }
64
65 /* Accellerators for sched_clock()
66 * convert from cycles(64bits) => nanoseconds (64bits)
67 * basic equation:
68 * ns = cycles / (freq / ns_per_sec)
69 * ns = cycles * (ns_per_sec / freq)
70 * ns = cycles * (10^9 / (cpu_khz * 10^3))
71 * ns = cycles * (10^6 / cpu_khz)
72 *
73 * Then we use scaling math (suggested by george@mvista.com) to get:
74 * ns = cycles * (10^6 * SC / cpu_khz) / SC
75 * ns = cycles * cyc2ns_scale / SC
76 *
77 * And since SC is a constant power of two, we can convert the div
78 * into a shift.
79 *
80 * We can use khz divisor instead of mhz to keep a better percision, since
81 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
82 * (mathieu.desnoyers@polymtl.ca)
83 *
84 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
85 */
86 static unsigned long cyc2ns_scale __read_mostly;
87
88 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
89
90 static inline void set_cyc2ns_scale(unsigned long cpu_khz)
91 {
92 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
93 }
94
95 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
96 {
97 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
98 }
99
100 /*
101 * Scheduler clock - returns current time in nanosec units.
102 */
103 unsigned long long sched_clock(void)
104 {
105 unsigned long long this_offset;
106
107 /*
108 * Fall back to jiffies if there's no TSC available:
109 */
110 if (unlikely(!tsc_enabled))
111 /* No locking but a rare wrong value is not a big deal: */
112 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
113
114 /* read the Time Stamp Counter: */
115 get_scheduled_cycles(this_offset);
116
117 /* return the value in ns */
118 return cycles_2_ns(this_offset);
119 }
120
121 unsigned long native_calculate_cpu_khz(void)
122 {
123 unsigned long long start, end;
124 unsigned long count;
125 u64 delta64;
126 int i;
127 unsigned long flags;
128
129 local_irq_save(flags);
130
131 /* run 3 times to ensure the cache is warm */
132 for (i = 0; i < 3; i++) {
133 mach_prepare_counter();
134 rdtscll(start);
135 mach_countup(&count);
136 rdtscll(end);
137 }
138 /*
139 * Error: ECTCNEVERSET
140 * The CTC wasn't reliable: we got a hit on the very first read,
141 * or the CPU was so fast/slow that the quotient wouldn't fit in
142 * 32 bits..
143 */
144 if (count <= 1)
145 goto err;
146
147 delta64 = end - start;
148
149 /* cpu freq too fast: */
150 if (delta64 > (1ULL<<32))
151 goto err;
152
153 /* cpu freq too slow: */
154 if (delta64 <= CALIBRATE_TIME_MSEC)
155 goto err;
156
157 delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
158 do_div(delta64,CALIBRATE_TIME_MSEC);
159
160 local_irq_restore(flags);
161 return (unsigned long)delta64;
162 err:
163 local_irq_restore(flags);
164 return 0;
165 }
166
167 int recalibrate_cpu_khz(void)
168 {
169 #ifndef CONFIG_SMP
170 unsigned long cpu_khz_old = cpu_khz;
171
172 if (cpu_has_tsc) {
173 cpu_khz = calculate_cpu_khz();
174 tsc_khz = cpu_khz;
175 cpu_data[0].loops_per_jiffy =
176 cpufreq_scale(cpu_data[0].loops_per_jiffy,
177 cpu_khz_old, cpu_khz);
178 return 0;
179 } else
180 return -ENODEV;
181 #else
182 return -ENODEV;
183 #endif
184 }
185
186 EXPORT_SYMBOL(recalibrate_cpu_khz);
187
188 #ifdef CONFIG_CPU_FREQ
189
190 /*
191 * if the CPU frequency is scaled, TSC-based delays will need a different
192 * loops_per_jiffy value to function properly.
193 */
194 static unsigned int ref_freq = 0;
195 static unsigned long loops_per_jiffy_ref = 0;
196 static unsigned long cpu_khz_ref = 0;
197
198 static int
199 time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
200 {
201 struct cpufreq_freqs *freq = data;
202
203 if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
204 write_seqlock_irq(&xtime_lock);
205
206 if (!ref_freq) {
207 if (!freq->old){
208 ref_freq = freq->new;
209 goto end;
210 }
211 ref_freq = freq->old;
212 loops_per_jiffy_ref = cpu_data[freq->cpu].loops_per_jiffy;
213 cpu_khz_ref = cpu_khz;
214 }
215
216 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
217 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
218 (val == CPUFREQ_RESUMECHANGE)) {
219 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
220 cpu_data[freq->cpu].loops_per_jiffy =
221 cpufreq_scale(loops_per_jiffy_ref,
222 ref_freq, freq->new);
223
224 if (cpu_khz) {
225
226 if (num_online_cpus() == 1)
227 cpu_khz = cpufreq_scale(cpu_khz_ref,
228 ref_freq, freq->new);
229 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
230 tsc_khz = cpu_khz;
231 set_cyc2ns_scale(cpu_khz);
232 /*
233 * TSC based sched_clock turns
234 * to junk w/ cpufreq
235 */
236 mark_tsc_unstable();
237 }
238 }
239 }
240 end:
241 if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
242 write_sequnlock_irq(&xtime_lock);
243
244 return 0;
245 }
246
247 static struct notifier_block time_cpufreq_notifier_block = {
248 .notifier_call = time_cpufreq_notifier
249 };
250
251 static int __init cpufreq_tsc(void)
252 {
253 return cpufreq_register_notifier(&time_cpufreq_notifier_block,
254 CPUFREQ_TRANSITION_NOTIFIER);
255 }
256 core_initcall(cpufreq_tsc);
257
258 #endif
259
260 /* clock source code */
261
262 static unsigned long current_tsc_khz = 0;
263
264 static cycle_t read_tsc(void)
265 {
266 cycle_t ret;
267
268 rdtscll(ret);
269
270 return ret;
271 }
272
273 static struct clocksource clocksource_tsc = {
274 .name = "tsc",
275 .rating = 300,
276 .read = read_tsc,
277 .mask = CLOCKSOURCE_MASK(64),
278 .mult = 0, /* to be set */
279 .shift = 22,
280 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
281 CLOCK_SOURCE_MUST_VERIFY,
282 };
283
284 void mark_tsc_unstable(void)
285 {
286 if (!tsc_unstable) {
287 tsc_unstable = 1;
288 tsc_enabled = 0;
289 /* Can be called before registration */
290 if (clocksource_tsc.mult)
291 clocksource_change_rating(&clocksource_tsc, 0);
292 else
293 clocksource_tsc.rating = 0;
294 }
295 }
296 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
297
298 static int __init dmi_mark_tsc_unstable(struct dmi_system_id *d)
299 {
300 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
301 d->ident);
302 tsc_unstable = 1;
303 return 0;
304 }
305
306 /* List of systems that have known TSC problems */
307 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
308 {
309 .callback = dmi_mark_tsc_unstable,
310 .ident = "IBM Thinkpad 380XD",
311 .matches = {
312 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
313 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
314 },
315 },
316 {}
317 };
318
319 /*
320 * Make an educated guess if the TSC is trustworthy and synchronized
321 * over all CPUs.
322 */
323 __cpuinit int unsynchronized_tsc(void)
324 {
325 if (!cpu_has_tsc || tsc_unstable)
326 return 1;
327 /*
328 * Intel systems are normally all synchronized.
329 * Exceptions must mark TSC as unstable:
330 */
331 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
332 /* assume multi socket systems are not synchronized: */
333 if (num_possible_cpus() > 1)
334 tsc_unstable = 1;
335 }
336 return tsc_unstable;
337 }
338
339 /*
340 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
341 */
342 #ifdef CONFIG_MGEODE_LX
343 /* RTSC counts during suspend */
344 #define RTSC_SUSP 0x100
345
346 static void __init check_geode_tsc_reliable(void)
347 {
348 unsigned long val;
349
350 rdmsrl(MSR_GEODE_BUSCONT_CONF0, val);
351 if ((val & RTSC_SUSP))
352 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
353 }
354 #else
355 static inline void check_geode_tsc_reliable(void) { }
356 #endif
357
358
359 void __init tsc_init(void)
360 {
361 if (!cpu_has_tsc || tsc_disable)
362 goto out_no_tsc;
363
364 cpu_khz = calculate_cpu_khz();
365 tsc_khz = cpu_khz;
366
367 if (!cpu_khz)
368 goto out_no_tsc;
369
370 printk("Detected %lu.%03lu MHz processor.\n",
371 (unsigned long)cpu_khz / 1000,
372 (unsigned long)cpu_khz % 1000);
373
374 set_cyc2ns_scale(cpu_khz);
375 use_tsc_delay();
376
377 /* Check and install the TSC clocksource */
378 dmi_check_system(bad_tsc_dmi_table);
379
380 unsynchronized_tsc();
381 check_geode_tsc_reliable();
382 current_tsc_khz = tsc_khz;
383 clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
384 clocksource_tsc.shift);
385 /* lower the rating if we already know its unstable: */
386 if (check_tsc_unstable()) {
387 clocksource_tsc.rating = 0;
388 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
389 } else
390 tsc_enabled = 1;
391
392 clocksource_register(&clocksource_tsc);
393
394 return;
395
396 out_no_tsc:
397 /*
398 * Set the tsc_disable flag if there's no TSC support, this
399 * makes it a fast flag for the kernel to see whether it
400 * should be using the TSC.
401 */
402 tsc_disable = 1;
403 }
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