arch/i386/pci/mmconfig.c

   1 /*
   2  * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
   3  * Copyright (C) 2004 Intel Corp.
   4  *
   5  * This code is released under the GNU General Public License version 2.
   6  */
   7
   8 /*
   9  * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
  10  */
  11
  12 #include <linux/pci.h>
  13 #include <linux/init.h>
  14 #include <linux/acpi.h>
  15 #include <asm/e820.h>
  16 #include "pci.h"
  17
  18 /* aperture is up to 256MB but BIOS may reserve less */
  19 #define MMCONFIG_APER_MIN       (2 * 1024*1024)
  20 #define MMCONFIG_APER_MAX       (256 * 1024*1024)
  21
  22 /* Assume systems with more busses have correct MCFG */
  23 #define MAX_CHECK_BUS 16
  24
  25 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
  26
  27 /* The base address of the last MMCONFIG device accessed */
  28 static u32 mmcfg_last_accessed_device;
  29
  30 static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
  31
  32 /*
  33  * Functions for accessing PCI configuration space with MMCONFIG accesses
  34  */
  35 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
  36 {
  37         int cfg_num = -1;
  38         struct acpi_table_mcfg_config *cfg;
  39
  40         if (seg == 0 && bus < MAX_CHECK_BUS &&
  41             test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
  42                 return 0;
  43
  44         while (1) {
  45                 ++cfg_num;
  46                 if (cfg_num >= pci_mmcfg_config_num) {
  47                         break;
  48                 }
  49                 cfg = &pci_mmcfg_config[cfg_num];
  50                 if (cfg->pci_segment_group_number != seg)
  51                         continue;
  52                 if ((cfg->start_bus_number <= bus) &&
  53                     (cfg->end_bus_number >= bus))
  54                         return cfg->base_address;
  55         }
  56
  57         /* Handle more broken MCFG tables on Asus etc.
  58            They only contain a single entry for bus 0-0. Assume
  59            this applies to all busses. */
  60         cfg = &pci_mmcfg_config[0];
  61         if (pci_mmcfg_config_num == 1 &&
  62                 cfg->pci_segment_group_number == 0 &&
  63                 (cfg->start_bus_number | cfg->end_bus_number) == 0)
  64                 return cfg->base_address;
  65
  66         /* Fall back to type 0 */
  67         return 0;
  68 }
  69
  70 static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
  71 {
  72         u32 dev_base = base | (bus << 20) | (devfn << 12);
  73         if (dev_base != mmcfg_last_accessed_device) {
  74                 mmcfg_last_accessed_device = dev_base;
  75                 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
  76         }
  77 }
  78
  79 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
  80                           unsigned int devfn, int reg, int len, u32 *value)
  81 {
  82         unsigned long flags;
  83         u32 base;
  84
  85         if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
  86                 *value = -1;
  87                 return -EINVAL;
  88         }
  89
  90         base = get_base_addr(seg, bus, devfn);
  91         if (!base)
  92                 return pci_conf1_read(seg,bus,devfn,reg,len,value);
  93
  94         spin_lock_irqsave(&pci_config_lock, flags);
  95
  96         pci_exp_set_dev_base(base, bus, devfn);
  97
  98         switch (len) {
  99         case 1:
 100                 *value = readb(mmcfg_virt_addr + reg);
 101                 break;
 102         case 2:
 103                 *value = readw(mmcfg_virt_addr + reg);
 104                 break;
 105         case 4:
 106                 *value = readl(mmcfg_virt_addr + reg);
 107                 break;
 108         }
 109
 110         spin_unlock_irqrestore(&pci_config_lock, flags);
 111
 112         return 0;
 113 }
 114
 115 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
 116                            unsigned int devfn, int reg, int len, u32 value)
 117 {
 118         unsigned long flags;
 119         u32 base;
 120
 121         if ((bus > 255) || (devfn > 255) || (reg > 4095))
 122                 return -EINVAL;
 123
 124         base = get_base_addr(seg, bus, devfn);
 125         if (!base)
 126                 return pci_conf1_write(seg,bus,devfn,reg,len,value);
 127
 128         spin_lock_irqsave(&pci_config_lock, flags);
 129
 130         pci_exp_set_dev_base(base, bus, devfn);
 131
 132         switch (len) {
 133         case 1:
 134                 writeb(value, mmcfg_virt_addr + reg);
 135                 break;
 136         case 2:
 137                 writew(value, mmcfg_virt_addr + reg);
 138                 break;
 139         case 4:
 140                 writel(value, mmcfg_virt_addr + reg);
 141                 break;
 142         }
 143
 144         spin_unlock_irqrestore(&pci_config_lock, flags);
 145
 146         return 0;
 147 }
 148
 149 static struct pci_raw_ops pci_mmcfg = {
 150         .read =         pci_mmcfg_read,
 151         .write =        pci_mmcfg_write,
 152 };
 153
 154 /* K8 systems have some devices (typically in the builtin northbridge)
 155    that are only accessible using type1
 156    Normally this can be expressed in the MCFG by not listing them
 157    and assigning suitable _SEGs, but this isn't implemented in some BIOS.
 158    Instead try to discover all devices on bus 0 that are unreachable using MM
 159    and fallback for them. */
 160 static __init void unreachable_devices(void)
 161 {
 162         int i, k;
 163         unsigned long flags;
 164
 165         for (k = 0; k < MAX_CHECK_BUS; k++) {
 166                 for (i = 0; i < 32; i++) {
 167                         u32 val1;
 168                         u32 addr;
 169
 170                         pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
 171                         if (val1 == 0xffffffff)
 172                                 continue;
 173
 174                         /* Locking probably not needed, but safer */
 175                         spin_lock_irqsave(&pci_config_lock, flags);
 176                         addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
 177                         if (addr != 0)
 178                                 pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
 179                         if (addr == 0 ||
 180                             readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
 181                                 set_bit(i, fallback_slots);
 182                                 printk(KERN_NOTICE
 183                         "PCI: No mmconfig possible on %x:%x\n", k, i);
 184                         }
 185                         spin_unlock_irqrestore(&pci_config_lock, flags);
 186                 }
 187         }
 188 }
 189
 190 void __init pci_mmcfg_init(void)
 191 {
 192         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 193                 return;
 194
 195         acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
 196         if ((pci_mmcfg_config_num == 0) ||
 197             (pci_mmcfg_config == NULL) ||
 198             (pci_mmcfg_config[0].base_address == 0))
 199                 return;
 200
 201         if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
 202                         pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
 203                         E820_RESERVED)) {
 204                 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
 205                                 pci_mmcfg_config[0].base_address);
 206                 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
 207                 return;
 208         }
 209
 210         printk(KERN_INFO "PCI: Using MMCONFIG\n");
 211         raw_pci_ops = &pci_mmcfg;
 212         pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 213
 214         unreachable_devices();
 215 }