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0e63ee487d6d1315b6f06c069631cb383c932eb7
[deliverable/linux.git] / arch / mips / alchemy / common / dbdma.c
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/init.h>
34 #include <linux/kernel.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/interrupt.h>
38 #include <linux/module.h>
39 #include <linux/syscore_ops.h>
40 #include <asm/mach-au1x00/au1000.h>
41 #include <asm/mach-au1x00/au1xxx_dbdma.h>
42
43 /*
44 * The Descriptor Based DMA supports up to 16 channels.
45 *
46 * There are 32 devices defined. We keep an internal structure
47 * of devices using these channels, along with additional
48 * information.
49 *
50 * We allocate the descriptors and allow access to them through various
51 * functions. The drivers allocate the data buffers and assign them
52 * to the descriptors.
53 */
54 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
55
56 /* I couldn't find a macro that did this... */
57 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
58
59 static dbdma_global_t *dbdma_gptr =
60 (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
61 static int dbdma_initialized;
62
63 static dbdev_tab_t *dbdev_tab;
64
65 static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
66 /* UARTS */
67 { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
68 { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
69 { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
70 { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
71
72 /* EXT DMA */
73 { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
74 { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
75 { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
76 { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
77
78 /* USB DEV */
79 { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
80 { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
81 { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
82 { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
83 { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
84 { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
85
86 /* PSCs */
87 { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
88 { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
89 { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
90 { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
91 { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
92 { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
93 { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
94 { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
95
96 { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
97 { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
98
99 /* MAC 0 */
100 { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
101 { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
102
103 /* MAC 1 */
104 { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
105 { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
106
107 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
108 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
109 };
110
111 static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
112 { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
113 { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
114 { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
115 { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
116
117 { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
118 { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
119
120 { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
121 { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
122 { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
123 { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
124
125 { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
126 { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
127 { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
128 { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
129
130 { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
131 { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
132
133 { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
134 { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
135 { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
136 { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
137 { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
138 { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
139
140 { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
141 { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
142 { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
143 { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
144
145 { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
146
147 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149 };
150
151 /* 32 predefined plus 32 custom */
152 #define DBDEV_TAB_SIZE 64
153
154 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
155
156 static dbdev_tab_t *find_dbdev_id(u32 id)
157 {
158 int i;
159 dbdev_tab_t *p;
160 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
161 p = &dbdev_tab[i];
162 if (p->dev_id == id)
163 return p;
164 }
165 return NULL;
166 }
167
168 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
169 {
170 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
171 }
172 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
173
174 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
175 {
176 u32 ret = 0;
177 dbdev_tab_t *p;
178 static u16 new_id = 0x1000;
179
180 p = find_dbdev_id(~0);
181 if (NULL != p) {
182 memcpy(p, dev, sizeof(dbdev_tab_t));
183 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
184 ret = p->dev_id;
185 new_id++;
186 #if 0
187 printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
188 p->dev_id, p->dev_flags, p->dev_physaddr);
189 #endif
190 }
191
192 return ret;
193 }
194 EXPORT_SYMBOL(au1xxx_ddma_add_device);
195
196 void au1xxx_ddma_del_device(u32 devid)
197 {
198 dbdev_tab_t *p = find_dbdev_id(devid);
199
200 if (p != NULL) {
201 memset(p, 0, sizeof(dbdev_tab_t));
202 p->dev_id = ~0;
203 }
204 }
205 EXPORT_SYMBOL(au1xxx_ddma_del_device);
206
207 /* Allocate a channel and return a non-zero descriptor if successful. */
208 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
209 void (*callback)(int, void *), void *callparam)
210 {
211 unsigned long flags;
212 u32 used, chan;
213 u32 dcp;
214 int i;
215 dbdev_tab_t *stp, *dtp;
216 chan_tab_t *ctp;
217 au1x_dma_chan_t *cp;
218
219 /*
220 * We do the intialization on the first channel allocation.
221 * We have to wait because of the interrupt handler initialization
222 * which can't be done successfully during board set up.
223 */
224 if (!dbdma_initialized)
225 return 0;
226
227 stp = find_dbdev_id(srcid);
228 if (stp == NULL)
229 return 0;
230 dtp = find_dbdev_id(destid);
231 if (dtp == NULL)
232 return 0;
233
234 used = 0;
235
236 /* Check to see if we can get both channels. */
237 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
238 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
239 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
240 /* Got source */
241 stp->dev_flags |= DEV_FLAGS_INUSE;
242 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
243 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
244 /* Got destination */
245 dtp->dev_flags |= DEV_FLAGS_INUSE;
246 } else {
247 /* Can't get dest. Release src. */
248 stp->dev_flags &= ~DEV_FLAGS_INUSE;
249 used++;
250 }
251 } else
252 used++;
253 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
254
255 if (used)
256 return 0;
257
258 /* Let's see if we can allocate a channel for it. */
259 ctp = NULL;
260 chan = 0;
261 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
262 for (i = 0; i < NUM_DBDMA_CHANS; i++)
263 if (chan_tab_ptr[i] == NULL) {
264 /*
265 * If kmalloc fails, it is caught below same
266 * as a channel not available.
267 */
268 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
269 chan_tab_ptr[i] = ctp;
270 break;
271 }
272 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
273
274 if (ctp != NULL) {
275 memset(ctp, 0, sizeof(chan_tab_t));
276 ctp->chan_index = chan = i;
277 dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
278 dcp += (0x0100 * chan);
279 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
280 cp = (au1x_dma_chan_t *)dcp;
281 ctp->chan_src = stp;
282 ctp->chan_dest = dtp;
283 ctp->chan_callback = callback;
284 ctp->chan_callparam = callparam;
285
286 /* Initialize channel configuration. */
287 i = 0;
288 if (stp->dev_intlevel)
289 i |= DDMA_CFG_SED;
290 if (stp->dev_intpolarity)
291 i |= DDMA_CFG_SP;
292 if (dtp->dev_intlevel)
293 i |= DDMA_CFG_DED;
294 if (dtp->dev_intpolarity)
295 i |= DDMA_CFG_DP;
296 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
297 (dtp->dev_flags & DEV_FLAGS_SYNC))
298 i |= DDMA_CFG_SYNC;
299 cp->ddma_cfg = i;
300 au_sync();
301
302 /*
303 * Return a non-zero value that can be used to find the channel
304 * information in subsequent operations.
305 */
306 return (u32)(&chan_tab_ptr[chan]);
307 }
308
309 /* Release devices */
310 stp->dev_flags &= ~DEV_FLAGS_INUSE;
311 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
312
313 return 0;
314 }
315 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
316
317 /*
318 * Set the device width if source or destination is a FIFO.
319 * Should be 8, 16, or 32 bits.
320 */
321 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
322 {
323 u32 rv;
324 chan_tab_t *ctp;
325 dbdev_tab_t *stp, *dtp;
326
327 ctp = *((chan_tab_t **)chanid);
328 stp = ctp->chan_src;
329 dtp = ctp->chan_dest;
330 rv = 0;
331
332 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
333 rv = stp->dev_devwidth;
334 stp->dev_devwidth = bits;
335 }
336 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
337 rv = dtp->dev_devwidth;
338 dtp->dev_devwidth = bits;
339 }
340
341 return rv;
342 }
343 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
344
345 /* Allocate a descriptor ring, initializing as much as possible. */
346 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
347 {
348 int i;
349 u32 desc_base, srcid, destid;
350 u32 cmd0, cmd1, src1, dest1;
351 u32 src0, dest0;
352 chan_tab_t *ctp;
353 dbdev_tab_t *stp, *dtp;
354 au1x_ddma_desc_t *dp;
355
356 /*
357 * I guess we could check this to be within the
358 * range of the table......
359 */
360 ctp = *((chan_tab_t **)chanid);
361 stp = ctp->chan_src;
362 dtp = ctp->chan_dest;
363
364 /*
365 * The descriptors must be 32-byte aligned. There is a
366 * possibility the allocation will give us such an address,
367 * and if we try that first we are likely to not waste larger
368 * slabs of memory.
369 */
370 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
371 GFP_KERNEL|GFP_DMA);
372 if (desc_base == 0)
373 return 0;
374
375 if (desc_base & 0x1f) {
376 /*
377 * Lost....do it again, allocate extra, and round
378 * the address base.
379 */
380 kfree((const void *)desc_base);
381 i = entries * sizeof(au1x_ddma_desc_t);
382 i += (sizeof(au1x_ddma_desc_t) - 1);
383 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
384 if (desc_base == 0)
385 return 0;
386
387 ctp->cdb_membase = desc_base;
388 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
389 } else
390 ctp->cdb_membase = desc_base;
391
392 dp = (au1x_ddma_desc_t *)desc_base;
393
394 /* Keep track of the base descriptor. */
395 ctp->chan_desc_base = dp;
396
397 /* Initialize the rings with as much information as we know. */
398 srcid = stp->dev_id;
399 destid = dtp->dev_id;
400
401 cmd0 = cmd1 = src1 = dest1 = 0;
402 src0 = dest0 = 0;
403
404 cmd0 |= DSCR_CMD0_SID(srcid);
405 cmd0 |= DSCR_CMD0_DID(destid);
406 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
407 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
408
409 /* Is it mem to mem transfer? */
410 if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
411 (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
412 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
413 (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
414 cmd0 |= DSCR_CMD0_MEM;
415
416 switch (stp->dev_devwidth) {
417 case 8:
418 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
419 break;
420 case 16:
421 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
422 break;
423 case 32:
424 default:
425 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
426 break;
427 }
428
429 switch (dtp->dev_devwidth) {
430 case 8:
431 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
432 break;
433 case 16:
434 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
435 break;
436 case 32:
437 default:
438 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
439 break;
440 }
441
442 /*
443 * If the device is marked as an in/out FIFO, ensure it is
444 * set non-coherent.
445 */
446 if (stp->dev_flags & DEV_FLAGS_IN)
447 cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
448 if (dtp->dev_flags & DEV_FLAGS_OUT)
449 cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
450
451 /*
452 * Set up source1. For now, assume no stride and increment.
453 * A channel attribute update can change this later.
454 */
455 switch (stp->dev_tsize) {
456 case 1:
457 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
458 break;
459 case 2:
460 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
461 break;
462 case 4:
463 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
464 break;
465 case 8:
466 default:
467 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
468 break;
469 }
470
471 /* If source input is FIFO, set static address. */
472 if (stp->dev_flags & DEV_FLAGS_IN) {
473 if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
474 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
475 else
476 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
477 }
478
479 if (stp->dev_physaddr)
480 src0 = stp->dev_physaddr;
481
482 /*
483 * Set up dest1. For now, assume no stride and increment.
484 * A channel attribute update can change this later.
485 */
486 switch (dtp->dev_tsize) {
487 case 1:
488 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
489 break;
490 case 2:
491 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
492 break;
493 case 4:
494 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
495 break;
496 case 8:
497 default:
498 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
499 break;
500 }
501
502 /* If destination output is FIFO, set static address. */
503 if (dtp->dev_flags & DEV_FLAGS_OUT) {
504 if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
505 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
506 else
507 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
508 }
509
510 if (dtp->dev_physaddr)
511 dest0 = dtp->dev_physaddr;
512
513 #if 0
514 printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
515 "source1:%x dest0:%x dest1:%x\n",
516 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
517 src1, dest0, dest1);
518 #endif
519 for (i = 0; i < entries; i++) {
520 dp->dscr_cmd0 = cmd0;
521 dp->dscr_cmd1 = cmd1;
522 dp->dscr_source0 = src0;
523 dp->dscr_source1 = src1;
524 dp->dscr_dest0 = dest0;
525 dp->dscr_dest1 = dest1;
526 dp->dscr_stat = 0;
527 dp->sw_context = 0;
528 dp->sw_status = 0;
529 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
530 dp++;
531 }
532
533 /* Make last descrptor point to the first. */
534 dp--;
535 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
536 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
537
538 return (u32)ctp->chan_desc_base;
539 }
540 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
541
542 /*
543 * Put a source buffer into the DMA ring.
544 * This updates the source pointer and byte count. Normally used
545 * for memory to fifo transfers.
546 */
547 u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
548 {
549 chan_tab_t *ctp;
550 au1x_ddma_desc_t *dp;
551
552 /*
553 * I guess we could check this to be within the
554 * range of the table......
555 */
556 ctp = *(chan_tab_t **)chanid;
557
558 /*
559 * We should have multiple callers for a particular channel,
560 * an interrupt doesn't affect this pointer nor the descriptor,
561 * so no locking should be needed.
562 */
563 dp = ctp->put_ptr;
564
565 /*
566 * If the descriptor is valid, we are way ahead of the DMA
567 * engine, so just return an error condition.
568 */
569 if (dp->dscr_cmd0 & DSCR_CMD0_V)
570 return 0;
571
572 /* Load up buffer address and byte count. */
573 dp->dscr_source0 = buf & ~0UL;
574 dp->dscr_cmd1 = nbytes;
575 /* Check flags */
576 if (flags & DDMA_FLAGS_IE)
577 dp->dscr_cmd0 |= DSCR_CMD0_IE;
578 if (flags & DDMA_FLAGS_NOIE)
579 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
580
581 /*
582 * There is an errata on the Au1200/Au1550 parts that could result
583 * in "stale" data being DMA'ed. It has to do with the snoop logic on
584 * the cache eviction buffer. DMA_NONCOHERENT is on by default for
585 * these parts. If it is fixed in the future, these dma_cache_inv will
586 * just be nothing more than empty macros. See io.h.
587 */
588 dma_cache_wback_inv((unsigned long)buf, nbytes);
589 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
590 au_sync();
591 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
592 ctp->chan_ptr->ddma_dbell = 0;
593
594 /* Get next descriptor pointer. */
595 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
596
597 /* Return something non-zero. */
598 return nbytes;
599 }
600 EXPORT_SYMBOL(au1xxx_dbdma_put_source);
601
602 /* Put a destination buffer into the DMA ring.
603 * This updates the destination pointer and byte count. Normally used
604 * to place an empty buffer into the ring for fifo to memory transfers.
605 */
606 u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
607 {
608 chan_tab_t *ctp;
609 au1x_ddma_desc_t *dp;
610
611 /* I guess we could check this to be within the
612 * range of the table......
613 */
614 ctp = *((chan_tab_t **)chanid);
615
616 /* We should have multiple callers for a particular channel,
617 * an interrupt doesn't affect this pointer nor the descriptor,
618 * so no locking should be needed.
619 */
620 dp = ctp->put_ptr;
621
622 /* If the descriptor is valid, we are way ahead of the DMA
623 * engine, so just return an error condition.
624 */
625 if (dp->dscr_cmd0 & DSCR_CMD0_V)
626 return 0;
627
628 /* Load up buffer address and byte count */
629
630 /* Check flags */
631 if (flags & DDMA_FLAGS_IE)
632 dp->dscr_cmd0 |= DSCR_CMD0_IE;
633 if (flags & DDMA_FLAGS_NOIE)
634 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
635
636 dp->dscr_dest0 = buf & ~0UL;
637 dp->dscr_cmd1 = nbytes;
638 #if 0
639 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
640 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
641 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
642 #endif
643 /*
644 * There is an errata on the Au1200/Au1550 parts that could result in
645 * "stale" data being DMA'ed. It has to do with the snoop logic on the
646 * cache eviction buffer. DMA_NONCOHERENT is on by default for these
647 * parts. If it is fixed in the future, these dma_cache_inv will just
648 * be nothing more than empty macros. See io.h.
649 */
650 dma_cache_inv((unsigned long)buf, nbytes);
651 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
652 au_sync();
653 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
654 ctp->chan_ptr->ddma_dbell = 0;
655
656 /* Get next descriptor pointer. */
657 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
658
659 /* Return something non-zero. */
660 return nbytes;
661 }
662 EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
663
664 /*
665 * Get a destination buffer into the DMA ring.
666 * Normally used to get a full buffer from the ring during fifo
667 * to memory transfers. This does not set the valid bit, you will
668 * have to put another destination buffer to keep the DMA going.
669 */
670 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
671 {
672 chan_tab_t *ctp;
673 au1x_ddma_desc_t *dp;
674 u32 rv;
675
676 /*
677 * I guess we could check this to be within the
678 * range of the table......
679 */
680 ctp = *((chan_tab_t **)chanid);
681
682 /*
683 * We should have multiple callers for a particular channel,
684 * an interrupt doesn't affect this pointer nor the descriptor,
685 * so no locking should be needed.
686 */
687 dp = ctp->get_ptr;
688
689 /*
690 * If the descriptor is valid, we are way ahead of the DMA
691 * engine, so just return an error condition.
692 */
693 if (dp->dscr_cmd0 & DSCR_CMD0_V)
694 return 0;
695
696 /* Return buffer address and byte count. */
697 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
698 *nbytes = dp->dscr_cmd1;
699 rv = dp->dscr_stat;
700
701 /* Get next descriptor pointer. */
702 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
703
704 /* Return something non-zero. */
705 return rv;
706 }
707 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
708
709 void au1xxx_dbdma_stop(u32 chanid)
710 {
711 chan_tab_t *ctp;
712 au1x_dma_chan_t *cp;
713 int halt_timeout = 0;
714
715 ctp = *((chan_tab_t **)chanid);
716
717 cp = ctp->chan_ptr;
718 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
719 au_sync();
720 while (!(cp->ddma_stat & DDMA_STAT_H)) {
721 udelay(1);
722 halt_timeout++;
723 if (halt_timeout > 100) {
724 printk(KERN_WARNING "warning: DMA channel won't halt\n");
725 break;
726 }
727 }
728 /* clear current desc valid and doorbell */
729 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
730 au_sync();
731 }
732 EXPORT_SYMBOL(au1xxx_dbdma_stop);
733
734 /*
735 * Start using the current descriptor pointer. If the DBDMA encounters
736 * a non-valid descriptor, it will stop. In this case, we can just
737 * continue by adding a buffer to the list and starting again.
738 */
739 void au1xxx_dbdma_start(u32 chanid)
740 {
741 chan_tab_t *ctp;
742 au1x_dma_chan_t *cp;
743
744 ctp = *((chan_tab_t **)chanid);
745 cp = ctp->chan_ptr;
746 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
747 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
748 au_sync();
749 cp->ddma_dbell = 0;
750 au_sync();
751 }
752 EXPORT_SYMBOL(au1xxx_dbdma_start);
753
754 void au1xxx_dbdma_reset(u32 chanid)
755 {
756 chan_tab_t *ctp;
757 au1x_ddma_desc_t *dp;
758
759 au1xxx_dbdma_stop(chanid);
760
761 ctp = *((chan_tab_t **)chanid);
762 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
763
764 /* Run through the descriptors and reset the valid indicator. */
765 dp = ctp->chan_desc_base;
766
767 do {
768 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
769 /*
770 * Reset our software status -- this is used to determine
771 * if a descriptor is in use by upper level software. Since
772 * posting can reset 'V' bit.
773 */
774 dp->sw_status = 0;
775 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
776 } while (dp != ctp->chan_desc_base);
777 }
778 EXPORT_SYMBOL(au1xxx_dbdma_reset);
779
780 u32 au1xxx_get_dma_residue(u32 chanid)
781 {
782 chan_tab_t *ctp;
783 au1x_dma_chan_t *cp;
784 u32 rv;
785
786 ctp = *((chan_tab_t **)chanid);
787 cp = ctp->chan_ptr;
788
789 /* This is only valid if the channel is stopped. */
790 rv = cp->ddma_bytecnt;
791 au_sync();
792
793 return rv;
794 }
795 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
796
797 void au1xxx_dbdma_chan_free(u32 chanid)
798 {
799 chan_tab_t *ctp;
800 dbdev_tab_t *stp, *dtp;
801
802 ctp = *((chan_tab_t **)chanid);
803 stp = ctp->chan_src;
804 dtp = ctp->chan_dest;
805
806 au1xxx_dbdma_stop(chanid);
807
808 kfree((void *)ctp->cdb_membase);
809
810 stp->dev_flags &= ~DEV_FLAGS_INUSE;
811 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
812 chan_tab_ptr[ctp->chan_index] = NULL;
813
814 kfree(ctp);
815 }
816 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
817
818 static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
819 {
820 u32 intstat;
821 u32 chan_index;
822 chan_tab_t *ctp;
823 au1x_ddma_desc_t *dp;
824 au1x_dma_chan_t *cp;
825
826 intstat = dbdma_gptr->ddma_intstat;
827 au_sync();
828 chan_index = __ffs(intstat);
829
830 ctp = chan_tab_ptr[chan_index];
831 cp = ctp->chan_ptr;
832 dp = ctp->cur_ptr;
833
834 /* Reset interrupt. */
835 cp->ddma_irq = 0;
836 au_sync();
837
838 if (ctp->chan_callback)
839 ctp->chan_callback(irq, ctp->chan_callparam);
840
841 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
842 return IRQ_RETVAL(1);
843 }
844
845 void au1xxx_dbdma_dump(u32 chanid)
846 {
847 chan_tab_t *ctp;
848 au1x_ddma_desc_t *dp;
849 dbdev_tab_t *stp, *dtp;
850 au1x_dma_chan_t *cp;
851 u32 i = 0;
852
853 ctp = *((chan_tab_t **)chanid);
854 stp = ctp->chan_src;
855 dtp = ctp->chan_dest;
856 cp = ctp->chan_ptr;
857
858 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
859 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
860 dtp - dbdev_tab);
861 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
862 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
863 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
864
865 printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
866 printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
867 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
868 printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
869 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
870 cp->ddma_bytecnt);
871
872 /* Run through the descriptors */
873 dp = ctp->chan_desc_base;
874
875 do {
876 printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
877 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
878 printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
879 dp->dscr_source0, dp->dscr_source1,
880 dp->dscr_dest0, dp->dscr_dest1);
881 printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
882 dp->dscr_stat, dp->dscr_nxtptr);
883 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
884 } while (dp != ctp->chan_desc_base);
885 }
886
887 /* Put a descriptor into the DMA ring.
888 * This updates the source/destination pointers and byte count.
889 */
890 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
891 {
892 chan_tab_t *ctp;
893 au1x_ddma_desc_t *dp;
894 u32 nbytes = 0;
895
896 /*
897 * I guess we could check this to be within the
898 * range of the table......
899 */
900 ctp = *((chan_tab_t **)chanid);
901
902 /*
903 * We should have multiple callers for a particular channel,
904 * an interrupt doesn't affect this pointer nor the descriptor,
905 * so no locking should be needed.
906 */
907 dp = ctp->put_ptr;
908
909 /*
910 * If the descriptor is valid, we are way ahead of the DMA
911 * engine, so just return an error condition.
912 */
913 if (dp->dscr_cmd0 & DSCR_CMD0_V)
914 return 0;
915
916 /* Load up buffer addresses and byte count. */
917 dp->dscr_dest0 = dscr->dscr_dest0;
918 dp->dscr_source0 = dscr->dscr_source0;
919 dp->dscr_dest1 = dscr->dscr_dest1;
920 dp->dscr_source1 = dscr->dscr_source1;
921 dp->dscr_cmd1 = dscr->dscr_cmd1;
922 nbytes = dscr->dscr_cmd1;
923 /* Allow the caller to specifiy if an interrupt is generated */
924 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
925 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
926 ctp->chan_ptr->ddma_dbell = 0;
927
928 /* Get next descriptor pointer. */
929 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
930
931 /* Return something non-zero. */
932 return nbytes;
933 }
934
935
936 static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
937
938 static int alchemy_dbdma_suspend(void)
939 {
940 int i;
941 void __iomem *addr;
942
943 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
944 alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
945 alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
946 alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
947 alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
948
949 /* save channel configurations */
950 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
951 for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
952 alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
953 alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
954 alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
955 alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
956 alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
957 alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
958
959 /* halt channel */
960 __raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
961 wmb();
962 while (!(__raw_readl(addr + 0x14) & 1))
963 wmb();
964
965 addr += 0x100; /* next channel base */
966 }
967 /* disable channel interrupts */
968 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
969 __raw_writel(0, addr + 0x0c);
970 wmb();
971
972 return 0;
973 }
974
975 static void alchemy_dbdma_resume(void)
976 {
977 int i;
978 void __iomem *addr;
979
980 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
981 __raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
982 __raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
983 __raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
984 __raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
985
986 /* restore channel configurations */
987 addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
988 for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
989 __raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
990 __raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
991 __raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
992 __raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
993 __raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
994 __raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
995 wmb();
996 addr += 0x100; /* next channel base */
997 }
998 }
999
1000 static struct syscore_ops alchemy_dbdma_syscore_ops = {
1001 .suspend = alchemy_dbdma_suspend,
1002 .resume = alchemy_dbdma_resume,
1003 };
1004
1005 static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
1006 {
1007 int ret;
1008
1009 dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);
1010 if (!dbdev_tab)
1011 return -ENOMEM;
1012
1013 memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
1014 for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
1015 dbdev_tab[ret].dev_id = ~0;
1016
1017 dbdma_gptr->ddma_config = 0;
1018 dbdma_gptr->ddma_throttle = 0;
1019 dbdma_gptr->ddma_inten = 0xffff;
1020 au_sync();
1021
1022 ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",
1023 (void *)dbdma_gptr);
1024 if (ret)
1025 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1026 else {
1027 dbdma_initialized = 1;
1028 register_syscore_ops(&alchemy_dbdma_syscore_ops);
1029 }
1030
1031 return ret;
1032 }
1033
1034 static int __init alchemy_dbdma_init(void)
1035 {
1036 switch (alchemy_get_cputype()) {
1037 case ALCHEMY_CPU_AU1550:
1038 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1039 case ALCHEMY_CPU_AU1200:
1040 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1041 }
1042 return 0;
1043 }
1044 subsys_initcall(alchemy_dbdma_init);
Linux kernel - Deliverables
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