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MIPS: Remove trailing space in messages
[deliverable/linux.git] / arch / mips / alchemy / common / dbdma.c
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/init.h>
34 #include <linux/kernel.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/interrupt.h>
38 #include <linux/module.h>
39 #include <asm/mach-au1x00/au1000.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41
42 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
43
44 /*
45 * The Descriptor Based DMA supports up to 16 channels.
46 *
47 * There are 32 devices defined. We keep an internal structure
48 * of devices using these channels, along with additional
49 * information.
50 *
51 * We allocate the descriptors and allow access to them through various
52 * functions. The drivers allocate the data buffers and assign them
53 * to the descriptors.
54 */
55 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
56
57 /* I couldn't find a macro that did this... */
58 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
59
60 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
61 static int dbdma_initialized;
62
63 static dbdev_tab_t dbdev_tab[] = {
64 #ifdef CONFIG_SOC_AU1550
65 /* UARTS */
66 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
67 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
68 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
69 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
70
71 /* EXT DMA */
72 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
73 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
74 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
75 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
76
77 /* USB DEV */
78 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
79 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
80 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
81 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
82 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
83 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
84
85 /* PSC 0 */
86 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
87 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
88
89 /* PSC 1 */
90 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
91 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
92
93 /* PSC 2 */
94 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
95 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
96
97 /* PSC 3 */
98 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
99 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
100
101 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
102 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
103
104 /* MAC 0 */
105 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
106 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
107
108 /* MAC 1 */
109 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
110 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
111
112 #endif /* CONFIG_SOC_AU1550 */
113
114 #ifdef CONFIG_SOC_AU1200
115 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
116 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
117 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
118 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
119
120 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
121 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
122
123 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
124 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
125 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
126 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
127
128 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
129 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
130 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
131 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
132
133 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
134 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
135
136 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
137 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
138 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
139
140 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
141 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
142 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
143
144 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
145 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
146 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
147 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148
149 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
150
151 #endif /* CONFIG_SOC_AU1200 */
152
153 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
154 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
155
156 /* Provide 16 user definable device types */
157 { ~0, 0, 0, 0, 0, 0, 0 },
158 { ~0, 0, 0, 0, 0, 0, 0 },
159 { ~0, 0, 0, 0, 0, 0, 0 },
160 { ~0, 0, 0, 0, 0, 0, 0 },
161 { ~0, 0, 0, 0, 0, 0, 0 },
162 { ~0, 0, 0, 0, 0, 0, 0 },
163 { ~0, 0, 0, 0, 0, 0, 0 },
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 };
174
175 #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
176
177 #ifdef CONFIG_PM
178 static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6];
179 #endif
180
181
182 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
183
184 static dbdev_tab_t *find_dbdev_id(u32 id)
185 {
186 int i;
187 dbdev_tab_t *p;
188 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
189 p = &dbdev_tab[i];
190 if (p->dev_id == id)
191 return p;
192 }
193 return NULL;
194 }
195
196 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
197 {
198 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
199 }
200 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
201
202 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
203 {
204 u32 ret = 0;
205 dbdev_tab_t *p;
206 static u16 new_id = 0x1000;
207
208 p = find_dbdev_id(~0);
209 if (NULL != p) {
210 memcpy(p, dev, sizeof(dbdev_tab_t));
211 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
212 ret = p->dev_id;
213 new_id++;
214 #if 0
215 printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
216 p->dev_id, p->dev_flags, p->dev_physaddr);
217 #endif
218 }
219
220 return ret;
221 }
222 EXPORT_SYMBOL(au1xxx_ddma_add_device);
223
224 void au1xxx_ddma_del_device(u32 devid)
225 {
226 dbdev_tab_t *p = find_dbdev_id(devid);
227
228 if (p != NULL) {
229 memset(p, 0, sizeof(dbdev_tab_t));
230 p->dev_id = ~0;
231 }
232 }
233 EXPORT_SYMBOL(au1xxx_ddma_del_device);
234
235 /* Allocate a channel and return a non-zero descriptor if successful. */
236 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
237 void (*callback)(int, void *), void *callparam)
238 {
239 unsigned long flags;
240 u32 used, chan, rv;
241 u32 dcp;
242 int i;
243 dbdev_tab_t *stp, *dtp;
244 chan_tab_t *ctp;
245 au1x_dma_chan_t *cp;
246
247 /*
248 * We do the intialization on the first channel allocation.
249 * We have to wait because of the interrupt handler initialization
250 * which can't be done successfully during board set up.
251 */
252 if (!dbdma_initialized)
253 return 0;
254
255 stp = find_dbdev_id(srcid);
256 if (stp == NULL)
257 return 0;
258 dtp = find_dbdev_id(destid);
259 if (dtp == NULL)
260 return 0;
261
262 used = 0;
263 rv = 0;
264
265 /* Check to see if we can get both channels. */
266 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
267 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
268 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
269 /* Got source */
270 stp->dev_flags |= DEV_FLAGS_INUSE;
271 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
272 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
273 /* Got destination */
274 dtp->dev_flags |= DEV_FLAGS_INUSE;
275 } else {
276 /* Can't get dest. Release src. */
277 stp->dev_flags &= ~DEV_FLAGS_INUSE;
278 used++;
279 }
280 } else
281 used++;
282 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
283
284 if (!used) {
285 /* Let's see if we can allocate a channel for it. */
286 ctp = NULL;
287 chan = 0;
288 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
289 for (i = 0; i < NUM_DBDMA_CHANS; i++)
290 if (chan_tab_ptr[i] == NULL) {
291 /*
292 * If kmalloc fails, it is caught below same
293 * as a channel not available.
294 */
295 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
296 chan_tab_ptr[i] = ctp;
297 break;
298 }
299 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
300
301 if (ctp != NULL) {
302 memset(ctp, 0, sizeof(chan_tab_t));
303 ctp->chan_index = chan = i;
304 dcp = DDMA_CHANNEL_BASE;
305 dcp += (0x0100 * chan);
306 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
307 cp = (au1x_dma_chan_t *)dcp;
308 ctp->chan_src = stp;
309 ctp->chan_dest = dtp;
310 ctp->chan_callback = callback;
311 ctp->chan_callparam = callparam;
312
313 /* Initialize channel configuration. */
314 i = 0;
315 if (stp->dev_intlevel)
316 i |= DDMA_CFG_SED;
317 if (stp->dev_intpolarity)
318 i |= DDMA_CFG_SP;
319 if (dtp->dev_intlevel)
320 i |= DDMA_CFG_DED;
321 if (dtp->dev_intpolarity)
322 i |= DDMA_CFG_DP;
323 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
324 (dtp->dev_flags & DEV_FLAGS_SYNC))
325 i |= DDMA_CFG_SYNC;
326 cp->ddma_cfg = i;
327 au_sync();
328
329 /* Return a non-zero value that can be used to
330 * find the channel information in subsequent
331 * operations.
332 */
333 rv = (u32)(&chan_tab_ptr[chan]);
334 } else {
335 /* Release devices */
336 stp->dev_flags &= ~DEV_FLAGS_INUSE;
337 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
338 }
339 }
340 return rv;
341 }
342 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
343
344 /*
345 * Set the device width if source or destination is a FIFO.
346 * Should be 8, 16, or 32 bits.
347 */
348 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
349 {
350 u32 rv;
351 chan_tab_t *ctp;
352 dbdev_tab_t *stp, *dtp;
353
354 ctp = *((chan_tab_t **)chanid);
355 stp = ctp->chan_src;
356 dtp = ctp->chan_dest;
357 rv = 0;
358
359 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
360 rv = stp->dev_devwidth;
361 stp->dev_devwidth = bits;
362 }
363 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
364 rv = dtp->dev_devwidth;
365 dtp->dev_devwidth = bits;
366 }
367
368 return rv;
369 }
370 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
371
372 /* Allocate a descriptor ring, initializing as much as possible. */
373 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
374 {
375 int i;
376 u32 desc_base, srcid, destid;
377 u32 cmd0, cmd1, src1, dest1;
378 u32 src0, dest0;
379 chan_tab_t *ctp;
380 dbdev_tab_t *stp, *dtp;
381 au1x_ddma_desc_t *dp;
382
383 /*
384 * I guess we could check this to be within the
385 * range of the table......
386 */
387 ctp = *((chan_tab_t **)chanid);
388 stp = ctp->chan_src;
389 dtp = ctp->chan_dest;
390
391 /*
392 * The descriptors must be 32-byte aligned. There is a
393 * possibility the allocation will give us such an address,
394 * and if we try that first we are likely to not waste larger
395 * slabs of memory.
396 */
397 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
398 GFP_KERNEL|GFP_DMA);
399 if (desc_base == 0)
400 return 0;
401
402 if (desc_base & 0x1f) {
403 /*
404 * Lost....do it again, allocate extra, and round
405 * the address base.
406 */
407 kfree((const void *)desc_base);
408 i = entries * sizeof(au1x_ddma_desc_t);
409 i += (sizeof(au1x_ddma_desc_t) - 1);
410 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
411 if (desc_base == 0)
412 return 0;
413
414 ctp->cdb_membase = desc_base;
415 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
416 } else
417 ctp->cdb_membase = desc_base;
418
419 dp = (au1x_ddma_desc_t *)desc_base;
420
421 /* Keep track of the base descriptor. */
422 ctp->chan_desc_base = dp;
423
424 /* Initialize the rings with as much information as we know. */
425 srcid = stp->dev_id;
426 destid = dtp->dev_id;
427
428 cmd0 = cmd1 = src1 = dest1 = 0;
429 src0 = dest0 = 0;
430
431 cmd0 |= DSCR_CMD0_SID(srcid);
432 cmd0 |= DSCR_CMD0_DID(destid);
433 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
434 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
435
436 /* Is it mem to mem transfer? */
437 if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
438 (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
439 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
440 (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
441 cmd0 |= DSCR_CMD0_MEM;
442
443 switch (stp->dev_devwidth) {
444 case 8:
445 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
446 break;
447 case 16:
448 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
449 break;
450 case 32:
451 default:
452 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
453 break;
454 }
455
456 switch (dtp->dev_devwidth) {
457 case 8:
458 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
459 break;
460 case 16:
461 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
462 break;
463 case 32:
464 default:
465 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
466 break;
467 }
468
469 /*
470 * If the device is marked as an in/out FIFO, ensure it is
471 * set non-coherent.
472 */
473 if (stp->dev_flags & DEV_FLAGS_IN)
474 cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
475 if (dtp->dev_flags & DEV_FLAGS_OUT)
476 cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
477
478 /*
479 * Set up source1. For now, assume no stride and increment.
480 * A channel attribute update can change this later.
481 */
482 switch (stp->dev_tsize) {
483 case 1:
484 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
485 break;
486 case 2:
487 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
488 break;
489 case 4:
490 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
491 break;
492 case 8:
493 default:
494 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
495 break;
496 }
497
498 /* If source input is FIFO, set static address. */
499 if (stp->dev_flags & DEV_FLAGS_IN) {
500 if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
501 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
502 else
503 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
504 }
505
506 if (stp->dev_physaddr)
507 src0 = stp->dev_physaddr;
508
509 /*
510 * Set up dest1. For now, assume no stride and increment.
511 * A channel attribute update can change this later.
512 */
513 switch (dtp->dev_tsize) {
514 case 1:
515 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
516 break;
517 case 2:
518 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
519 break;
520 case 4:
521 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
522 break;
523 case 8:
524 default:
525 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
526 break;
527 }
528
529 /* If destination output is FIFO, set static address. */
530 if (dtp->dev_flags & DEV_FLAGS_OUT) {
531 if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
532 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
533 else
534 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
535 }
536
537 if (dtp->dev_physaddr)
538 dest0 = dtp->dev_physaddr;
539
540 #if 0
541 printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
542 "source1:%x dest0:%x dest1:%x\n",
543 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
544 src1, dest0, dest1);
545 #endif
546 for (i = 0; i < entries; i++) {
547 dp->dscr_cmd0 = cmd0;
548 dp->dscr_cmd1 = cmd1;
549 dp->dscr_source0 = src0;
550 dp->dscr_source1 = src1;
551 dp->dscr_dest0 = dest0;
552 dp->dscr_dest1 = dest1;
553 dp->dscr_stat = 0;
554 dp->sw_context = 0;
555 dp->sw_status = 0;
556 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
557 dp++;
558 }
559
560 /* Make last descrptor point to the first. */
561 dp--;
562 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
563 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
564
565 return (u32)ctp->chan_desc_base;
566 }
567 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
568
569 /*
570 * Put a source buffer into the DMA ring.
571 * This updates the source pointer and byte count. Normally used
572 * for memory to fifo transfers.
573 */
574 u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
575 {
576 chan_tab_t *ctp;
577 au1x_ddma_desc_t *dp;
578
579 /*
580 * I guess we could check this to be within the
581 * range of the table......
582 */
583 ctp = *(chan_tab_t **)chanid;
584
585 /*
586 * We should have multiple callers for a particular channel,
587 * an interrupt doesn't affect this pointer nor the descriptor,
588 * so no locking should be needed.
589 */
590 dp = ctp->put_ptr;
591
592 /*
593 * If the descriptor is valid, we are way ahead of the DMA
594 * engine, so just return an error condition.
595 */
596 if (dp->dscr_cmd0 & DSCR_CMD0_V)
597 return 0;
598
599 /* Load up buffer address and byte count. */
600 dp->dscr_source0 = buf & ~0UL;
601 dp->dscr_cmd1 = nbytes;
602 /* Check flags */
603 if (flags & DDMA_FLAGS_IE)
604 dp->dscr_cmd0 |= DSCR_CMD0_IE;
605 if (flags & DDMA_FLAGS_NOIE)
606 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
607
608 /*
609 * There is an errata on the Au1200/Au1550 parts that could result
610 * in "stale" data being DMA'ed. It has to do with the snoop logic on
611 * the cache eviction buffer. DMA_NONCOHERENT is on by default for
612 * these parts. If it is fixed in the future, these dma_cache_inv will
613 * just be nothing more than empty macros. See io.h.
614 */
615 dma_cache_wback_inv((unsigned long)buf, nbytes);
616 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
617 au_sync();
618 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
619 ctp->chan_ptr->ddma_dbell = 0;
620
621 /* Get next descriptor pointer. */
622 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
623
624 /* Return something non-zero. */
625 return nbytes;
626 }
627 EXPORT_SYMBOL(au1xxx_dbdma_put_source);
628
629 /* Put a destination buffer into the DMA ring.
630 * This updates the destination pointer and byte count. Normally used
631 * to place an empty buffer into the ring for fifo to memory transfers.
632 */
633 u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
634 {
635 chan_tab_t *ctp;
636 au1x_ddma_desc_t *dp;
637
638 /* I guess we could check this to be within the
639 * range of the table......
640 */
641 ctp = *((chan_tab_t **)chanid);
642
643 /* We should have multiple callers for a particular channel,
644 * an interrupt doesn't affect this pointer nor the descriptor,
645 * so no locking should be needed.
646 */
647 dp = ctp->put_ptr;
648
649 /* If the descriptor is valid, we are way ahead of the DMA
650 * engine, so just return an error condition.
651 */
652 if (dp->dscr_cmd0 & DSCR_CMD0_V)
653 return 0;
654
655 /* Load up buffer address and byte count */
656
657 /* Check flags */
658 if (flags & DDMA_FLAGS_IE)
659 dp->dscr_cmd0 |= DSCR_CMD0_IE;
660 if (flags & DDMA_FLAGS_NOIE)
661 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
662
663 dp->dscr_dest0 = buf & ~0UL;
664 dp->dscr_cmd1 = nbytes;
665 #if 0
666 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
667 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
668 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
669 #endif
670 /*
671 * There is an errata on the Au1200/Au1550 parts that could result in
672 * "stale" data being DMA'ed. It has to do with the snoop logic on the
673 * cache eviction buffer. DMA_NONCOHERENT is on by default for these
674 * parts. If it is fixed in the future, these dma_cache_inv will just
675 * be nothing more than empty macros. See io.h.
676 */
677 dma_cache_inv((unsigned long)buf, nbytes);
678 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
679 au_sync();
680 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
681 ctp->chan_ptr->ddma_dbell = 0;
682
683 /* Get next descriptor pointer. */
684 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
685
686 /* Return something non-zero. */
687 return nbytes;
688 }
689 EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
690
691 /*
692 * Get a destination buffer into the DMA ring.
693 * Normally used to get a full buffer from the ring during fifo
694 * to memory transfers. This does not set the valid bit, you will
695 * have to put another destination buffer to keep the DMA going.
696 */
697 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
698 {
699 chan_tab_t *ctp;
700 au1x_ddma_desc_t *dp;
701 u32 rv;
702
703 /*
704 * I guess we could check this to be within the
705 * range of the table......
706 */
707 ctp = *((chan_tab_t **)chanid);
708
709 /*
710 * We should have multiple callers for a particular channel,
711 * an interrupt doesn't affect this pointer nor the descriptor,
712 * so no locking should be needed.
713 */
714 dp = ctp->get_ptr;
715
716 /*
717 * If the descriptor is valid, we are way ahead of the DMA
718 * engine, so just return an error condition.
719 */
720 if (dp->dscr_cmd0 & DSCR_CMD0_V)
721 return 0;
722
723 /* Return buffer address and byte count. */
724 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
725 *nbytes = dp->dscr_cmd1;
726 rv = dp->dscr_stat;
727
728 /* Get next descriptor pointer. */
729 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
730
731 /* Return something non-zero. */
732 return rv;
733 }
734 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
735
736 void au1xxx_dbdma_stop(u32 chanid)
737 {
738 chan_tab_t *ctp;
739 au1x_dma_chan_t *cp;
740 int halt_timeout = 0;
741
742 ctp = *((chan_tab_t **)chanid);
743
744 cp = ctp->chan_ptr;
745 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
746 au_sync();
747 while (!(cp->ddma_stat & DDMA_STAT_H)) {
748 udelay(1);
749 halt_timeout++;
750 if (halt_timeout > 100) {
751 printk(KERN_WARNING "warning: DMA channel won't halt\n");
752 break;
753 }
754 }
755 /* clear current desc valid and doorbell */
756 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
757 au_sync();
758 }
759 EXPORT_SYMBOL(au1xxx_dbdma_stop);
760
761 /*
762 * Start using the current descriptor pointer. If the DBDMA encounters
763 * a non-valid descriptor, it will stop. In this case, we can just
764 * continue by adding a buffer to the list and starting again.
765 */
766 void au1xxx_dbdma_start(u32 chanid)
767 {
768 chan_tab_t *ctp;
769 au1x_dma_chan_t *cp;
770
771 ctp = *((chan_tab_t **)chanid);
772 cp = ctp->chan_ptr;
773 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
774 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
775 au_sync();
776 cp->ddma_dbell = 0;
777 au_sync();
778 }
779 EXPORT_SYMBOL(au1xxx_dbdma_start);
780
781 void au1xxx_dbdma_reset(u32 chanid)
782 {
783 chan_tab_t *ctp;
784 au1x_ddma_desc_t *dp;
785
786 au1xxx_dbdma_stop(chanid);
787
788 ctp = *((chan_tab_t **)chanid);
789 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
790
791 /* Run through the descriptors and reset the valid indicator. */
792 dp = ctp->chan_desc_base;
793
794 do {
795 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
796 /*
797 * Reset our software status -- this is used to determine
798 * if a descriptor is in use by upper level software. Since
799 * posting can reset 'V' bit.
800 */
801 dp->sw_status = 0;
802 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
803 } while (dp != ctp->chan_desc_base);
804 }
805 EXPORT_SYMBOL(au1xxx_dbdma_reset);
806
807 u32 au1xxx_get_dma_residue(u32 chanid)
808 {
809 chan_tab_t *ctp;
810 au1x_dma_chan_t *cp;
811 u32 rv;
812
813 ctp = *((chan_tab_t **)chanid);
814 cp = ctp->chan_ptr;
815
816 /* This is only valid if the channel is stopped. */
817 rv = cp->ddma_bytecnt;
818 au_sync();
819
820 return rv;
821 }
822 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
823
824 void au1xxx_dbdma_chan_free(u32 chanid)
825 {
826 chan_tab_t *ctp;
827 dbdev_tab_t *stp, *dtp;
828
829 ctp = *((chan_tab_t **)chanid);
830 stp = ctp->chan_src;
831 dtp = ctp->chan_dest;
832
833 au1xxx_dbdma_stop(chanid);
834
835 kfree((void *)ctp->cdb_membase);
836
837 stp->dev_flags &= ~DEV_FLAGS_INUSE;
838 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
839 chan_tab_ptr[ctp->chan_index] = NULL;
840
841 kfree(ctp);
842 }
843 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
844
845 static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
846 {
847 u32 intstat;
848 u32 chan_index;
849 chan_tab_t *ctp;
850 au1x_ddma_desc_t *dp;
851 au1x_dma_chan_t *cp;
852
853 intstat = dbdma_gptr->ddma_intstat;
854 au_sync();
855 chan_index = __ffs(intstat);
856
857 ctp = chan_tab_ptr[chan_index];
858 cp = ctp->chan_ptr;
859 dp = ctp->cur_ptr;
860
861 /* Reset interrupt. */
862 cp->ddma_irq = 0;
863 au_sync();
864
865 if (ctp->chan_callback)
866 ctp->chan_callback(irq, ctp->chan_callparam);
867
868 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
869 return IRQ_RETVAL(1);
870 }
871
872 void au1xxx_dbdma_dump(u32 chanid)
873 {
874 chan_tab_t *ctp;
875 au1x_ddma_desc_t *dp;
876 dbdev_tab_t *stp, *dtp;
877 au1x_dma_chan_t *cp;
878 u32 i = 0;
879
880 ctp = *((chan_tab_t **)chanid);
881 stp = ctp->chan_src;
882 dtp = ctp->chan_dest;
883 cp = ctp->chan_ptr;
884
885 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
886 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
887 dtp - dbdev_tab);
888 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
889 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
890 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
891
892 printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
893 printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
894 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
895 printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
896 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
897 cp->ddma_bytecnt);
898
899 /* Run through the descriptors */
900 dp = ctp->chan_desc_base;
901
902 do {
903 printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
904 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
905 printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
906 dp->dscr_source0, dp->dscr_source1,
907 dp->dscr_dest0, dp->dscr_dest1);
908 printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
909 dp->dscr_stat, dp->dscr_nxtptr);
910 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
911 } while (dp != ctp->chan_desc_base);
912 }
913
914 /* Put a descriptor into the DMA ring.
915 * This updates the source/destination pointers and byte count.
916 */
917 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
918 {
919 chan_tab_t *ctp;
920 au1x_ddma_desc_t *dp;
921 u32 nbytes = 0;
922
923 /*
924 * I guess we could check this to be within the
925 * range of the table......
926 */
927 ctp = *((chan_tab_t **)chanid);
928
929 /*
930 * We should have multiple callers for a particular channel,
931 * an interrupt doesn't affect this pointer nor the descriptor,
932 * so no locking should be needed.
933 */
934 dp = ctp->put_ptr;
935
936 /*
937 * If the descriptor is valid, we are way ahead of the DMA
938 * engine, so just return an error condition.
939 */
940 if (dp->dscr_cmd0 & DSCR_CMD0_V)
941 return 0;
942
943 /* Load up buffer addresses and byte count. */
944 dp->dscr_dest0 = dscr->dscr_dest0;
945 dp->dscr_source0 = dscr->dscr_source0;
946 dp->dscr_dest1 = dscr->dscr_dest1;
947 dp->dscr_source1 = dscr->dscr_source1;
948 dp->dscr_cmd1 = dscr->dscr_cmd1;
949 nbytes = dscr->dscr_cmd1;
950 /* Allow the caller to specifiy if an interrupt is generated */
951 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
952 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
953 ctp->chan_ptr->ddma_dbell = 0;
954
955 /* Get next descriptor pointer. */
956 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
957
958 /* Return something non-zero. */
959 return nbytes;
960 }
961
962 #ifdef CONFIG_PM
963 void au1xxx_dbdma_suspend(void)
964 {
965 int i;
966 u32 addr;
967
968 addr = DDMA_GLOBAL_BASE;
969 au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00);
970 au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04);
971 au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08);
972 au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c);
973
974 /* save channel configurations */
975 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
976 au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00);
977 au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04);
978 au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08);
979 au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c);
980 au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10);
981 au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14);
982
983 /* halt channel */
984 au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00);
985 au_sync();
986 while (!(au_readl(addr + 0x14) & 1))
987 au_sync();
988
989 addr += 0x100; /* next channel base */
990 }
991 /* disable channel interrupts */
992 au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
993 au_sync();
994 }
995
996 void au1xxx_dbdma_resume(void)
997 {
998 int i;
999 u32 addr;
1000
1001 addr = DDMA_GLOBAL_BASE;
1002 au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00);
1003 au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04);
1004 au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08);
1005 au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c);
1006
1007 /* restore channel configurations */
1008 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
1009 au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00);
1010 au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04);
1011 au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08);
1012 au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c);
1013 au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10);
1014 au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14);
1015 au_sync();
1016 addr += 0x100; /* next channel base */
1017 }
1018 }
1019 #endif /* CONFIG_PM */
1020
1021 static int __init au1xxx_dbdma_init(void)
1022 {
1023 int irq_nr, ret;
1024
1025 dbdma_gptr->ddma_config = 0;
1026 dbdma_gptr->ddma_throttle = 0;
1027 dbdma_gptr->ddma_inten = 0xffff;
1028 au_sync();
1029
1030 switch (alchemy_get_cputype()) {
1031 case ALCHEMY_CPU_AU1550:
1032 irq_nr = AU1550_DDMA_INT;
1033 break;
1034 case ALCHEMY_CPU_AU1200:
1035 irq_nr = AU1200_DDMA_INT;
1036 break;
1037 default:
1038 return -ENODEV;
1039 }
1040
1041 ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
1042 "Au1xxx dbdma", (void *)dbdma_gptr);
1043 if (ret)
1044 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1045 else {
1046 dbdma_initialized = 1;
1047 printk(KERN_INFO "Alchemy DBDMA initialized\n");
1048 }
1049
1050 return ret;
1051 }
1052 subsys_initcall(au1xxx_dbdma_init);
1053
1054 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
Linux kernel - Deliverables
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