2 * BRIEF MODULE DESCRIPTION
3 * Au1000 interrupt routines.
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <linux/config.h>
30 #include <linux/errno.h>
31 #include <linux/init.h>
32 #include <linux/irq.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/module.h>
35 #include <linux/signal.h>
36 #include <linux/sched.h>
37 #include <linux/types.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/timex.h>
41 #include <linux/slab.h>
42 #include <linux/random.h>
43 #include <linux/delay.h>
44 #include <linux/bitops.h>
46 #include <asm/bootinfo.h>
48 #include <asm/mipsregs.h>
49 #include <asm/system.h>
50 #include <asm/mach-au1x00/au1000.h>
51 #ifdef CONFIG_MIPS_PB1000
52 #include <asm/mach-pb1x00/pb1000.h>
57 /* note: prints function name for you */
58 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
60 #define DPRINTK(fmt, args...)
63 #define EXT_INTC0_REQ0 2 /* IP 2 */
64 #define EXT_INTC0_REQ1 3 /* IP 3 */
65 #define EXT_INTC1_REQ0 4 /* IP 4 */
66 #define EXT_INTC1_REQ1 5 /* IP 5 */
67 #define MIPS_TIMER_IP 7 /* IP 7 */
69 extern asmlinkage
void au1000_IRQ(void);
70 extern void set_debug_traps(void);
71 extern irq_cpustat_t irq_stat
[NR_CPUS
];
73 static void setup_local_irq(unsigned int irq
, int type
, int int_req
);
74 static unsigned int startup_irq(unsigned int irq
);
75 static void end_irq(unsigned int irq_nr
);
76 static inline void mask_and_ack_level_irq(unsigned int irq_nr
);
77 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr
);
78 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr
);
79 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr
);
80 inline void local_enable_irq(unsigned int irq_nr
);
81 inline void local_disable_irq(unsigned int irq_nr
);
83 void (*board_init_irq
)(void);
86 extern irqreturn_t
counter0_irq(int irq
, void *dev_id
, struct pt_regs
*regs
);
89 static DEFINE_SPINLOCK(irq_lock
);
92 static unsigned int startup_irq(unsigned int irq_nr
)
94 local_enable_irq(irq_nr
);
99 static void shutdown_irq(unsigned int irq_nr
)
101 local_disable_irq(irq_nr
);
106 inline void local_enable_irq(unsigned int irq_nr
)
108 if (irq_nr
> AU1000_LAST_INTC0_INT
) {
109 au_writel(1<<(irq_nr
-32), IC1_MASKSET
);
110 au_writel(1<<(irq_nr
-32), IC1_WAKESET
);
113 au_writel(1<<irq_nr
, IC0_MASKSET
);
114 au_writel(1<<irq_nr
, IC0_WAKESET
);
120 inline void local_disable_irq(unsigned int irq_nr
)
122 if (irq_nr
> AU1000_LAST_INTC0_INT
) {
123 au_writel(1<<(irq_nr
-32), IC1_MASKCLR
);
124 au_writel(1<<(irq_nr
-32), IC1_WAKECLR
);
127 au_writel(1<<irq_nr
, IC0_MASKCLR
);
128 au_writel(1<<irq_nr
, IC0_WAKECLR
);
134 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr
)
136 if (irq_nr
> AU1000_LAST_INTC0_INT
) {
137 au_writel(1<<(irq_nr
-32), IC1_RISINGCLR
);
138 au_writel(1<<(irq_nr
-32), IC1_MASKCLR
);
141 au_writel(1<<irq_nr
, IC0_RISINGCLR
);
142 au_writel(1<<irq_nr
, IC0_MASKCLR
);
148 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr
)
150 if (irq_nr
> AU1000_LAST_INTC0_INT
) {
151 au_writel(1<<(irq_nr
-32), IC1_FALLINGCLR
);
152 au_writel(1<<(irq_nr
-32), IC1_MASKCLR
);
155 au_writel(1<<irq_nr
, IC0_FALLINGCLR
);
156 au_writel(1<<irq_nr
, IC0_MASKCLR
);
162 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr
)
164 /* This may assume that we don't get interrupts from
165 * both edges at once, or if we do, that we don't care.
167 if (irq_nr
> AU1000_LAST_INTC0_INT
) {
168 au_writel(1<<(irq_nr
-32), IC1_FALLINGCLR
);
169 au_writel(1<<(irq_nr
-32), IC1_RISINGCLR
);
170 au_writel(1<<(irq_nr
-32), IC1_MASKCLR
);
173 au_writel(1<<irq_nr
, IC0_FALLINGCLR
);
174 au_writel(1<<irq_nr
, IC0_RISINGCLR
);
175 au_writel(1<<irq_nr
, IC0_MASKCLR
);
181 static inline void mask_and_ack_level_irq(unsigned int irq_nr
)
184 local_disable_irq(irq_nr
);
186 #if defined(CONFIG_MIPS_PB1000)
187 if (irq_nr
== AU1000_GPIO_15
) {
188 au_writel(0x8000, PB1000_MDR
); /* ack int */
196 static void end_irq(unsigned int irq_nr
)
198 if (!(irq_desc
[irq_nr
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
))) {
199 local_enable_irq(irq_nr
);
201 #if defined(CONFIG_MIPS_PB1000)
202 if (irq_nr
== AU1000_GPIO_15
) {
203 au_writel(0x4000, PB1000_MDR
); /* enable int */
209 unsigned long save_local_and_disable(int controller
)
212 unsigned long flags
, mask
;
214 spin_lock_irqsave(&irq_lock
, flags
);
216 mask
= au_readl(IC1_MASKSET
);
217 for (i
=32; i
<64; i
++) {
218 local_disable_irq(i
);
222 mask
= au_readl(IC0_MASKSET
);
223 for (i
=0; i
<32; i
++) {
224 local_disable_irq(i
);
227 spin_unlock_irqrestore(&irq_lock
, flags
);
232 void restore_local_and_enable(int controller
, unsigned long mask
)
235 unsigned long flags
, new_mask
;
237 spin_lock_irqsave(&irq_lock
, flags
);
238 for (i
=0; i
<32; i
++) {
241 local_enable_irq(i
+32);
247 new_mask
= au_readl(IC1_MASKSET
);
249 new_mask
= au_readl(IC0_MASKSET
);
251 spin_unlock_irqrestore(&irq_lock
, flags
);
255 static struct hw_interrupt_type rise_edge_irq_type
= {
256 .typename
= "Au1000 Rise Edge",
257 .startup
= startup_irq
,
258 .shutdown
= shutdown_irq
,
259 .enable
= local_enable_irq
,
260 .disable
= local_disable_irq
,
261 .ack
= mask_and_ack_rise_edge_irq
,
265 static struct hw_interrupt_type fall_edge_irq_type
= {
266 .typename
= "Au1000 Fall Edge",
267 .startup
= startup_irq
,
268 .shutdown
= shutdown_irq
,
269 .enable
= local_enable_irq
,
270 .disable
= local_disable_irq
,
271 .ack
= mask_and_ack_fall_edge_irq
,
275 static struct hw_interrupt_type either_edge_irq_type
= {
276 .typename
= "Au1000 Rise or Fall Edge",
277 .startup
= startup_irq
,
278 .shutdown
= shutdown_irq
,
279 .enable
= local_enable_irq
,
280 .disable
= local_disable_irq
,
281 .ack
= mask_and_ack_either_edge_irq
,
285 static struct hw_interrupt_type level_irq_type
= {
286 .typename
= "Au1000 Level",
287 .startup
= startup_irq
,
288 .shutdown
= shutdown_irq
,
289 .enable
= local_enable_irq
,
290 .disable
= local_disable_irq
,
291 .ack
= mask_and_ack_level_irq
,
296 void startup_match20_interrupt(irqreturn_t (*handler
)(int, void *, struct pt_regs
*))
298 struct irq_desc
*desc
= &irq_desc
[AU1000_TOY_MATCH2_INT
];
300 static struct irqaction action
;
301 memset(&action
, 0, sizeof(struct irqaction
));
303 /* This is a big problem.... since we didn't use request_irq
304 * when kernel/irq.c calls probe_irq_xxx this interrupt will
305 * be probed for usage. This will end up disabling the device :(
306 * Give it a bogus "action" pointer -- this will keep it from
307 * getting auto-probed!
309 * By setting the status to match that of request_irq() we
310 * can avoid it. --cgray
312 action
.dev_id
= handler
;
313 action
.flags
= SA_INTERRUPT
;
314 cpus_clear(action
.mask
);
315 action
.name
= "Au1xxx TOY";
316 action
.handler
= handler
;
319 desc
->action
= &action
;
320 desc
->status
&= ~(IRQ_DISABLED
| IRQ_AUTODETECT
| IRQ_WAITING
| IRQ_INPROGRESS
);
322 local_enable_irq(AU1000_TOY_MATCH2_INT
);
326 static void setup_local_irq(unsigned int irq_nr
, int type
, int int_req
)
328 if (irq_nr
> AU1000_MAX_INTR
) return;
329 /* Config2[n], Config1[n], Config0[n] */
330 if (irq_nr
> AU1000_LAST_INTC0_INT
) {
332 case INTC_INT_RISE_EDGE
: /* 0:0:1 */
333 au_writel(1<<(irq_nr
-32), IC1_CFG2CLR
);
334 au_writel(1<<(irq_nr
-32), IC1_CFG1CLR
);
335 au_writel(1<<(irq_nr
-32), IC1_CFG0SET
);
336 irq_desc
[irq_nr
].handler
= &rise_edge_irq_type
;
338 case INTC_INT_FALL_EDGE
: /* 0:1:0 */
339 au_writel(1<<(irq_nr
-32), IC1_CFG2CLR
);
340 au_writel(1<<(irq_nr
-32), IC1_CFG1SET
);
341 au_writel(1<<(irq_nr
-32), IC1_CFG0CLR
);
342 irq_desc
[irq_nr
].handler
= &fall_edge_irq_type
;
344 case INTC_INT_RISE_AND_FALL_EDGE
: /* 0:1:1 */
345 au_writel(1<<(irq_nr
-32), IC1_CFG2CLR
);
346 au_writel(1<<(irq_nr
-32), IC1_CFG1SET
);
347 au_writel(1<<(irq_nr
-32), IC1_CFG0SET
);
348 irq_desc
[irq_nr
].handler
= &either_edge_irq_type
;
350 case INTC_INT_HIGH_LEVEL
: /* 1:0:1 */
351 au_writel(1<<(irq_nr
-32), IC1_CFG2SET
);
352 au_writel(1<<(irq_nr
-32), IC1_CFG1CLR
);
353 au_writel(1<<(irq_nr
-32), IC1_CFG0SET
);
354 irq_desc
[irq_nr
].handler
= &level_irq_type
;
356 case INTC_INT_LOW_LEVEL
: /* 1:1:0 */
357 au_writel(1<<(irq_nr
-32), IC1_CFG2SET
);
358 au_writel(1<<(irq_nr
-32), IC1_CFG1SET
);
359 au_writel(1<<(irq_nr
-32), IC1_CFG0CLR
);
360 irq_desc
[irq_nr
].handler
= &level_irq_type
;
362 case INTC_INT_DISABLED
: /* 0:0:0 */
363 au_writel(1<<(irq_nr
-32), IC1_CFG0CLR
);
364 au_writel(1<<(irq_nr
-32), IC1_CFG1CLR
);
365 au_writel(1<<(irq_nr
-32), IC1_CFG2CLR
);
367 default: /* disable the interrupt */
368 printk("unexpected int type %d (irq %d)\n", type
, irq_nr
);
369 au_writel(1<<(irq_nr
-32), IC1_CFG0CLR
);
370 au_writel(1<<(irq_nr
-32), IC1_CFG1CLR
);
371 au_writel(1<<(irq_nr
-32), IC1_CFG2CLR
);
374 if (int_req
) /* assign to interrupt request 1 */
375 au_writel(1<<(irq_nr
-32), IC1_ASSIGNCLR
);
376 else /* assign to interrupt request 0 */
377 au_writel(1<<(irq_nr
-32), IC1_ASSIGNSET
);
378 au_writel(1<<(irq_nr
-32), IC1_SRCSET
);
379 au_writel(1<<(irq_nr
-32), IC1_MASKCLR
);
380 au_writel(1<<(irq_nr
-32), IC1_WAKECLR
);
384 case INTC_INT_RISE_EDGE
: /* 0:0:1 */
385 au_writel(1<<irq_nr
, IC0_CFG2CLR
);
386 au_writel(1<<irq_nr
, IC0_CFG1CLR
);
387 au_writel(1<<irq_nr
, IC0_CFG0SET
);
388 irq_desc
[irq_nr
].handler
= &rise_edge_irq_type
;
390 case INTC_INT_FALL_EDGE
: /* 0:1:0 */
391 au_writel(1<<irq_nr
, IC0_CFG2CLR
);
392 au_writel(1<<irq_nr
, IC0_CFG1SET
);
393 au_writel(1<<irq_nr
, IC0_CFG0CLR
);
394 irq_desc
[irq_nr
].handler
= &fall_edge_irq_type
;
396 case INTC_INT_RISE_AND_FALL_EDGE
: /* 0:1:1 */
397 au_writel(1<<irq_nr
, IC0_CFG2CLR
);
398 au_writel(1<<irq_nr
, IC0_CFG1SET
);
399 au_writel(1<<irq_nr
, IC0_CFG0SET
);
400 irq_desc
[irq_nr
].handler
= &either_edge_irq_type
;
402 case INTC_INT_HIGH_LEVEL
: /* 1:0:1 */
403 au_writel(1<<irq_nr
, IC0_CFG2SET
);
404 au_writel(1<<irq_nr
, IC0_CFG1CLR
);
405 au_writel(1<<irq_nr
, IC0_CFG0SET
);
406 irq_desc
[irq_nr
].handler
= &level_irq_type
;
408 case INTC_INT_LOW_LEVEL
: /* 1:1:0 */
409 au_writel(1<<irq_nr
, IC0_CFG2SET
);
410 au_writel(1<<irq_nr
, IC0_CFG1SET
);
411 au_writel(1<<irq_nr
, IC0_CFG0CLR
);
412 irq_desc
[irq_nr
].handler
= &level_irq_type
;
414 case INTC_INT_DISABLED
: /* 0:0:0 */
415 au_writel(1<<irq_nr
, IC0_CFG0CLR
);
416 au_writel(1<<irq_nr
, IC0_CFG1CLR
);
417 au_writel(1<<irq_nr
, IC0_CFG2CLR
);
419 default: /* disable the interrupt */
420 printk("unexpected int type %d (irq %d)\n", type
, irq_nr
);
421 au_writel(1<<irq_nr
, IC0_CFG0CLR
);
422 au_writel(1<<irq_nr
, IC0_CFG1CLR
);
423 au_writel(1<<irq_nr
, IC0_CFG2CLR
);
426 if (int_req
) /* assign to interrupt request 1 */
427 au_writel(1<<irq_nr
, IC0_ASSIGNCLR
);
428 else /* assign to interrupt request 0 */
429 au_writel(1<<irq_nr
, IC0_ASSIGNSET
);
430 au_writel(1<<irq_nr
, IC0_SRCSET
);
431 au_writel(1<<irq_nr
, IC0_MASKCLR
);
432 au_writel(1<<irq_nr
, IC0_WAKECLR
);
438 void __init
arch_init_irq(void)
441 unsigned long cp0_status
;
442 au1xxx_irq_map_t
*imp
;
443 extern au1xxx_irq_map_t au1xxx_irq_map
[];
444 extern au1xxx_irq_map_t au1xxx_ic0_map
[];
445 extern int au1xxx_nr_irqs
;
446 extern int au1xxx_ic0_nr_irqs
;
448 cp0_status
= read_c0_status();
449 set_except_vector(0, au1000_IRQ
);
451 /* Initialize interrupt controllers to a safe state.
453 au_writel(0xffffffff, IC0_CFG0CLR
);
454 au_writel(0xffffffff, IC0_CFG1CLR
);
455 au_writel(0xffffffff, IC0_CFG2CLR
);
456 au_writel(0xffffffff, IC0_MASKCLR
);
457 au_writel(0xffffffff, IC0_ASSIGNSET
);
458 au_writel(0xffffffff, IC0_WAKECLR
);
459 au_writel(0xffffffff, IC0_SRCSET
);
460 au_writel(0xffffffff, IC0_FALLINGCLR
);
461 au_writel(0xffffffff, IC0_RISINGCLR
);
462 au_writel(0x00000000, IC0_TESTBIT
);
464 au_writel(0xffffffff, IC1_CFG0CLR
);
465 au_writel(0xffffffff, IC1_CFG1CLR
);
466 au_writel(0xffffffff, IC1_CFG2CLR
);
467 au_writel(0xffffffff, IC1_MASKCLR
);
468 au_writel(0xffffffff, IC1_ASSIGNSET
);
469 au_writel(0xffffffff, IC1_WAKECLR
);
470 au_writel(0xffffffff, IC1_SRCSET
);
471 au_writel(0xffffffff, IC1_FALLINGCLR
);
472 au_writel(0xffffffff, IC1_RISINGCLR
);
473 au_writel(0x00000000, IC1_TESTBIT
);
475 /* Initialize IC0, which is fixed per processor.
477 imp
= au1xxx_ic0_map
;
478 for (i
=0; i
<au1xxx_ic0_nr_irqs
; i
++) {
479 setup_local_irq(imp
->im_irq
, imp
->im_type
, imp
->im_request
);
483 /* Now set up the irq mapping for the board.
485 imp
= au1xxx_irq_map
;
486 for (i
=0; i
<au1xxx_nr_irqs
; i
++) {
487 setup_local_irq(imp
->im_irq
, imp
->im_type
, imp
->im_request
);
491 set_c0_status(ALLINTS
);
493 /* Board specific IRQ initialization.
501 * Interrupts are nested. Even if an interrupt handler is registered
502 * as "fast", we might get another interrupt before we return from
503 * intcX_reqX_irqdispatch().
506 void intc0_req0_irqdispatch(struct pt_regs
*regs
)
509 static unsigned long intc0_req0
= 0;
511 intc0_req0
|= au_readl(IC0_REQ0INT
);
513 if (!intc0_req0
) return;
514 #ifdef AU1000_USB_DEV_REQ_INT
516 * Because of the tight timing of SETUP token to reply
517 * transactions, the USB devices-side packet complete
518 * interrupt needs the highest priority.
520 if ((intc0_req0
& (1<<AU1000_USB_DEV_REQ_INT
))) {
521 intc0_req0
&= ~(1<<AU1000_USB_DEV_REQ_INT
);
522 do_IRQ(AU1000_USB_DEV_REQ_INT
, regs
);
526 irq
= au_ffs(intc0_req0
) - 1;
527 intc0_req0
&= ~(1<<irq
);
532 void intc0_req1_irqdispatch(struct pt_regs
*regs
)
535 static unsigned long intc0_req1
= 0;
537 intc0_req1
|= au_readl(IC0_REQ1INT
);
539 if (!intc0_req1
) return;
541 irq
= au_ffs(intc0_req1
) - 1;
542 intc0_req1
&= ~(1<<irq
);
548 * Interrupt Controller 1:
551 void intc1_req0_irqdispatch(struct pt_regs
*regs
)
554 static unsigned long intc1_req0
= 0;
556 intc1_req0
|= au_readl(IC1_REQ0INT
);
558 if (!intc1_req0
) return;
560 irq
= au_ffs(intc1_req0
) - 1;
561 intc1_req0
&= ~(1<<irq
);
567 void intc1_req1_irqdispatch(struct pt_regs
*regs
)
570 static unsigned long intc1_req1
= 0;
572 intc1_req1
|= au_readl(IC1_REQ1INT
);
574 if (!intc1_req1
) return;
576 irq
= au_ffs(intc1_req1
) - 1;
577 intc1_req1
&= ~(1<<irq
);
584 /* Save/restore the interrupt controller state.
585 * Called from the save/restore core registers as part of the
586 * au_sleep function in power.c.....maybe I should just pm_register()
589 static uint sleep_intctl_config0
[2];
590 static uint sleep_intctl_config1
[2];
591 static uint sleep_intctl_config2
[2];
592 static uint sleep_intctl_src
[2];
593 static uint sleep_intctl_assign
[2];
594 static uint sleep_intctl_wake
[2];
595 static uint sleep_intctl_mask
[2];
598 save_au1xxx_intctl(void)
600 sleep_intctl_config0
[0] = au_readl(IC0_CFG0RD
);
601 sleep_intctl_config1
[0] = au_readl(IC0_CFG1RD
);
602 sleep_intctl_config2
[0] = au_readl(IC0_CFG2RD
);
603 sleep_intctl_src
[0] = au_readl(IC0_SRCRD
);
604 sleep_intctl_assign
[0] = au_readl(IC0_ASSIGNRD
);
605 sleep_intctl_wake
[0] = au_readl(IC0_WAKERD
);
606 sleep_intctl_mask
[0] = au_readl(IC0_MASKRD
);
608 sleep_intctl_config0
[1] = au_readl(IC1_CFG0RD
);
609 sleep_intctl_config1
[1] = au_readl(IC1_CFG1RD
);
610 sleep_intctl_config2
[1] = au_readl(IC1_CFG2RD
);
611 sleep_intctl_src
[1] = au_readl(IC1_SRCRD
);
612 sleep_intctl_assign
[1] = au_readl(IC1_ASSIGNRD
);
613 sleep_intctl_wake
[1] = au_readl(IC1_WAKERD
);
614 sleep_intctl_mask
[1] = au_readl(IC1_MASKRD
);
617 /* For most restore operations, we clear the entire register and
618 * then set the bits we found during the save.
621 restore_au1xxx_intctl(void)
623 au_writel(0xffffffff, IC0_MASKCLR
); au_sync();
625 au_writel(0xffffffff, IC0_CFG0CLR
); au_sync();
626 au_writel(sleep_intctl_config0
[0], IC0_CFG0SET
); au_sync();
627 au_writel(0xffffffff, IC0_CFG1CLR
); au_sync();
628 au_writel(sleep_intctl_config1
[0], IC0_CFG1SET
); au_sync();
629 au_writel(0xffffffff, IC0_CFG2CLR
); au_sync();
630 au_writel(sleep_intctl_config2
[0], IC0_CFG2SET
); au_sync();
631 au_writel(0xffffffff, IC0_SRCCLR
); au_sync();
632 au_writel(sleep_intctl_src
[0], IC0_SRCSET
); au_sync();
633 au_writel(0xffffffff, IC0_ASSIGNCLR
); au_sync();
634 au_writel(sleep_intctl_assign
[0], IC0_ASSIGNSET
); au_sync();
635 au_writel(0xffffffff, IC0_WAKECLR
); au_sync();
636 au_writel(sleep_intctl_wake
[0], IC0_WAKESET
); au_sync();
637 au_writel(0xffffffff, IC0_RISINGCLR
); au_sync();
638 au_writel(0xffffffff, IC0_FALLINGCLR
); au_sync();
639 au_writel(0x00000000, IC0_TESTBIT
); au_sync();
641 au_writel(0xffffffff, IC1_MASKCLR
); au_sync();
643 au_writel(0xffffffff, IC1_CFG0CLR
); au_sync();
644 au_writel(sleep_intctl_config0
[1], IC1_CFG0SET
); au_sync();
645 au_writel(0xffffffff, IC1_CFG1CLR
); au_sync();
646 au_writel(sleep_intctl_config1
[1], IC1_CFG1SET
); au_sync();
647 au_writel(0xffffffff, IC1_CFG2CLR
); au_sync();
648 au_writel(sleep_intctl_config2
[1], IC1_CFG2SET
); au_sync();
649 au_writel(0xffffffff, IC1_SRCCLR
); au_sync();
650 au_writel(sleep_intctl_src
[1], IC1_SRCSET
); au_sync();
651 au_writel(0xffffffff, IC1_ASSIGNCLR
); au_sync();
652 au_writel(sleep_intctl_assign
[1], IC1_ASSIGNSET
); au_sync();
653 au_writel(0xffffffff, IC1_WAKECLR
); au_sync();
654 au_writel(sleep_intctl_wake
[1], IC1_WAKESET
); au_sync();
655 au_writel(0xffffffff, IC1_RISINGCLR
); au_sync();
656 au_writel(0xffffffff, IC1_FALLINGCLR
); au_sync();
657 au_writel(0x00000000, IC1_TESTBIT
); au_sync();
659 au_writel(sleep_intctl_mask
[1], IC1_MASKSET
); au_sync();
661 au_writel(sleep_intctl_mask
[0], IC0_MASKSET
); au_sync();
663 #endif /* CONFIG_PM */