2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
9 #include <linux/module.h>
10 #include <linux/mutex.h>
11 #include <linux/err.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <bcm63xx_cpu.h>
15 #include <bcm63xx_io.h>
16 #include <bcm63xx_regs.h>
17 #include <bcm63xx_reset.h>
19 #define __GEN_RESET_BITS_TABLE(__cpu) \
20 [BCM63XX_RESET_SPI] = BCM## __cpu ##_RESET_SPI, \
21 [BCM63XX_RESET_ENET] = BCM## __cpu ##_RESET_ENET, \
22 [BCM63XX_RESET_USBH] = BCM## __cpu ##_RESET_USBH, \
23 [BCM63XX_RESET_USBD] = BCM## __cpu ##_RESET_USBD, \
24 [BCM63XX_RESET_DSL] = BCM## __cpu ##_RESET_DSL, \
25 [BCM63XX_RESET_SAR] = BCM## __cpu ##_RESET_SAR, \
26 [BCM63XX_RESET_EPHY] = BCM## __cpu ##_RESET_EPHY, \
27 [BCM63XX_RESET_ENETSW] = BCM## __cpu ##_RESET_ENETSW, \
28 [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
29 [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
30 [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
31 [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
33 #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
34 #define BCM6328_RESET_ENET 0
35 #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
36 #define BCM6328_RESET_USBD SOFTRESET_6328_USBS_MASK
37 #define BCM6328_RESET_DSL 0
38 #define BCM6328_RESET_SAR SOFTRESET_6328_SAR_MASK
39 #define BCM6328_RESET_EPHY SOFTRESET_6328_EPHY_MASK
40 #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
41 #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
42 #define BCM6328_RESET_MPI 0
43 #define BCM6328_RESET_PCIE \
44 (SOFTRESET_6328_PCIE_MASK | \
45 SOFTRESET_6328_PCIE_CORE_MASK | \
46 SOFTRESET_6328_PCIE_HARD_MASK)
47 #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
49 #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
50 #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
51 #define BCM6338_RESET_USBH SOFTRESET_6338_USBH_MASK
52 #define BCM6338_RESET_USBD SOFTRESET_6338_USBS_MASK
53 #define BCM6338_RESET_DSL SOFTRESET_6338_ADSL_MASK
54 #define BCM6338_RESET_SAR SOFTRESET_6338_SAR_MASK
55 #define BCM6338_RESET_EPHY 0
56 #define BCM6338_RESET_ENETSW 0
57 #define BCM6338_RESET_PCM 0
58 #define BCM6338_RESET_MPI 0
59 #define BCM6338_RESET_PCIE 0
60 #define BCM6338_RESET_PCIE_EXT 0
62 #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
63 #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
64 #define BCM6348_RESET_USBH SOFTRESET_6348_USBH_MASK
65 #define BCM6348_RESET_USBD SOFTRESET_6348_USBS_MASK
66 #define BCM6348_RESET_DSL SOFTRESET_6348_ADSL_MASK
67 #define BCM6348_RESET_SAR SOFTRESET_6348_SAR_MASK
68 #define BCM6348_RESET_EPHY 0
69 #define BCM6348_RESET_ENETSW 0
70 #define BCM6348_RESET_PCM 0
71 #define BCM6348_RESET_MPI 0
72 #define BCM6348_RESET_PCIE 0
73 #define BCM6348_RESET_PCIE_EXT 0
75 #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
76 #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
77 #define BCM6358_RESET_USBH SOFTRESET_6358_USBH_MASK
78 #define BCM6358_RESET_USBD 0
79 #define BCM6358_RESET_DSL SOFTRESET_6358_ADSL_MASK
80 #define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
81 #define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
82 #define BCM6358_RESET_ENETSW 0
83 #define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
84 #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
85 #define BCM6358_RESET_PCIE 0
86 #define BCM6358_RESET_PCIE_EXT 0
88 #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
89 #define BCM6368_RESET_ENET 0
90 #define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
91 #define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
92 #define BCM6368_RESET_DSL 0
93 #define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
94 #define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
95 #define BCM6368_RESET_ENETSW 0
96 #define BCM6368_RESET_PCM SOFTRESET_6368_PCM_MASK
97 #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
98 #define BCM6368_RESET_PCIE 0
99 #define BCM6368_RESET_PCIE_EXT 0
101 #ifdef BCMCPU_RUNTIME_DETECT
106 static const u32 bcm6328_reset_bits
[] = {
107 __GEN_RESET_BITS_TABLE(6328)
110 static const u32 bcm6338_reset_bits
[] = {
111 __GEN_RESET_BITS_TABLE(6338)
114 static const u32 bcm6348_reset_bits
[] = {
115 __GEN_RESET_BITS_TABLE(6348)
118 static const u32 bcm6358_reset_bits
[] = {
119 __GEN_RESET_BITS_TABLE(6358)
122 static const u32 bcm6368_reset_bits
[] = {
123 __GEN_RESET_BITS_TABLE(6368)
126 const u32
*bcm63xx_reset_bits
;
127 static int reset_reg
;
129 static int __init
bcm63xx_reset_bits_init(void)
131 if (BCMCPU_IS_6328()) {
132 reset_reg
= PERF_SOFTRESET_6328_REG
;
133 bcm63xx_reset_bits
= bcm6328_reset_bits
;
134 } else if (BCMCPU_IS_6338()) {
135 reset_reg
= PERF_SOFTRESET_REG
;
136 bcm63xx_reset_bits
= bcm6338_reset_bits
;
137 } else if (BCMCPU_IS_6348()) {
138 reset_reg
= PERF_SOFTRESET_REG
;
139 bcm63xx_reset_bits
= bcm6348_reset_bits
;
140 } else if (BCMCPU_IS_6358()) {
141 reset_reg
= PERF_SOFTRESET_6358_REG
;
142 bcm63xx_reset_bits
= bcm6358_reset_bits
;
143 } else if (BCMCPU_IS_6368()) {
144 reset_reg
= PERF_SOFTRESET_6368_REG
;
145 bcm63xx_reset_bits
= bcm6368_reset_bits
;
152 #ifdef CONFIG_BCM63XX_CPU_6328
153 static const u32 bcm63xx_reset_bits
[] = {
154 __GEN_RESET_BITS_TABLE(6328)
156 #define reset_reg PERF_SOFTRESET_6328_REG
159 #ifdef CONFIG_BCM63XX_CPU_6338
160 static const u32 bcm63xx_reset_bits
[] = {
161 __GEN_RESET_BITS_TABLE(6338)
163 #define reset_reg PERF_SOFTRESET_REG
166 #ifdef CONFIG_BCM63XX_CPU_6345
167 static const u32 bcm63xx_reset_bits
[] = { };
171 #ifdef CONFIG_BCM63XX_CPU_6348
172 static const u32 bcm63xx_reset_bits
[] = {
173 __GEN_RESET_BITS_TABLE(6348)
175 #define reset_reg PERF_SOFTRESET_REG
178 #ifdef CONFIG_BCM63XX_CPU_6358
179 static const u32 bcm63xx_reset_bits
[] = {
180 __GEN_RESET_BITS_TABLE(6358)
182 #define reset_reg PERF_SOFTRESET_6358_REG
185 #ifdef CONFIG_BCM63XX_CPU_6368
186 static const u32 bcm63xx_reset_bits
[] = {
187 __GEN_RESET_BITS_TABLE(6368)
189 #define reset_reg PERF_SOFTRESET_6368_REG
192 static int __init
bcm63xx_reset_bits_init(void) { return 0; }
195 static DEFINE_SPINLOCK(reset_mutex
);
197 static void __bcm63xx_core_set_reset(u32 mask
, int enable
)
205 spin_lock_irqsave(&reset_mutex
, flags
);
206 val
= bcm_perf_readl(reset_reg
);
213 bcm_perf_writel(val
, reset_reg
);
214 spin_unlock_irqrestore(&reset_mutex
, flags
);
217 void bcm63xx_core_set_reset(enum bcm63xx_core_reset core
, int reset
)
219 __bcm63xx_core_set_reset(bcm63xx_reset_bits
[core
], reset
);
221 EXPORT_SYMBOL(bcm63xx_core_set_reset
);
223 postcore_initcall(bcm63xx_reset_bits_init
);
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