4 compatible = "brcm,bcm7358";
10 mips-hpt-frequency = <375000000>;
13 compatible = "brcm,bmips3300";
25 compatible = "mti,cpu-interrupt-controller";
28 #interrupt-cells = <1>;
33 compatible = "fixed-clock";
35 clock-frequency = <81000000>;
43 compatible = "simple-bus";
44 ranges = <0 0x10000000 0x01000000>;
46 periph_intc: periph_intc@411400 {
47 compatible = "brcm,bcm7038-l1-intc";
48 reg = <0x411400 0x30>;
51 #interrupt-cells = <1>;
53 interrupt-parent = <&cpu_intc>;
57 sun_l2_intc: sun_l2_intc@403000 {
58 compatible = "brcm,l2-intc";
59 reg = <0x403000 0x30>;
61 #interrupt-cells = <1>;
62 interrupt-parent = <&periph_intc>;
67 compatible = "brcm,bcm7400-gisb-arb";
68 reg = <0x400000 0xdc>;
70 interrupt-parent = <&sun_l2_intc>;
71 interrupts = <0>, <2>;
72 brcm,gisb-arb-master-mask = <0x2f3>;
73 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
78 upg_irq0_intc: upg_irq0_intc@406600 {
79 compatible = "brcm,bcm7120-l2-intc";
82 brcm,int-map-mask = <0x44>, <0x7000000>;
83 brcm,int-fwd-mask = <0x70000>;
86 #interrupt-cells = <1>;
88 interrupt-parent = <&periph_intc>;
89 interrupts = <56>, <54>;
90 interrupt-names = "upg_main", "upg_bsc";
93 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
94 compatible = "brcm,bcm7120-l2-intc";
97 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
98 brcm,int-fwd-mask = <0>;
101 interrupt-controller;
102 #interrupt-cells = <1>;
104 interrupt-parent = <&periph_intc>;
105 interrupts = <57>, <55>, <59>;
106 interrupt-names = "upg_main_aon", "upg_bsc_aon",
110 sun_top_ctrl: syscon@404000 {
111 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
112 reg = <0x404000 0x51c>;
117 compatible = "brcm,brcmstb-reboot";
118 syscon = <&sun_top_ctrl 0x304 0x308>;
121 uart0: serial@406800 {
122 compatible = "ns16550a";
123 reg = <0x406800 0x20>;
124 reg-io-width = <0x4>;
127 interrupt-parent = <&periph_intc>;
129 clocks = <&uart_clk>;
133 uart1: serial@406840 {
134 compatible = "ns16550a";
135 reg = <0x406840 0x20>;
136 reg-io-width = <0x4>;
139 interrupt-parent = <&periph_intc>;
141 clocks = <&uart_clk>;
145 uart2: serial@406880 {
146 compatible = "ns16550a";
147 reg = <0x406880 0x20>;
148 reg-io-width = <0x4>;
151 interrupt-parent = <&periph_intc>;
153 clocks = <&uart_clk>;
158 clock-frequency = <390000>;
159 compatible = "brcm,brcmstb-i2c";
160 interrupt-parent = <&upg_irq0_intc>;
161 reg = <0x406200 0x58>;
163 interrupt-names = "upg_bsca";
168 clock-frequency = <390000>;
169 compatible = "brcm,brcmstb-i2c";
170 interrupt-parent = <&upg_irq0_intc>;
171 reg = <0x406280 0x58>;
173 interrupt-names = "upg_bscb";
178 clock-frequency = <390000>;
179 compatible = "brcm,brcmstb-i2c";
180 interrupt-parent = <&upg_irq0_intc>;
181 reg = <0x406300 0x58>;
183 interrupt-names = "upg_bscc";
188 clock-frequency = <390000>;
189 compatible = "brcm,brcmstb-i2c";
190 interrupt-parent = <&upg_aon_irq0_intc>;
191 reg = <0x408980 0x58>;
193 interrupt-names = "upg_bscd";
197 enet0: ethernet@430000 {
198 phy-mode = "internal";
199 phy-handle = <&phy1>;
200 mac-address = [ 00 10 18 36 23 1a ];
201 compatible = "brcm,genet-v2";
202 #address-cells = <0x1>;
204 reg = <0x430000 0x4c8c>;
205 interrupts = <24>, <25>;
206 interrupt-parent = <&periph_intc>;
210 compatible = "brcm,genet-mdio-v2";
211 #address-cells = <0x1>;
215 phy1: ethernet-phy@1 {
218 compatible = "brcm,40nm-ephy",
219 "ethernet-phy-ieee802.3-c22";
225 compatible = "brcm,bcm7358-ehci", "generic-ehci";
226 reg = <0x480300 0x100>;
228 interrupt-parent = <&periph_intc>;
234 compatible = "brcm,bcm7358-ohci", "generic-ohci";
235 reg = <0x480400 0x100>;
238 interrupt-parent = <&periph_intc>;