4 compatible = "brcm,bcm7435";
10 mips-hpt-frequency = <175625000>;
13 compatible = "brcm,bmips5200";
19 compatible = "brcm,bmips5200";
25 compatible = "brcm,bmips5200";
31 compatible = "brcm,bmips5200";
43 compatible = "mti,cpu-interrupt-controller";
46 #interrupt-cells = <1>;
51 compatible = "fixed-clock";
53 clock-frequency = <81000000>;
61 compatible = "simple-bus";
62 ranges = <0 0x10000000 0x01000000>;
64 periph_intc: periph_intc@41b500 {
65 compatible = "brcm,bcm7038-l1-intc";
66 reg = <0x41b500 0x40>, <0x41b600 0x40>,
67 <0x41b700 0x40>, <0x41b800 0x40>;
70 #interrupt-cells = <1>;
72 interrupt-parent = <&cpu_intc>;
73 interrupts = <2>, <3>, <2>, <3>;
76 sun_l2_intc: sun_l2_intc@403000 {
77 compatible = "brcm,l2-intc";
78 reg = <0x403000 0x30>;
80 #interrupt-cells = <1>;
81 interrupt-parent = <&periph_intc>;
86 compatible = "brcm,bcm7435-gisb-arb";
87 reg = <0x400000 0xdc>;
89 interrupt-parent = <&sun_l2_intc>;
90 interrupts = <0>, <2>;
91 brcm,gisb-arb-master-mask = <0xf77f>;
92 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
101 upg_irq0_intc: upg_irq0_intc@406780 {
102 compatible = "brcm,bcm7120-l2-intc";
103 reg = <0x406780 0x8>;
105 brcm,int-map-mask = <0x44>, <0x7000000>;
106 brcm,int-fwd-mask = <0x70000>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
111 interrupt-parent = <&periph_intc>;
112 interrupts = <60>, <58>;
113 interrupt-names = "upg_main", "upg_bsc";
116 upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
117 compatible = "brcm,bcm7120-l2-intc";
118 reg = <0x409480 0x8>;
120 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
121 brcm,int-fwd-mask = <0>;
124 interrupt-controller;
125 #interrupt-cells = <1>;
127 interrupt-parent = <&periph_intc>;
128 interrupts = <61>, <59>, <64>;
129 interrupt-names = "upg_main_aon", "upg_bsc_aon",
133 sun_top_ctrl: syscon@404000 {
134 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
135 reg = <0x404000 0x51c>;
140 compatible = "brcm,brcmstb-reboot";
141 syscon = <&sun_top_ctrl 0x304 0x308>;
144 uart0: serial@406b00 {
145 compatible = "ns16550a";
146 reg = <0x406b00 0x20>;
147 reg-io-width = <0x4>;
149 interrupt-parent = <&periph_intc>;
151 clocks = <&uart_clk>;
155 uart1: serial@406b40 {
156 compatible = "ns16550a";
157 reg = <0x406b40 0x20>;
158 reg-io-width = <0x4>;
160 interrupt-parent = <&periph_intc>;
162 clocks = <&uart_clk>;
166 uart2: serial@406b80 {
167 compatible = "ns16550a";
168 reg = <0x406b80 0x20>;
169 reg-io-width = <0x4>;
171 interrupt-parent = <&periph_intc>;
173 clocks = <&uart_clk>;
178 clock-frequency = <390000>;
179 compatible = "brcm,brcmstb-i2c";
180 interrupt-parent = <&upg_irq0_intc>;
181 reg = <0x406300 0x58>;
183 interrupt-names = "upg_bsca";
188 clock-frequency = <390000>;
189 compatible = "brcm,brcmstb-i2c";
190 interrupt-parent = <&upg_aon_irq0_intc>;
191 reg = <0x409400 0x58>;
193 interrupt-names = "upg_bscb";
198 clock-frequency = <390000>;
199 compatible = "brcm,brcmstb-i2c";
200 interrupt-parent = <&upg_irq0_intc>;
201 reg = <0x406200 0x58>;
203 interrupt-names = "upg_bscc";
208 clock-frequency = <390000>;
209 compatible = "brcm,brcmstb-i2c";
210 interrupt-parent = <&upg_irq0_intc>;
211 reg = <0x406280 0x58>;
213 interrupt-names = "upg_bscd";
218 clock-frequency = <390000>;
219 compatible = "brcm,brcmstb-i2c";
220 interrupt-parent = <&upg_aon_irq0_intc>;
221 reg = <0x409180 0x58>;
223 interrupt-names = "upg_bsce";
227 enet0: ethernet@b80000 {
228 phy-mode = "internal";
229 phy-handle = <&phy1>;
230 mac-address = [ 00 10 18 36 23 1a ];
231 compatible = "brcm,genet-v3";
232 #address-cells = <0x1>;
234 reg = <0xb80000 0x11c88>;
235 interrupts = <17>, <18>;
236 interrupt-parent = <&periph_intc>;
240 compatible = "brcm,genet-mdio-v3";
241 #address-cells = <0x1>;
245 phy1: ethernet-phy@1 {
248 compatible = "brcm,40nm-ephy",
249 "ethernet-phy-ieee802.3-c22";
255 compatible = "brcm,bcm7435-ehci", "generic-ehci";
256 reg = <0x480300 0x100>;
258 interrupt-parent = <&periph_intc>;
264 compatible = "brcm,bcm7435-ohci", "generic-ohci";
265 reg = <0x480400 0x100>;
268 interrupt-parent = <&periph_intc>;
274 compatible = "brcm,bcm7435-ehci", "generic-ehci";
275 reg = <0x480500 0x100>;
277 interrupt-parent = <&periph_intc>;
283 compatible = "brcm,bcm7435-ohci", "generic-ohci";
284 reg = <0x480600 0x100>;
287 interrupt-parent = <&periph_intc>;
293 compatible = "brcm,bcm7435-ehci", "generic-ehci";
294 reg = <0x490300 0x100>;
296 interrupt-parent = <&periph_intc>;
302 compatible = "brcm,bcm7435-ohci", "generic-ohci";
303 reg = <0x490400 0x100>;
306 interrupt-parent = <&periph_intc>;
312 compatible = "brcm,bcm7435-ehci", "generic-ehci";
313 reg = <0x490500 0x100>;
315 interrupt-parent = <&periph_intc>;
321 compatible = "brcm,bcm7435-ohci", "generic-ohci";
322 reg = <0x490600 0x100>;
325 interrupt-parent = <&periph_intc>;
331 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
332 reg-names = "ahci", "top-ctrl";
333 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
334 interrupt-parent = <&periph_intc>;
336 #address-cells = <1>;
351 sata_phy: sata-phy@180100 {
352 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
353 reg = <0x180100 0x0eff>;
355 #address-cells = <1>;
359 sata_phy0: sata-phy@0 {
364 sata_phy1: sata-phy@1 {