2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 * Copyright (C) 2004 Maciej W. Rozycki
12 #ifndef __ASM_CPU_INFO_H
13 #define __ASM_CPU_INFO_H
15 #include <linux/types.h>
17 #include <asm/cache.h>
20 * Descriptor for a cache
23 unsigned int waysize
; /* Bytes per way */
24 unsigned short sets
; /* Number of lines per set */
25 unsigned char ways
; /* Number of ways */
26 unsigned char linesz
; /* Size of line in bytes */
27 unsigned char waybit
; /* Bits to select in a cache set */
28 unsigned char flags
; /* Flags describing cache properties */
34 #define MIPS_CACHE_NOT_PRESENT 0x00000001
35 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
36 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
37 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
38 #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
39 #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
42 unsigned long asid_cache
;
45 * Capability and feature descriptor structure for MIPS CPU
48 unsigned long long options
;
49 unsigned int udelay_val
;
50 unsigned int processor_id
;
59 struct cache_desc icache
; /* Primary I-cache */
60 struct cache_desc dcache
; /* Primary D or combined I/D cache */
61 struct cache_desc scache
; /* Secondary cache */
62 struct cache_desc tcache
; /* Tertiary/split secondary cache */
63 int srsets
; /* Shadow register sets */
64 int package
;/* physical package number */
65 int core
; /* physical core number */
67 int vmbits
; /* Virtual memory size in bits */
69 #ifdef CONFIG_MIPS_MT_SMP
71 * There is not necessarily a 1:1 mapping of VPE num to CPU number
72 * in particular on multi-core systems.
74 int vpe_id
; /* Virtual Processor number */
76 void *data
; /* Additional data */
77 unsigned int watch_reg_count
; /* Number that exist */
78 unsigned int watch_reg_use_cnt
; /* Usable by ptrace */
79 #define NUM_WATCH_REGS 4
80 u16 watch_reg_masks
[NUM_WATCH_REGS
];
81 unsigned int kscratch_mask
; /* Usable KScratch mask. */
83 * Cache Coherency attribute for write-combine memory writes.
84 * (shifted by _CACHE_SHIFT)
86 unsigned int writecombine
;
87 } __attribute__((aligned(SMP_CACHE_BYTES
)));
89 extern struct cpuinfo_mips cpu_data
[];
90 #define current_cpu_data cpu_data[smp_processor_id()]
91 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
92 #define boot_cpu_data cpu_data[0]
94 extern void cpu_probe(void);
95 extern void cpu_report(void);
97 extern const char *__cpu_name
[];
98 #define cpu_name_string() __cpu_name[smp_processor_id()]
101 struct notifier_block
;
103 extern int register_proc_cpuinfo_notifier(struct notifier_block
*nb
);
104 extern int proc_cpuinfo_notifier_call_chain(unsigned long val
, void *v
);
106 #define proc_cpuinfo_notifier(fn, pri) \
108 static struct notifier_block fn##_nb = { \
109 .notifier_call = fn, \
113 register_proc_cpuinfo_notifier(&fn##_nb); \
116 struct proc_cpuinfo_notifier_args
{
121 #ifdef CONFIG_MIPS_MT_SMP
122 # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
124 # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
127 #endif /* __ASM_CPU_INFO_H */