2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
23 #include <asm/mipsregs.h>
25 /* MIPS KVM register ids */
26 #define MIPS_CP0_32(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
29 #define MIPS_CP0_64(_R, _S) \
30 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
32 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
33 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
34 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
35 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
36 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
37 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
38 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
39 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
40 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
41 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
42 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
43 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
44 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
45 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
46 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
47 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
48 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
49 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
50 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
51 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
52 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
53 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
54 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
55 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
56 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
57 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
58 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
61 #define KVM_MAX_VCPUS 1
62 #define KVM_USER_MEM_SLOTS 8
63 /* memory slots that does not exposed to userspace */
64 #define KVM_PRIVATE_MEM_SLOTS 0
66 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
67 #define KVM_HALT_POLL_NS_DEFAULT 500000
71 /* Special address that contains the comm page, used for reducing # of traps */
72 #define KVM_GUEST_COMMPAGE_ADDR 0x0
74 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
75 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
77 #define KVM_GUEST_KUSEG 0x00000000UL
78 #define KVM_GUEST_KSEG0 0x40000000UL
79 #define KVM_GUEST_KSEG23 0x60000000UL
80 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
81 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
83 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
84 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
85 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
88 * Map an address to a certain kernel segment
90 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
91 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
92 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
94 #define KVM_INVALID_PAGE 0xdeadbeef
95 #define KVM_INVALID_INST 0xdeadbeef
96 #define KVM_INVALID_ADDR 0xdeadbeef
98 extern atomic_t kvm_mips_instance
;
101 u32 remote_tlb_flush
;
104 struct kvm_vcpu_stat
{
109 u32 cop_unusable_exits
;
111 u32 tlbmiss_ld_exits
;
112 u32 tlbmiss_st_exits
;
113 u32 addrerr_st_exits
;
114 u32 addrerr_ld_exits
;
116 u32 resvd_inst_exits
;
117 u32 break_inst_exits
;
121 u32 msa_disabled_exits
;
122 u32 flush_dcache_exits
;
123 u32 halt_successful_poll
;
124 u32 halt_attempted_poll
;
125 u32 halt_poll_invalid
;
129 struct kvm_arch_memory_slot
{
133 /* Guest GVA->HPA page table */
134 unsigned long *guest_pmap
;
135 unsigned long guest_pmap_npages
;
137 /* Wired host TLB used for the commpage */
141 #define N_MIPS_COPROC_REGS 32
142 #define N_MIPS_COPROC_SEL 8
145 unsigned long reg
[N_MIPS_COPROC_REGS
][N_MIPS_COPROC_SEL
];
146 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
147 unsigned long stat
[N_MIPS_COPROC_REGS
][N_MIPS_COPROC_SEL
];
152 * Coprocessor 0 register names
154 #define MIPS_CP0_TLB_INDEX 0
155 #define MIPS_CP0_TLB_RANDOM 1
156 #define MIPS_CP0_TLB_LOW 2
157 #define MIPS_CP0_TLB_LO0 2
158 #define MIPS_CP0_TLB_LO1 3
159 #define MIPS_CP0_TLB_CONTEXT 4
160 #define MIPS_CP0_TLB_PG_MASK 5
161 #define MIPS_CP0_TLB_WIRED 6
162 #define MIPS_CP0_HWRENA 7
163 #define MIPS_CP0_BAD_VADDR 8
164 #define MIPS_CP0_COUNT 9
165 #define MIPS_CP0_TLB_HI 10
166 #define MIPS_CP0_COMPARE 11
167 #define MIPS_CP0_STATUS 12
168 #define MIPS_CP0_CAUSE 13
169 #define MIPS_CP0_EXC_PC 14
170 #define MIPS_CP0_PRID 15
171 #define MIPS_CP0_CONFIG 16
172 #define MIPS_CP0_LLADDR 17
173 #define MIPS_CP0_WATCH_LO 18
174 #define MIPS_CP0_WATCH_HI 19
175 #define MIPS_CP0_TLB_XCONTEXT 20
176 #define MIPS_CP0_ECC 26
177 #define MIPS_CP0_CACHE_ERR 27
178 #define MIPS_CP0_TAG_LO 28
179 #define MIPS_CP0_TAG_HI 29
180 #define MIPS_CP0_ERROR_PC 30
181 #define MIPS_CP0_DEBUG 23
182 #define MIPS_CP0_DEPC 24
183 #define MIPS_CP0_PERFCNT 25
184 #define MIPS_CP0_ERRCTL 26
185 #define MIPS_CP0_DATA_LO 28
186 #define MIPS_CP0_DATA_HI 29
187 #define MIPS_CP0_DESAVE 31
189 #define MIPS_CP0_CONFIG_SEL 0
190 #define MIPS_CP0_CONFIG1_SEL 1
191 #define MIPS_CP0_CONFIG2_SEL 2
192 #define MIPS_CP0_CONFIG3_SEL 3
193 #define MIPS_CP0_CONFIG4_SEL 4
194 #define MIPS_CP0_CONFIG5_SEL 5
196 /* Config0 register bits */
210 /* Config1 register bits */
227 /* Config2 Register bits */
238 /* Config3 Register bits */
240 #define CP0C3_ISA_ON_EXC 16
241 #define CP0C3_ULRI 13
242 #define CP0C3_DSPP 10
251 /* MMU types, the first four entries have the same layout as the
253 enum mips_mmu_types
{
264 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
265 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
267 #define RESUME_GUEST 0
268 #define RESUME_GUEST_DR RESUME_FLAG_DR
269 #define RESUME_HOST RESUME_FLAG_HOST
271 enum emulation_result
{
272 EMULATE_DONE
, /* no further processing */
273 EMULATE_DO_MMIO
, /* kvm_run filled with MMIO request */
274 EMULATE_FAIL
, /* can't emulate this instruction */
275 EMULATE_WAIT
, /* WAIT instruction */
279 #define mips3_paddr_to_tlbpfn(x) \
280 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
281 #define mips3_tlbpfn_to_paddr(x) \
282 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
284 #define MIPS3_PG_SHIFT 6
285 #define MIPS3_PG_FRAME 0x3fffffc0
287 #define VPN2_MASK 0xffffe000
288 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
289 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
290 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
291 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
292 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
293 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
294 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
295 ((y) & VPN2_MASK & ~(x).tlb_mask))
296 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
297 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
299 struct kvm_mips_tlb
{
305 #define KVM_MIPS_AUX_FPU 0x1
306 #define KVM_MIPS_AUX_MSA 0x2
308 #define KVM_MIPS_GUEST_TLB_SIZE 64
309 struct kvm_vcpu_arch
{
311 int (*vcpu_run
)(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
);
312 unsigned long host_stack
;
313 unsigned long host_gp
;
315 /* Host CP0 registers used when handling exits from guest */
316 unsigned long host_cp0_badvaddr
;
317 unsigned long host_cp0_epc
;
321 unsigned long gprs
[32];
327 struct mips_fpu_struct fpu
;
328 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
329 unsigned int aux_inuse
;
332 struct mips_coproc
*cop0
;
334 /* Host KSEG0 address of the EI/DI offset */
335 void *kseg0_commpage
;
337 u32 io_gpr
; /* GPR used as IO source/target */
339 struct hrtimer comparecount_timer
;
340 /* Count timer control KVM register */
342 /* Count bias from the raw time */
344 /* Frequency of timer in Hz */
346 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
349 ktime_t count_resume
;
350 /* Period of timer tick in ns */
353 /* Bitmask of exceptions that are pending */
354 unsigned long pending_exceptions
;
356 /* Bitmask of pending exceptions to be cleared */
357 unsigned long pending_exceptions_clr
;
359 u32 pending_load_cause
;
361 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
362 unsigned long preempt_entryhi
;
364 /* S/W Based TLB for guest */
365 struct kvm_mips_tlb guest_tlb
[KVM_MIPS_GUEST_TLB_SIZE
];
367 /* Cached guest kernel/user ASIDs */
368 u32 guest_user_asid
[NR_CPUS
];
369 u32 guest_kernel_asid
[NR_CPUS
];
370 struct mm_struct guest_kernel_mm
, guest_user_mm
;
382 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
383 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
384 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
385 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
386 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
387 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
388 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
389 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
390 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
391 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
392 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
393 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
394 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
395 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
396 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
397 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
398 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
399 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
400 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
401 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
402 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
403 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
404 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
405 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
406 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
407 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
408 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
409 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
410 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
411 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
412 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
413 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
414 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
415 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
416 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
417 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
418 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
419 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
420 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
421 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
422 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
423 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
424 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
425 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
426 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
427 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
428 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
429 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
430 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
431 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
434 * Some of the guest registers may be modified asynchronously (e.g. from a
435 * hrtimer callback in hard irq context) and therefore need stronger atomicity
436 * guarantees than other registers.
439 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg
,
444 __asm__
__volatile__(
450 : "=&r" (temp
), "+m" (*reg
)
452 } while (unlikely(!temp
));
455 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg
,
460 __asm__
__volatile__(
466 : "=&r" (temp
), "+m" (*reg
)
468 } while (unlikely(!temp
));
471 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg
,
472 unsigned long change
,
477 __asm__
__volatile__(
484 : "=&r" (temp
), "+m" (*reg
)
485 : "r" (~change
), "r" (val
& change
));
486 } while (unlikely(!temp
));
489 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
490 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
492 /* Cause can be modified asynchronously from hardirq hrtimer callback */
493 #define kvm_set_c0_guest_cause(cop0, val) \
494 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
495 #define kvm_clear_c0_guest_cause(cop0, val) \
496 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
497 #define kvm_change_c0_guest_cause(cop0, change, val) \
498 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
501 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
502 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
503 #define kvm_change_c0_guest_ebase(cop0, change, val) \
505 kvm_clear_c0_guest_ebase(cop0, change); \
506 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
511 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch
*vcpu
)
513 return (!__builtin_constant_p(cpu_has_fpu
) || cpu_has_fpu
) &&
517 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch
*vcpu
)
519 return kvm_mips_guest_can_have_fpu(vcpu
) &&
520 kvm_read_c0_guest_config1(vcpu
->cop0
) & MIPS_CONF1_FP
;
523 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch
*vcpu
)
525 return (!__builtin_constant_p(cpu_has_msa
) || cpu_has_msa
) &&
529 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch
*vcpu
)
531 return kvm_mips_guest_can_have_msa(vcpu
) &&
532 kvm_read_c0_guest_config3(vcpu
->cop0
) & MIPS_CONF3_MSA
;
535 struct kvm_mips_callbacks
{
536 int (*handle_cop_unusable
)(struct kvm_vcpu
*vcpu
);
537 int (*handle_tlb_mod
)(struct kvm_vcpu
*vcpu
);
538 int (*handle_tlb_ld_miss
)(struct kvm_vcpu
*vcpu
);
539 int (*handle_tlb_st_miss
)(struct kvm_vcpu
*vcpu
);
540 int (*handle_addr_err_st
)(struct kvm_vcpu
*vcpu
);
541 int (*handle_addr_err_ld
)(struct kvm_vcpu
*vcpu
);
542 int (*handle_syscall
)(struct kvm_vcpu
*vcpu
);
543 int (*handle_res_inst
)(struct kvm_vcpu
*vcpu
);
544 int (*handle_break
)(struct kvm_vcpu
*vcpu
);
545 int (*handle_trap
)(struct kvm_vcpu
*vcpu
);
546 int (*handle_msa_fpe
)(struct kvm_vcpu
*vcpu
);
547 int (*handle_fpe
)(struct kvm_vcpu
*vcpu
);
548 int (*handle_msa_disabled
)(struct kvm_vcpu
*vcpu
);
549 int (*vm_init
)(struct kvm
*kvm
);
550 int (*vcpu_init
)(struct kvm_vcpu
*vcpu
);
551 int (*vcpu_setup
)(struct kvm_vcpu
*vcpu
);
552 gpa_t (*gva_to_gpa
)(gva_t gva
);
553 void (*queue_timer_int
)(struct kvm_vcpu
*vcpu
);
554 void (*dequeue_timer_int
)(struct kvm_vcpu
*vcpu
);
555 void (*queue_io_int
)(struct kvm_vcpu
*vcpu
,
556 struct kvm_mips_interrupt
*irq
);
557 void (*dequeue_io_int
)(struct kvm_vcpu
*vcpu
,
558 struct kvm_mips_interrupt
*irq
);
559 int (*irq_deliver
)(struct kvm_vcpu
*vcpu
, unsigned int priority
,
561 int (*irq_clear
)(struct kvm_vcpu
*vcpu
, unsigned int priority
,
563 int (*get_one_reg
)(struct kvm_vcpu
*vcpu
,
564 const struct kvm_one_reg
*reg
, s64
*v
);
565 int (*set_one_reg
)(struct kvm_vcpu
*vcpu
,
566 const struct kvm_one_reg
*reg
, s64 v
);
567 int (*vcpu_get_regs
)(struct kvm_vcpu
*vcpu
);
568 int (*vcpu_set_regs
)(struct kvm_vcpu
*vcpu
);
570 extern struct kvm_mips_callbacks
*kvm_mips_callbacks
;
571 int kvm_mips_emulation_init(struct kvm_mips_callbacks
**install_callbacks
);
573 /* Debug: dump vcpu state */
574 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu
*vcpu
);
576 /* Trampoline ASM routine to start running in "Guest" context */
577 extern int __kvm_mips_vcpu_run(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
);
579 /* FPU/MSA context management */
580 void __kvm_save_fpu(struct kvm_vcpu_arch
*vcpu
);
581 void __kvm_restore_fpu(struct kvm_vcpu_arch
*vcpu
);
582 void __kvm_restore_fcsr(struct kvm_vcpu_arch
*vcpu
);
583 void __kvm_save_msa(struct kvm_vcpu_arch
*vcpu
);
584 void __kvm_restore_msa(struct kvm_vcpu_arch
*vcpu
);
585 void __kvm_restore_msa_upper(struct kvm_vcpu_arch
*vcpu
);
586 void __kvm_restore_msacsr(struct kvm_vcpu_arch
*vcpu
);
587 void kvm_own_fpu(struct kvm_vcpu
*vcpu
);
588 void kvm_own_msa(struct kvm_vcpu
*vcpu
);
589 void kvm_drop_fpu(struct kvm_vcpu
*vcpu
);
590 void kvm_lose_fpu(struct kvm_vcpu
*vcpu
);
593 u32
kvm_get_kernel_asid(struct kvm_vcpu
*vcpu
);
595 u32
kvm_get_user_asid(struct kvm_vcpu
*vcpu
);
597 u32
kvm_get_commpage_asid (struct kvm_vcpu
*vcpu
);
599 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr
,
600 struct kvm_vcpu
*vcpu
);
602 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr
,
603 struct kvm_vcpu
*vcpu
);
605 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu
*vcpu
,
606 struct kvm_mips_tlb
*tlb
);
608 extern enum emulation_result
kvm_mips_handle_tlbmiss(u32 cause
,
611 struct kvm_vcpu
*vcpu
);
613 extern enum emulation_result
kvm_mips_handle_tlbmod(u32 cause
,
616 struct kvm_vcpu
*vcpu
);
618 extern void kvm_mips_dump_host_tlbs(void);
619 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu
*vcpu
);
620 extern int kvm_mips_host_tlb_write(struct kvm_vcpu
*vcpu
, unsigned long entryhi
,
621 unsigned long entrylo0
,
622 unsigned long entrylo1
,
623 int flush_dcache_mask
);
624 extern void kvm_mips_flush_host_tlb(int skip_kseg0
);
625 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu
*vcpu
, unsigned long entryhi
);
627 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu
*vcpu
,
628 unsigned long entryhi
);
629 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu
*vcpu
, unsigned long vaddr
);
630 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu
*vcpu
,
632 extern void kvm_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
,
633 struct kvm_vcpu
*vcpu
);
634 extern void kvm_local_flush_tlb_all(void);
635 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu
*vcpu
);
636 extern void kvm_mips_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
);
637 extern void kvm_mips_vcpu_put(struct kvm_vcpu
*vcpu
);
640 u32
kvm_get_inst(u32
*opc
, struct kvm_vcpu
*vcpu
);
641 enum emulation_result
update_pc(struct kvm_vcpu
*vcpu
, u32 cause
);
643 extern enum emulation_result
kvm_mips_emulate_inst(u32 cause
,
646 struct kvm_vcpu
*vcpu
);
648 extern enum emulation_result
kvm_mips_emulate_syscall(u32 cause
,
651 struct kvm_vcpu
*vcpu
);
653 extern enum emulation_result
kvm_mips_emulate_tlbmiss_ld(u32 cause
,
656 struct kvm_vcpu
*vcpu
);
658 extern enum emulation_result
kvm_mips_emulate_tlbinv_ld(u32 cause
,
661 struct kvm_vcpu
*vcpu
);
663 extern enum emulation_result
kvm_mips_emulate_tlbmiss_st(u32 cause
,
666 struct kvm_vcpu
*vcpu
);
668 extern enum emulation_result
kvm_mips_emulate_tlbinv_st(u32 cause
,
671 struct kvm_vcpu
*vcpu
);
673 extern enum emulation_result
kvm_mips_emulate_tlbmod(u32 cause
,
676 struct kvm_vcpu
*vcpu
);
678 extern enum emulation_result
kvm_mips_emulate_fpu_exc(u32 cause
,
681 struct kvm_vcpu
*vcpu
);
683 extern enum emulation_result
kvm_mips_handle_ri(u32 cause
,
686 struct kvm_vcpu
*vcpu
);
688 extern enum emulation_result
kvm_mips_emulate_ri_exc(u32 cause
,
691 struct kvm_vcpu
*vcpu
);
693 extern enum emulation_result
kvm_mips_emulate_bp_exc(u32 cause
,
696 struct kvm_vcpu
*vcpu
);
698 extern enum emulation_result
kvm_mips_emulate_trap_exc(u32 cause
,
701 struct kvm_vcpu
*vcpu
);
703 extern enum emulation_result
kvm_mips_emulate_msafpe_exc(u32 cause
,
706 struct kvm_vcpu
*vcpu
);
708 extern enum emulation_result
kvm_mips_emulate_fpe_exc(u32 cause
,
711 struct kvm_vcpu
*vcpu
);
713 extern enum emulation_result
kvm_mips_emulate_msadis_exc(u32 cause
,
716 struct kvm_vcpu
*vcpu
);
718 extern enum emulation_result
kvm_mips_complete_mmio_load(struct kvm_vcpu
*vcpu
,
719 struct kvm_run
*run
);
721 u32
kvm_mips_read_count(struct kvm_vcpu
*vcpu
);
722 void kvm_mips_write_count(struct kvm_vcpu
*vcpu
, u32 count
);
723 void kvm_mips_write_compare(struct kvm_vcpu
*vcpu
, u32 compare
, bool ack
);
724 void kvm_mips_init_count(struct kvm_vcpu
*vcpu
);
725 int kvm_mips_set_count_ctl(struct kvm_vcpu
*vcpu
, s64 count_ctl
);
726 int kvm_mips_set_count_resume(struct kvm_vcpu
*vcpu
, s64 count_resume
);
727 int kvm_mips_set_count_hz(struct kvm_vcpu
*vcpu
, s64 count_hz
);
728 void kvm_mips_count_enable_cause(struct kvm_vcpu
*vcpu
);
729 void kvm_mips_count_disable_cause(struct kvm_vcpu
*vcpu
);
730 enum hrtimer_restart
kvm_mips_count_timeout(struct kvm_vcpu
*vcpu
);
732 enum emulation_result
kvm_mips_check_privilege(u32 cause
,
735 struct kvm_vcpu
*vcpu
);
737 enum emulation_result
kvm_mips_emulate_cache(union mips_instruction inst
,
741 struct kvm_vcpu
*vcpu
);
742 enum emulation_result
kvm_mips_emulate_CP0(union mips_instruction inst
,
746 struct kvm_vcpu
*vcpu
);
747 enum emulation_result
kvm_mips_emulate_store(union mips_instruction inst
,
750 struct kvm_vcpu
*vcpu
);
751 enum emulation_result
kvm_mips_emulate_load(union mips_instruction inst
,
754 struct kvm_vcpu
*vcpu
);
756 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu
*vcpu
);
757 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu
*vcpu
);
758 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu
*vcpu
);
759 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu
*vcpu
);
761 /* Dynamic binary translation */
762 extern int kvm_mips_trans_cache_index(union mips_instruction inst
,
763 u32
*opc
, struct kvm_vcpu
*vcpu
);
764 extern int kvm_mips_trans_cache_va(union mips_instruction inst
, u32
*opc
,
765 struct kvm_vcpu
*vcpu
);
766 extern int kvm_mips_trans_mfc0(union mips_instruction inst
, u32
*opc
,
767 struct kvm_vcpu
*vcpu
);
768 extern int kvm_mips_trans_mtc0(union mips_instruction inst
, u32
*opc
,
769 struct kvm_vcpu
*vcpu
);
772 extern void kvm_mips_dump_stats(struct kvm_vcpu
*vcpu
);
773 extern unsigned long kvm_mips_get_ramsize(struct kvm
*kvm
);
775 static inline void kvm_arch_hardware_disable(void) {}
776 static inline void kvm_arch_hardware_unsetup(void) {}
777 static inline void kvm_arch_sync_events(struct kvm
*kvm
) {}
778 static inline void kvm_arch_free_memslot(struct kvm
*kvm
,
779 struct kvm_memory_slot
*free
, struct kvm_memory_slot
*dont
) {}
780 static inline void kvm_arch_memslots_updated(struct kvm
*kvm
, struct kvm_memslots
*slots
) {}
781 static inline void kvm_arch_flush_shadow_all(struct kvm
*kvm
) {}
782 static inline void kvm_arch_flush_shadow_memslot(struct kvm
*kvm
,
783 struct kvm_memory_slot
*slot
) {}
784 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu
*vcpu
) {}
785 static inline void kvm_arch_sched_in(struct kvm_vcpu
*vcpu
, int cpu
) {}
786 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu
*vcpu
) {}
787 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu
*vcpu
) {}
788 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu
*vcpu
) {}
790 #endif /* __MIPS_KVM_HOST_H__ */