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[deliverable/linux.git] / arch / mips / include / asm / kvm_host.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 #include <asm/inst.h>
23 #include <asm/mipsregs.h>
24
25 /* MIPS KVM register ids */
26 #define MIPS_CP0_32(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
28
29 #define MIPS_CP0_64(_R, _S) \
30 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
31
32 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
33 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
34 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
35 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
36 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
37 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
38 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
39 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
40 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
41 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
42 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
43 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
44 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
45 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
46 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
47 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
48 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
49 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
50 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
51 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
52 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
53 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
54 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
55 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
56 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
57 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
58 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
59 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
60 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
61 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
62 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
63 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
64 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
65
66
67 #define KVM_MAX_VCPUS 1
68 #define KVM_USER_MEM_SLOTS 8
69 /* memory slots that does not exposed to userspace */
70 #define KVM_PRIVATE_MEM_SLOTS 0
71
72 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
73 #define KVM_HALT_POLL_NS_DEFAULT 500000
74
75
76
77 /*
78 * Special address that contains the comm page, used for reducing # of traps
79 * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
80 * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
81 * caught.
82 */
83 #define KVM_GUEST_COMMPAGE_ADDR ((PAGE_SIZE > 0x8000) ? 0 : \
84 (0x8000 - PAGE_SIZE))
85
86 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
87 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
88
89 #define KVM_GUEST_KUSEG 0x00000000UL
90 #define KVM_GUEST_KSEG0 0x40000000UL
91 #define KVM_GUEST_KSEG23 0x60000000UL
92 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
93 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
94
95 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
96 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
97 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
98
99 /*
100 * Map an address to a certain kernel segment
101 */
102 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
103 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
104 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
105
106 #define KVM_INVALID_PAGE 0xdeadbeef
107 #define KVM_INVALID_INST 0xdeadbeef
108 #define KVM_INVALID_ADDR 0xdeadbeef
109
110 extern atomic_t kvm_mips_instance;
111
112 struct kvm_vm_stat {
113 u32 remote_tlb_flush;
114 };
115
116 struct kvm_vcpu_stat {
117 u32 wait_exits;
118 u32 cache_exits;
119 u32 signal_exits;
120 u32 int_exits;
121 u32 cop_unusable_exits;
122 u32 tlbmod_exits;
123 u32 tlbmiss_ld_exits;
124 u32 tlbmiss_st_exits;
125 u32 addrerr_st_exits;
126 u32 addrerr_ld_exits;
127 u32 syscall_exits;
128 u32 resvd_inst_exits;
129 u32 break_inst_exits;
130 u32 trap_inst_exits;
131 u32 msa_fpe_exits;
132 u32 fpe_exits;
133 u32 msa_disabled_exits;
134 u32 flush_dcache_exits;
135 u32 halt_successful_poll;
136 u32 halt_attempted_poll;
137 u32 halt_poll_invalid;
138 u32 halt_wakeup;
139 };
140
141 struct kvm_arch_memory_slot {
142 };
143
144 struct kvm_arch {
145 /* Guest GVA->HPA page table */
146 unsigned long *guest_pmap;
147 unsigned long guest_pmap_npages;
148
149 /* Wired host TLB used for the commpage */
150 int commpage_tlb;
151 };
152
153 #define N_MIPS_COPROC_REGS 32
154 #define N_MIPS_COPROC_SEL 8
155
156 struct mips_coproc {
157 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
158 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
159 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
160 #endif
161 };
162
163 /*
164 * Coprocessor 0 register names
165 */
166 #define MIPS_CP0_TLB_INDEX 0
167 #define MIPS_CP0_TLB_RANDOM 1
168 #define MIPS_CP0_TLB_LOW 2
169 #define MIPS_CP0_TLB_LO0 2
170 #define MIPS_CP0_TLB_LO1 3
171 #define MIPS_CP0_TLB_CONTEXT 4
172 #define MIPS_CP0_TLB_PG_MASK 5
173 #define MIPS_CP0_TLB_WIRED 6
174 #define MIPS_CP0_HWRENA 7
175 #define MIPS_CP0_BAD_VADDR 8
176 #define MIPS_CP0_COUNT 9
177 #define MIPS_CP0_TLB_HI 10
178 #define MIPS_CP0_COMPARE 11
179 #define MIPS_CP0_STATUS 12
180 #define MIPS_CP0_CAUSE 13
181 #define MIPS_CP0_EXC_PC 14
182 #define MIPS_CP0_PRID 15
183 #define MIPS_CP0_CONFIG 16
184 #define MIPS_CP0_LLADDR 17
185 #define MIPS_CP0_WATCH_LO 18
186 #define MIPS_CP0_WATCH_HI 19
187 #define MIPS_CP0_TLB_XCONTEXT 20
188 #define MIPS_CP0_ECC 26
189 #define MIPS_CP0_CACHE_ERR 27
190 #define MIPS_CP0_TAG_LO 28
191 #define MIPS_CP0_TAG_HI 29
192 #define MIPS_CP0_ERROR_PC 30
193 #define MIPS_CP0_DEBUG 23
194 #define MIPS_CP0_DEPC 24
195 #define MIPS_CP0_PERFCNT 25
196 #define MIPS_CP0_ERRCTL 26
197 #define MIPS_CP0_DATA_LO 28
198 #define MIPS_CP0_DATA_HI 29
199 #define MIPS_CP0_DESAVE 31
200
201 #define MIPS_CP0_CONFIG_SEL 0
202 #define MIPS_CP0_CONFIG1_SEL 1
203 #define MIPS_CP0_CONFIG2_SEL 2
204 #define MIPS_CP0_CONFIG3_SEL 3
205 #define MIPS_CP0_CONFIG4_SEL 4
206 #define MIPS_CP0_CONFIG5_SEL 5
207
208 /* Config0 register bits */
209 #define CP0C0_M 31
210 #define CP0C0_K23 28
211 #define CP0C0_KU 25
212 #define CP0C0_MDU 20
213 #define CP0C0_MM 17
214 #define CP0C0_BM 16
215 #define CP0C0_BE 15
216 #define CP0C0_AT 13
217 #define CP0C0_AR 10
218 #define CP0C0_MT 7
219 #define CP0C0_VI 3
220 #define CP0C0_K0 0
221
222 /* Config1 register bits */
223 #define CP0C1_M 31
224 #define CP0C1_MMU 25
225 #define CP0C1_IS 22
226 #define CP0C1_IL 19
227 #define CP0C1_IA 16
228 #define CP0C1_DS 13
229 #define CP0C1_DL 10
230 #define CP0C1_DA 7
231 #define CP0C1_C2 6
232 #define CP0C1_MD 5
233 #define CP0C1_PC 4
234 #define CP0C1_WR 3
235 #define CP0C1_CA 2
236 #define CP0C1_EP 1
237 #define CP0C1_FP 0
238
239 /* Config2 Register bits */
240 #define CP0C2_M 31
241 #define CP0C2_TU 28
242 #define CP0C2_TS 24
243 #define CP0C2_TL 20
244 #define CP0C2_TA 16
245 #define CP0C2_SU 12
246 #define CP0C2_SS 8
247 #define CP0C2_SL 4
248 #define CP0C2_SA 0
249
250 /* Config3 Register bits */
251 #define CP0C3_M 31
252 #define CP0C3_ISA_ON_EXC 16
253 #define CP0C3_ULRI 13
254 #define CP0C3_DSPP 10
255 #define CP0C3_LPA 7
256 #define CP0C3_VEIC 6
257 #define CP0C3_VInt 5
258 #define CP0C3_SP 4
259 #define CP0C3_MT 2
260 #define CP0C3_SM 1
261 #define CP0C3_TL 0
262
263 /* MMU types, the first four entries have the same layout as the
264 CP0C0_MT field. */
265 enum mips_mmu_types {
266 MMU_TYPE_NONE,
267 MMU_TYPE_R4000,
268 MMU_TYPE_RESERVED,
269 MMU_TYPE_FMT,
270 MMU_TYPE_R3000,
271 MMU_TYPE_R6000,
272 MMU_TYPE_R8000
273 };
274
275 /* Resume Flags */
276 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
277 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
278
279 #define RESUME_GUEST 0
280 #define RESUME_GUEST_DR RESUME_FLAG_DR
281 #define RESUME_HOST RESUME_FLAG_HOST
282
283 enum emulation_result {
284 EMULATE_DONE, /* no further processing */
285 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
286 EMULATE_FAIL, /* can't emulate this instruction */
287 EMULATE_WAIT, /* WAIT instruction */
288 EMULATE_PRIV_FAIL,
289 };
290
291 #define mips3_paddr_to_tlbpfn(x) \
292 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
293 #define mips3_tlbpfn_to_paddr(x) \
294 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
295
296 #define MIPS3_PG_SHIFT 6
297 #define MIPS3_PG_FRAME 0x3fffffc0
298
299 #define VPN2_MASK 0xffffe000
300 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
301 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
302 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
303 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
304 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
305 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
306 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
307 ((y) & VPN2_MASK & ~(x).tlb_mask))
308 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
309 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
310
311 struct kvm_mips_tlb {
312 long tlb_mask;
313 long tlb_hi;
314 long tlb_lo[2];
315 };
316
317 #define KVM_MIPS_AUX_FPU 0x1
318 #define KVM_MIPS_AUX_MSA 0x2
319
320 #define KVM_MIPS_GUEST_TLB_SIZE 64
321 struct kvm_vcpu_arch {
322 void *guest_ebase;
323 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
324 unsigned long host_stack;
325 unsigned long host_gp;
326
327 /* Host CP0 registers used when handling exits from guest */
328 unsigned long host_cp0_badvaddr;
329 unsigned long host_cp0_epc;
330 u32 host_cp0_cause;
331
332 /* GPRS */
333 unsigned long gprs[32];
334 unsigned long hi;
335 unsigned long lo;
336 unsigned long pc;
337
338 /* FPU State */
339 struct mips_fpu_struct fpu;
340 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
341 unsigned int aux_inuse;
342
343 /* COP0 State */
344 struct mips_coproc *cop0;
345
346 /* Host KSEG0 address of the EI/DI offset */
347 void *kseg0_commpage;
348
349 u32 io_gpr; /* GPR used as IO source/target */
350
351 struct hrtimer comparecount_timer;
352 /* Count timer control KVM register */
353 u32 count_ctl;
354 /* Count bias from the raw time */
355 u32 count_bias;
356 /* Frequency of timer in Hz */
357 u32 count_hz;
358 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
359 s64 count_dyn_bias;
360 /* Resume time */
361 ktime_t count_resume;
362 /* Period of timer tick in ns */
363 u64 count_period;
364
365 /* Bitmask of exceptions that are pending */
366 unsigned long pending_exceptions;
367
368 /* Bitmask of pending exceptions to be cleared */
369 unsigned long pending_exceptions_clr;
370
371 u32 pending_load_cause;
372
373 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
374 unsigned long preempt_entryhi;
375
376 /* S/W Based TLB for guest */
377 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
378
379 /* Cached guest kernel/user ASIDs */
380 u32 guest_user_asid[NR_CPUS];
381 u32 guest_kernel_asid[NR_CPUS];
382 struct mm_struct guest_kernel_mm, guest_user_mm;
383
384 int last_sched_cpu;
385
386 /* WAIT executed */
387 int wait;
388
389 u8 fpu_enabled;
390 u8 msa_enabled;
391 u8 kscratch_enabled;
392 };
393
394
395 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
396 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
397 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
398 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
399 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
400 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
401 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
402 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
403 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
404 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
405 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
406 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
407 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
408 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
409 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
410 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
411 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
412 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
413 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
414 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
415 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
416 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
417 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
418 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
419 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
420 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
421 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
422 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
423 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
424 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
425 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
426 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
427 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
428 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
429 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
430 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
431 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
432 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
433 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
434 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
435 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
436 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
437 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
438 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
439 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
440 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
441 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
442 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
443 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
444 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
445 #define kvm_read_c0_guest_kscratch1(cop0) (cop0->reg[MIPS_CP0_DESAVE][2])
446 #define kvm_read_c0_guest_kscratch2(cop0) (cop0->reg[MIPS_CP0_DESAVE][3])
447 #define kvm_read_c0_guest_kscratch3(cop0) (cop0->reg[MIPS_CP0_DESAVE][4])
448 #define kvm_read_c0_guest_kscratch4(cop0) (cop0->reg[MIPS_CP0_DESAVE][5])
449 #define kvm_read_c0_guest_kscratch5(cop0) (cop0->reg[MIPS_CP0_DESAVE][6])
450 #define kvm_read_c0_guest_kscratch6(cop0) (cop0->reg[MIPS_CP0_DESAVE][7])
451 #define kvm_write_c0_guest_kscratch1(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][2] = (val))
452 #define kvm_write_c0_guest_kscratch2(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][3] = (val))
453 #define kvm_write_c0_guest_kscratch3(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][4] = (val))
454 #define kvm_write_c0_guest_kscratch4(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][5] = (val))
455 #define kvm_write_c0_guest_kscratch5(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][6] = (val))
456 #define kvm_write_c0_guest_kscratch6(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][7] = (val))
457
458 /*
459 * Some of the guest registers may be modified asynchronously (e.g. from a
460 * hrtimer callback in hard irq context) and therefore need stronger atomicity
461 * guarantees than other registers.
462 */
463
464 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
465 unsigned long val)
466 {
467 unsigned long temp;
468 do {
469 __asm__ __volatile__(
470 " .set mips3 \n"
471 " " __LL "%0, %1 \n"
472 " or %0, %2 \n"
473 " " __SC "%0, %1 \n"
474 " .set mips0 \n"
475 : "=&r" (temp), "+m" (*reg)
476 : "r" (val));
477 } while (unlikely(!temp));
478 }
479
480 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
481 unsigned long val)
482 {
483 unsigned long temp;
484 do {
485 __asm__ __volatile__(
486 " .set mips3 \n"
487 " " __LL "%0, %1 \n"
488 " and %0, %2 \n"
489 " " __SC "%0, %1 \n"
490 " .set mips0 \n"
491 : "=&r" (temp), "+m" (*reg)
492 : "r" (~val));
493 } while (unlikely(!temp));
494 }
495
496 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
497 unsigned long change,
498 unsigned long val)
499 {
500 unsigned long temp;
501 do {
502 __asm__ __volatile__(
503 " .set mips3 \n"
504 " " __LL "%0, %1 \n"
505 " and %0, %2 \n"
506 " or %0, %3 \n"
507 " " __SC "%0, %1 \n"
508 " .set mips0 \n"
509 : "=&r" (temp), "+m" (*reg)
510 : "r" (~change), "r" (val & change));
511 } while (unlikely(!temp));
512 }
513
514 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
515 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
516
517 /* Cause can be modified asynchronously from hardirq hrtimer callback */
518 #define kvm_set_c0_guest_cause(cop0, val) \
519 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
520 #define kvm_clear_c0_guest_cause(cop0, val) \
521 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
522 #define kvm_change_c0_guest_cause(cop0, change, val) \
523 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
524 change, val)
525
526 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
527 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
528 #define kvm_change_c0_guest_ebase(cop0, change, val) \
529 { \
530 kvm_clear_c0_guest_ebase(cop0, change); \
531 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
532 }
533
534 /* Helpers */
535
536 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
537 {
538 return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
539 vcpu->fpu_enabled;
540 }
541
542 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
543 {
544 return kvm_mips_guest_can_have_fpu(vcpu) &&
545 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
546 }
547
548 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
549 {
550 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
551 vcpu->msa_enabled;
552 }
553
554 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
555 {
556 return kvm_mips_guest_can_have_msa(vcpu) &&
557 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
558 }
559
560 struct kvm_mips_callbacks {
561 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
562 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
563 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
564 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
565 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
566 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
567 int (*handle_syscall)(struct kvm_vcpu *vcpu);
568 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
569 int (*handle_break)(struct kvm_vcpu *vcpu);
570 int (*handle_trap)(struct kvm_vcpu *vcpu);
571 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
572 int (*handle_fpe)(struct kvm_vcpu *vcpu);
573 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
574 int (*vm_init)(struct kvm *kvm);
575 int (*vcpu_init)(struct kvm_vcpu *vcpu);
576 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
577 gpa_t (*gva_to_gpa)(gva_t gva);
578 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
579 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
580 void (*queue_io_int)(struct kvm_vcpu *vcpu,
581 struct kvm_mips_interrupt *irq);
582 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
583 struct kvm_mips_interrupt *irq);
584 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
585 u32 cause);
586 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
587 u32 cause);
588 unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
589 int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
590 int (*get_one_reg)(struct kvm_vcpu *vcpu,
591 const struct kvm_one_reg *reg, s64 *v);
592 int (*set_one_reg)(struct kvm_vcpu *vcpu,
593 const struct kvm_one_reg *reg, s64 v);
594 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
595 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
596 };
597 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
598 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
599
600 /* Debug: dump vcpu state */
601 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
602
603 /* Trampoline ASM routine to start running in "Guest" context */
604 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
605
606 /* FPU/MSA context management */
607 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
608 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
609 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
610 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
611 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
612 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
613 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
614 void kvm_own_fpu(struct kvm_vcpu *vcpu);
615 void kvm_own_msa(struct kvm_vcpu *vcpu);
616 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
617 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
618
619 /* TLB handling */
620 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
621
622 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
623
624 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
625
626 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
627 struct kvm_vcpu *vcpu);
628
629 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
630 struct kvm_vcpu *vcpu);
631
632 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
633 struct kvm_mips_tlb *tlb);
634
635 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
636 u32 *opc,
637 struct kvm_run *run,
638 struct kvm_vcpu *vcpu);
639
640 extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause,
641 u32 *opc,
642 struct kvm_run *run,
643 struct kvm_vcpu *vcpu);
644
645 extern void kvm_mips_dump_host_tlbs(void);
646 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
647 extern int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
648 unsigned long entrylo0,
649 unsigned long entrylo1,
650 int flush_dcache_mask);
651 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
652 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
653
654 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
655 unsigned long entryhi);
656 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
657 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
658 unsigned long gva);
659 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
660 struct kvm_vcpu *vcpu);
661 extern void kvm_local_flush_tlb_all(void);
662 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
663 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
664 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
665
666 /* Emulation */
667 u32 kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu);
668 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
669
670 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
671 u32 *opc,
672 struct kvm_run *run,
673 struct kvm_vcpu *vcpu);
674
675 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
676 u32 *opc,
677 struct kvm_run *run,
678 struct kvm_vcpu *vcpu);
679
680 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
681 u32 *opc,
682 struct kvm_run *run,
683 struct kvm_vcpu *vcpu);
684
685 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
686 u32 *opc,
687 struct kvm_run *run,
688 struct kvm_vcpu *vcpu);
689
690 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
691 u32 *opc,
692 struct kvm_run *run,
693 struct kvm_vcpu *vcpu);
694
695 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
696 u32 *opc,
697 struct kvm_run *run,
698 struct kvm_vcpu *vcpu);
699
700 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
701 u32 *opc,
702 struct kvm_run *run,
703 struct kvm_vcpu *vcpu);
704
705 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
706 u32 *opc,
707 struct kvm_run *run,
708 struct kvm_vcpu *vcpu);
709
710 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
711 u32 *opc,
712 struct kvm_run *run,
713 struct kvm_vcpu *vcpu);
714
715 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
716 u32 *opc,
717 struct kvm_run *run,
718 struct kvm_vcpu *vcpu);
719
720 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
721 u32 *opc,
722 struct kvm_run *run,
723 struct kvm_vcpu *vcpu);
724
725 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
726 u32 *opc,
727 struct kvm_run *run,
728 struct kvm_vcpu *vcpu);
729
730 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
731 u32 *opc,
732 struct kvm_run *run,
733 struct kvm_vcpu *vcpu);
734
735 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
736 u32 *opc,
737 struct kvm_run *run,
738 struct kvm_vcpu *vcpu);
739
740 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
741 u32 *opc,
742 struct kvm_run *run,
743 struct kvm_vcpu *vcpu);
744
745 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
746 struct kvm_run *run);
747
748 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
749 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
750 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
751 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
752 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
753 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
754 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
755 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
756 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
757 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
758
759 enum emulation_result kvm_mips_check_privilege(u32 cause,
760 u32 *opc,
761 struct kvm_run *run,
762 struct kvm_vcpu *vcpu);
763
764 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
765 u32 *opc,
766 u32 cause,
767 struct kvm_run *run,
768 struct kvm_vcpu *vcpu);
769 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
770 u32 *opc,
771 u32 cause,
772 struct kvm_run *run,
773 struct kvm_vcpu *vcpu);
774 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
775 u32 cause,
776 struct kvm_run *run,
777 struct kvm_vcpu *vcpu);
778 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
779 u32 cause,
780 struct kvm_run *run,
781 struct kvm_vcpu *vcpu);
782
783 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
784 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
785 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
786 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
787
788 /* Dynamic binary translation */
789 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
790 u32 *opc, struct kvm_vcpu *vcpu);
791 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
792 struct kvm_vcpu *vcpu);
793 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
794 struct kvm_vcpu *vcpu);
795 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
796 struct kvm_vcpu *vcpu);
797
798 /* Misc */
799 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
800 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
801
802 static inline void kvm_arch_hardware_disable(void) {}
803 static inline void kvm_arch_hardware_unsetup(void) {}
804 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
805 static inline void kvm_arch_free_memslot(struct kvm *kvm,
806 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
807 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
808 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
809 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
810 struct kvm_memory_slot *slot) {}
811 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
812 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
813 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
814 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
815 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
816
817 #endif /* __MIPS_KVM_HOST_H__ */
Linux kernel - Deliverables
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