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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/livep...
[deliverable/linux.git] / arch / mips / include / asm / kvm_host.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
25
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
28
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
46 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
47 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
48 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
49 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
50 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
51 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
52 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
53
54
55 #define KVM_MAX_VCPUS 1
56 #define KVM_USER_MEM_SLOTS 8
57 /* memory slots that does not exposed to userspace */
58 #define KVM_PRIVATE_MEM_SLOTS 0
59
60 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
61
62
63
64 /* Special address that contains the comm page, used for reducing # of traps */
65 #define KVM_GUEST_COMMPAGE_ADDR 0x0
66
67 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
68 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
69
70 #define KVM_GUEST_KUSEG 0x00000000UL
71 #define KVM_GUEST_KSEG0 0x40000000UL
72 #define KVM_GUEST_KSEG23 0x60000000UL
73 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
74 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
75
76 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
77 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
78 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
79
80 /*
81 * Map an address to a certain kernel segment
82 */
83 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
84 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
85 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
86
87 #define KVM_INVALID_PAGE 0xdeadbeef
88 #define KVM_INVALID_INST 0xdeadbeef
89 #define KVM_INVALID_ADDR 0xdeadbeef
90
91 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
92
93 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
94 #define MS_TO_NS(x) (x * 1E6L)
95
96 #define CAUSEB_DC 27
97 #define CAUSEF_DC (_ULCAST_(1) << 27)
98
99 extern atomic_t kvm_mips_instance;
100 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
101 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
102 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
103
104 struct kvm_vm_stat {
105 u32 remote_tlb_flush;
106 };
107
108 struct kvm_vcpu_stat {
109 u32 wait_exits;
110 u32 cache_exits;
111 u32 signal_exits;
112 u32 int_exits;
113 u32 cop_unusable_exits;
114 u32 tlbmod_exits;
115 u32 tlbmiss_ld_exits;
116 u32 tlbmiss_st_exits;
117 u32 addrerr_st_exits;
118 u32 addrerr_ld_exits;
119 u32 syscall_exits;
120 u32 resvd_inst_exits;
121 u32 break_inst_exits;
122 u32 flush_dcache_exits;
123 u32 halt_successful_poll;
124 u32 halt_wakeup;
125 };
126
127 enum kvm_mips_exit_types {
128 WAIT_EXITS,
129 CACHE_EXITS,
130 SIGNAL_EXITS,
131 INT_EXITS,
132 COP_UNUSABLE_EXITS,
133 TLBMOD_EXITS,
134 TLBMISS_LD_EXITS,
135 TLBMISS_ST_EXITS,
136 ADDRERR_ST_EXITS,
137 ADDRERR_LD_EXITS,
138 SYSCALL_EXITS,
139 RESVD_INST_EXITS,
140 BREAK_INST_EXITS,
141 FLUSH_DCACHE_EXITS,
142 MAX_KVM_MIPS_EXIT_TYPES
143 };
144
145 struct kvm_arch_memory_slot {
146 };
147
148 struct kvm_arch {
149 /* Guest GVA->HPA page table */
150 unsigned long *guest_pmap;
151 unsigned long guest_pmap_npages;
152
153 /* Wired host TLB used for the commpage */
154 int commpage_tlb;
155 };
156
157 #define N_MIPS_COPROC_REGS 32
158 #define N_MIPS_COPROC_SEL 8
159
160 struct mips_coproc {
161 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
162 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
163 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
164 #endif
165 };
166
167 /*
168 * Coprocessor 0 register names
169 */
170 #define MIPS_CP0_TLB_INDEX 0
171 #define MIPS_CP0_TLB_RANDOM 1
172 #define MIPS_CP0_TLB_LOW 2
173 #define MIPS_CP0_TLB_LO0 2
174 #define MIPS_CP0_TLB_LO1 3
175 #define MIPS_CP0_TLB_CONTEXT 4
176 #define MIPS_CP0_TLB_PG_MASK 5
177 #define MIPS_CP0_TLB_WIRED 6
178 #define MIPS_CP0_HWRENA 7
179 #define MIPS_CP0_BAD_VADDR 8
180 #define MIPS_CP0_COUNT 9
181 #define MIPS_CP0_TLB_HI 10
182 #define MIPS_CP0_COMPARE 11
183 #define MIPS_CP0_STATUS 12
184 #define MIPS_CP0_CAUSE 13
185 #define MIPS_CP0_EXC_PC 14
186 #define MIPS_CP0_PRID 15
187 #define MIPS_CP0_CONFIG 16
188 #define MIPS_CP0_LLADDR 17
189 #define MIPS_CP0_WATCH_LO 18
190 #define MIPS_CP0_WATCH_HI 19
191 #define MIPS_CP0_TLB_XCONTEXT 20
192 #define MIPS_CP0_ECC 26
193 #define MIPS_CP0_CACHE_ERR 27
194 #define MIPS_CP0_TAG_LO 28
195 #define MIPS_CP0_TAG_HI 29
196 #define MIPS_CP0_ERROR_PC 30
197 #define MIPS_CP0_DEBUG 23
198 #define MIPS_CP0_DEPC 24
199 #define MIPS_CP0_PERFCNT 25
200 #define MIPS_CP0_ERRCTL 26
201 #define MIPS_CP0_DATA_LO 28
202 #define MIPS_CP0_DATA_HI 29
203 #define MIPS_CP0_DESAVE 31
204
205 #define MIPS_CP0_CONFIG_SEL 0
206 #define MIPS_CP0_CONFIG1_SEL 1
207 #define MIPS_CP0_CONFIG2_SEL 2
208 #define MIPS_CP0_CONFIG3_SEL 3
209
210 /* Config0 register bits */
211 #define CP0C0_M 31
212 #define CP0C0_K23 28
213 #define CP0C0_KU 25
214 #define CP0C0_MDU 20
215 #define CP0C0_MM 17
216 #define CP0C0_BM 16
217 #define CP0C0_BE 15
218 #define CP0C0_AT 13
219 #define CP0C0_AR 10
220 #define CP0C0_MT 7
221 #define CP0C0_VI 3
222 #define CP0C0_K0 0
223
224 /* Config1 register bits */
225 #define CP0C1_M 31
226 #define CP0C1_MMU 25
227 #define CP0C1_IS 22
228 #define CP0C1_IL 19
229 #define CP0C1_IA 16
230 #define CP0C1_DS 13
231 #define CP0C1_DL 10
232 #define CP0C1_DA 7
233 #define CP0C1_C2 6
234 #define CP0C1_MD 5
235 #define CP0C1_PC 4
236 #define CP0C1_WR 3
237 #define CP0C1_CA 2
238 #define CP0C1_EP 1
239 #define CP0C1_FP 0
240
241 /* Config2 Register bits */
242 #define CP0C2_M 31
243 #define CP0C2_TU 28
244 #define CP0C2_TS 24
245 #define CP0C2_TL 20
246 #define CP0C2_TA 16
247 #define CP0C2_SU 12
248 #define CP0C2_SS 8
249 #define CP0C2_SL 4
250 #define CP0C2_SA 0
251
252 /* Config3 Register bits */
253 #define CP0C3_M 31
254 #define CP0C3_ISA_ON_EXC 16
255 #define CP0C3_ULRI 13
256 #define CP0C3_DSPP 10
257 #define CP0C3_LPA 7
258 #define CP0C3_VEIC 6
259 #define CP0C3_VInt 5
260 #define CP0C3_SP 4
261 #define CP0C3_MT 2
262 #define CP0C3_SM 1
263 #define CP0C3_TL 0
264
265 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
266 #define MIPS_CONFIG0 \
267 ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
268
269 /* Have config2, no coprocessor2 attached, no MDMX support attached,
270 no performance counters, watch registers present,
271 no code compression, EJTAG present, no FPU, no watch registers */
272 #define MIPS_CONFIG1 \
273 ((1 << CP0C1_M) | \
274 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
275 (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
276 (0 << CP0C1_FP))
277
278 /* Have config3, no tertiary/secondary caches implemented */
279 #define MIPS_CONFIG2 \
280 ((1 << CP0C2_M))
281
282 /* No config4, no DSP ASE, no large physaddr (PABITS),
283 no external interrupt controller, no vectored interrupts,
284 no 1kb pages, no SmartMIPS ASE, no trace logic */
285 #define MIPS_CONFIG3 \
286 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
287 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
288 (0 << CP0C3_SM) | (0 << CP0C3_TL))
289
290 /* MMU types, the first four entries have the same layout as the
291 CP0C0_MT field. */
292 enum mips_mmu_types {
293 MMU_TYPE_NONE,
294 MMU_TYPE_R4000,
295 MMU_TYPE_RESERVED,
296 MMU_TYPE_FMT,
297 MMU_TYPE_R3000,
298 MMU_TYPE_R6000,
299 MMU_TYPE_R8000
300 };
301
302 /*
303 * Trap codes
304 */
305 #define T_INT 0 /* Interrupt pending */
306 #define T_TLB_MOD 1 /* TLB modified fault */
307 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
308 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
309 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
310 #define T_ADDR_ERR_ST 5 /* Address error on a store */
311 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
312 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
313 #define T_SYSCALL 8 /* System call */
314 #define T_BREAK 9 /* Breakpoint */
315 #define T_RES_INST 10 /* Reserved instruction exception */
316 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
317 #define T_OVFLOW 12 /* Arithmetic overflow */
318
319 /*
320 * Trap definitions added for r4000 port.
321 */
322 #define T_TRAP 13 /* Trap instruction */
323 #define T_VCEI 14 /* Virtual coherency exception */
324 #define T_FPE 15 /* Floating point exception */
325 #define T_WATCH 23 /* Watch address reference */
326 #define T_VCED 31 /* Virtual coherency data */
327
328 /* Resume Flags */
329 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
330 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
331
332 #define RESUME_GUEST 0
333 #define RESUME_GUEST_DR RESUME_FLAG_DR
334 #define RESUME_HOST RESUME_FLAG_HOST
335
336 enum emulation_result {
337 EMULATE_DONE, /* no further processing */
338 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
339 EMULATE_FAIL, /* can't emulate this instruction */
340 EMULATE_WAIT, /* WAIT instruction */
341 EMULATE_PRIV_FAIL,
342 };
343
344 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
345 #define MIPS3_PG_V 0x00000002 /* Valid */
346 #define MIPS3_PG_NV 0x00000000
347 #define MIPS3_PG_D 0x00000004 /* Dirty */
348
349 #define mips3_paddr_to_tlbpfn(x) \
350 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
351 #define mips3_tlbpfn_to_paddr(x) \
352 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
353
354 #define MIPS3_PG_SHIFT 6
355 #define MIPS3_PG_FRAME 0x3fffffc0
356
357 #define VPN2_MASK 0xffffe000
358 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
359 ((x).tlb_lo1 & MIPS3_PG_G))
360 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
361 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
362 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
363 ? ((x).tlb_lo1 & MIPS3_PG_V) \
364 : ((x).tlb_lo0 & MIPS3_PG_V))
365 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
366 ((y) & VPN2_MASK & ~(x).tlb_mask))
367 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
368 TLB_ASID(x) == ((y) & ASID_MASK))
369
370 struct kvm_mips_tlb {
371 long tlb_mask;
372 long tlb_hi;
373 long tlb_lo0;
374 long tlb_lo1;
375 };
376
377 #define KVM_MIPS_GUEST_TLB_SIZE 64
378 struct kvm_vcpu_arch {
379 void *host_ebase, *guest_ebase;
380 unsigned long host_stack;
381 unsigned long host_gp;
382
383 /* Host CP0 registers used when handling exits from guest */
384 unsigned long host_cp0_badvaddr;
385 unsigned long host_cp0_cause;
386 unsigned long host_cp0_epc;
387 unsigned long host_cp0_entryhi;
388 uint32_t guest_inst;
389
390 /* GPRS */
391 unsigned long gprs[32];
392 unsigned long hi;
393 unsigned long lo;
394 unsigned long pc;
395
396 /* FPU State */
397 struct mips_fpu_struct fpu;
398
399 /* COP0 State */
400 struct mips_coproc *cop0;
401
402 /* Host KSEG0 address of the EI/DI offset */
403 void *kseg0_commpage;
404
405 u32 io_gpr; /* GPR used as IO source/target */
406
407 struct hrtimer comparecount_timer;
408 /* Count timer control KVM register */
409 uint32_t count_ctl;
410 /* Count bias from the raw time */
411 uint32_t count_bias;
412 /* Frequency of timer in Hz */
413 uint32_t count_hz;
414 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
415 s64 count_dyn_bias;
416 /* Resume time */
417 ktime_t count_resume;
418 /* Period of timer tick in ns */
419 u64 count_period;
420
421 /* Bitmask of exceptions that are pending */
422 unsigned long pending_exceptions;
423
424 /* Bitmask of pending exceptions to be cleared */
425 unsigned long pending_exceptions_clr;
426
427 unsigned long pending_load_cause;
428
429 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
430 unsigned long preempt_entryhi;
431
432 /* S/W Based TLB for guest */
433 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
434
435 /* Cached guest kernel/user ASIDs */
436 uint32_t guest_user_asid[NR_CPUS];
437 uint32_t guest_kernel_asid[NR_CPUS];
438 struct mm_struct guest_kernel_mm, guest_user_mm;
439
440 int last_sched_cpu;
441
442 /* WAIT executed */
443 int wait;
444 };
445
446
447 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
448 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
449 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
450 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
451 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
452 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
453 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
454 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
455 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
456 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
457 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
458 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
459 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
460 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
461 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
462 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
463 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
464 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
465 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
466 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
467 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
468 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
469 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
470 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
471 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
472 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
473 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
474 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
475 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
476 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
477 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
478 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
479 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
480 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
481 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
482 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
483 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
484 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
485 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
486 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
487 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
488 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
489 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
490 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
491 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
492 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
493
494 /*
495 * Some of the guest registers may be modified asynchronously (e.g. from a
496 * hrtimer callback in hard irq context) and therefore need stronger atomicity
497 * guarantees than other registers.
498 */
499
500 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
501 unsigned long val)
502 {
503 unsigned long temp;
504 do {
505 __asm__ __volatile__(
506 " .set mips3 \n"
507 " " __LL "%0, %1 \n"
508 " or %0, %2 \n"
509 " " __SC "%0, %1 \n"
510 " .set mips0 \n"
511 : "=&r" (temp), "+m" (*reg)
512 : "r" (val));
513 } while (unlikely(!temp));
514 }
515
516 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
517 unsigned long val)
518 {
519 unsigned long temp;
520 do {
521 __asm__ __volatile__(
522 " .set mips3 \n"
523 " " __LL "%0, %1 \n"
524 " and %0, %2 \n"
525 " " __SC "%0, %1 \n"
526 " .set mips0 \n"
527 : "=&r" (temp), "+m" (*reg)
528 : "r" (~val));
529 } while (unlikely(!temp));
530 }
531
532 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
533 unsigned long change,
534 unsigned long val)
535 {
536 unsigned long temp;
537 do {
538 __asm__ __volatile__(
539 " .set mips3 \n"
540 " " __LL "%0, %1 \n"
541 " and %0, %2 \n"
542 " or %0, %3 \n"
543 " " __SC "%0, %1 \n"
544 " .set mips0 \n"
545 : "=&r" (temp), "+m" (*reg)
546 : "r" (~change), "r" (val & change));
547 } while (unlikely(!temp));
548 }
549
550 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
551 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
552
553 /* Cause can be modified asynchronously from hardirq hrtimer callback */
554 #define kvm_set_c0_guest_cause(cop0, val) \
555 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
556 #define kvm_clear_c0_guest_cause(cop0, val) \
557 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
558 #define kvm_change_c0_guest_cause(cop0, change, val) \
559 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
560 change, val)
561
562 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
563 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
564 #define kvm_change_c0_guest_ebase(cop0, change, val) \
565 { \
566 kvm_clear_c0_guest_ebase(cop0, change); \
567 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
568 }
569
570
571 struct kvm_mips_callbacks {
572 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
573 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
574 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
575 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
576 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
577 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
578 int (*handle_syscall)(struct kvm_vcpu *vcpu);
579 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
580 int (*handle_break)(struct kvm_vcpu *vcpu);
581 int (*vm_init)(struct kvm *kvm);
582 int (*vcpu_init)(struct kvm_vcpu *vcpu);
583 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
584 gpa_t (*gva_to_gpa)(gva_t gva);
585 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
586 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
587 void (*queue_io_int)(struct kvm_vcpu *vcpu,
588 struct kvm_mips_interrupt *irq);
589 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
590 struct kvm_mips_interrupt *irq);
591 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
592 uint32_t cause);
593 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
594 uint32_t cause);
595 int (*get_one_reg)(struct kvm_vcpu *vcpu,
596 const struct kvm_one_reg *reg, s64 *v);
597 int (*set_one_reg)(struct kvm_vcpu *vcpu,
598 const struct kvm_one_reg *reg, s64 v);
599 };
600 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
601 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
602
603 /* Debug: dump vcpu state */
604 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
605
606 /* Trampoline ASM routine to start running in "Guest" context */
607 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
608
609 /* TLB handling */
610 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
611
612 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
613
614 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
615
616 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
617 struct kvm_vcpu *vcpu);
618
619 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
620 struct kvm_vcpu *vcpu);
621
622 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
623 struct kvm_mips_tlb *tlb,
624 unsigned long *hpa0,
625 unsigned long *hpa1);
626
627 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
628 uint32_t *opc,
629 struct kvm_run *run,
630 struct kvm_vcpu *vcpu);
631
632 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
633 uint32_t *opc,
634 struct kvm_run *run,
635 struct kvm_vcpu *vcpu);
636
637 extern void kvm_mips_dump_host_tlbs(void);
638 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
639 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
640 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
641 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
642
643 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
644 unsigned long entryhi);
645 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
646 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
647 unsigned long gva);
648 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
649 struct kvm_vcpu *vcpu);
650 extern void kvm_local_flush_tlb_all(void);
651 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
652 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
653 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
654
655 /* Emulation */
656 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
657 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
658
659 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
660 uint32_t *opc,
661 struct kvm_run *run,
662 struct kvm_vcpu *vcpu);
663
664 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
665 uint32_t *opc,
666 struct kvm_run *run,
667 struct kvm_vcpu *vcpu);
668
669 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
670 uint32_t *opc,
671 struct kvm_run *run,
672 struct kvm_vcpu *vcpu);
673
674 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
675 uint32_t *opc,
676 struct kvm_run *run,
677 struct kvm_vcpu *vcpu);
678
679 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
680 uint32_t *opc,
681 struct kvm_run *run,
682 struct kvm_vcpu *vcpu);
683
684 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
685 uint32_t *opc,
686 struct kvm_run *run,
687 struct kvm_vcpu *vcpu);
688
689 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
690 uint32_t *opc,
691 struct kvm_run *run,
692 struct kvm_vcpu *vcpu);
693
694 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
695 uint32_t *opc,
696 struct kvm_run *run,
697 struct kvm_vcpu *vcpu);
698
699 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
700 uint32_t *opc,
701 struct kvm_run *run,
702 struct kvm_vcpu *vcpu);
703
704 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
705 uint32_t *opc,
706 struct kvm_run *run,
707 struct kvm_vcpu *vcpu);
708
709 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
710 uint32_t *opc,
711 struct kvm_run *run,
712 struct kvm_vcpu *vcpu);
713
714 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
715 struct kvm_run *run);
716
717 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
718 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
719 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
720 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
721 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
722 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
723 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
724 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
725 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
726 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
727
728 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
729 uint32_t *opc,
730 struct kvm_run *run,
731 struct kvm_vcpu *vcpu);
732
733 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
734 uint32_t *opc,
735 uint32_t cause,
736 struct kvm_run *run,
737 struct kvm_vcpu *vcpu);
738 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
739 uint32_t *opc,
740 uint32_t cause,
741 struct kvm_run *run,
742 struct kvm_vcpu *vcpu);
743 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
744 uint32_t cause,
745 struct kvm_run *run,
746 struct kvm_vcpu *vcpu);
747 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
748 uint32_t cause,
749 struct kvm_run *run,
750 struct kvm_vcpu *vcpu);
751
752 /* Dynamic binary translation */
753 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
754 struct kvm_vcpu *vcpu);
755 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
756 struct kvm_vcpu *vcpu);
757 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
758 struct kvm_vcpu *vcpu);
759 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
760 struct kvm_vcpu *vcpu);
761
762 /* Misc */
763 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
764 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
765
766 static inline void kvm_arch_hardware_disable(void) {}
767 static inline void kvm_arch_hardware_unsetup(void) {}
768 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
769 static inline void kvm_arch_free_memslot(struct kvm *kvm,
770 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
771 static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
772 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
773 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
774 struct kvm_memory_slot *slot) {}
775 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
776 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
777
778 #endif /* __MIPS_KVM_HOST_H__ */
Linux kernel - Deliverables
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