2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
46 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
47 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
48 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
49 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
50 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
51 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
52 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
55 #define KVM_MAX_VCPUS 1
56 #define KVM_USER_MEM_SLOTS 8
57 /* memory slots that does not exposed to userspace */
58 #define KVM_PRIVATE_MEM_SLOTS 0
60 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64 /* Special address that contains the comm page, used for reducing # of traps */
65 #define KVM_GUEST_COMMPAGE_ADDR 0x0
67 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
68 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
70 #define KVM_GUEST_KUSEG 0x00000000UL
71 #define KVM_GUEST_KSEG0 0x40000000UL
72 #define KVM_GUEST_KSEG23 0x60000000UL
73 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
74 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
76 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
77 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
78 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
81 * Map an address to a certain kernel segment
83 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
84 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
85 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
87 #define KVM_INVALID_PAGE 0xdeadbeef
88 #define KVM_INVALID_INST 0xdeadbeef
89 #define KVM_INVALID_ADDR 0xdeadbeef
91 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
93 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
94 #define MS_TO_NS(x) (x * 1E6L)
97 #define CAUSEF_DC (_ULCAST_(1) << 27)
99 extern atomic_t kvm_mips_instance
;
100 extern pfn_t(*kvm_mips_gfn_to_pfn
) (struct kvm
*kvm
, gfn_t gfn
);
101 extern void (*kvm_mips_release_pfn_clean
) (pfn_t pfn
);
102 extern bool(*kvm_mips_is_error_pfn
) (pfn_t pfn
);
105 u32 remote_tlb_flush
;
108 struct kvm_vcpu_stat
{
113 u32 cop_unusable_exits
;
115 u32 tlbmiss_ld_exits
;
116 u32 tlbmiss_st_exits
;
117 u32 addrerr_st_exits
;
118 u32 addrerr_ld_exits
;
120 u32 resvd_inst_exits
;
121 u32 break_inst_exits
;
122 u32 flush_dcache_exits
;
126 enum kvm_mips_exit_types
{
141 MAX_KVM_MIPS_EXIT_TYPES
144 struct kvm_arch_memory_slot
{
148 /* Guest GVA->HPA page table */
149 unsigned long *guest_pmap
;
150 unsigned long guest_pmap_npages
;
152 /* Wired host TLB used for the commpage */
156 #define N_MIPS_COPROC_REGS 32
157 #define N_MIPS_COPROC_SEL 8
160 unsigned long reg
[N_MIPS_COPROC_REGS
][N_MIPS_COPROC_SEL
];
161 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
162 unsigned long stat
[N_MIPS_COPROC_REGS
][N_MIPS_COPROC_SEL
];
167 * Coprocessor 0 register names
169 #define MIPS_CP0_TLB_INDEX 0
170 #define MIPS_CP0_TLB_RANDOM 1
171 #define MIPS_CP0_TLB_LOW 2
172 #define MIPS_CP0_TLB_LO0 2
173 #define MIPS_CP0_TLB_LO1 3
174 #define MIPS_CP0_TLB_CONTEXT 4
175 #define MIPS_CP0_TLB_PG_MASK 5
176 #define MIPS_CP0_TLB_WIRED 6
177 #define MIPS_CP0_HWRENA 7
178 #define MIPS_CP0_BAD_VADDR 8
179 #define MIPS_CP0_COUNT 9
180 #define MIPS_CP0_TLB_HI 10
181 #define MIPS_CP0_COMPARE 11
182 #define MIPS_CP0_STATUS 12
183 #define MIPS_CP0_CAUSE 13
184 #define MIPS_CP0_EXC_PC 14
185 #define MIPS_CP0_PRID 15
186 #define MIPS_CP0_CONFIG 16
187 #define MIPS_CP0_LLADDR 17
188 #define MIPS_CP0_WATCH_LO 18
189 #define MIPS_CP0_WATCH_HI 19
190 #define MIPS_CP0_TLB_XCONTEXT 20
191 #define MIPS_CP0_ECC 26
192 #define MIPS_CP0_CACHE_ERR 27
193 #define MIPS_CP0_TAG_LO 28
194 #define MIPS_CP0_TAG_HI 29
195 #define MIPS_CP0_ERROR_PC 30
196 #define MIPS_CP0_DEBUG 23
197 #define MIPS_CP0_DEPC 24
198 #define MIPS_CP0_PERFCNT 25
199 #define MIPS_CP0_ERRCTL 26
200 #define MIPS_CP0_DATA_LO 28
201 #define MIPS_CP0_DATA_HI 29
202 #define MIPS_CP0_DESAVE 31
204 #define MIPS_CP0_CONFIG_SEL 0
205 #define MIPS_CP0_CONFIG1_SEL 1
206 #define MIPS_CP0_CONFIG2_SEL 2
207 #define MIPS_CP0_CONFIG3_SEL 3
209 /* Config0 register bits */
223 /* Config1 register bits */
240 /* Config2 Register bits */
251 /* Config3 Register bits */
253 #define CP0C3_ISA_ON_EXC 16
254 #define CP0C3_ULRI 13
255 #define CP0C3_DSPP 10
264 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
265 #define MIPS_CONFIG0 \
266 ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
268 /* Have config2, no coprocessor2 attached, no MDMX support attached,
269 no performance counters, watch registers present,
270 no code compression, EJTAG present, no FPU, no watch registers */
271 #define MIPS_CONFIG1 \
273 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
274 (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
277 /* Have config3, no tertiary/secondary caches implemented */
278 #define MIPS_CONFIG2 \
281 /* No config4, no DSP ASE, no large physaddr (PABITS),
282 no external interrupt controller, no vectored interrupts,
283 no 1kb pages, no SmartMIPS ASE, no trace logic */
284 #define MIPS_CONFIG3 \
285 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
286 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
287 (0 << CP0C3_SM) | (0 << CP0C3_TL))
289 /* MMU types, the first four entries have the same layout as the
291 enum mips_mmu_types
{
304 #define T_INT 0 /* Interrupt pending */
305 #define T_TLB_MOD 1 /* TLB modified fault */
306 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
307 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
308 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
309 #define T_ADDR_ERR_ST 5 /* Address error on a store */
310 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
311 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
312 #define T_SYSCALL 8 /* System call */
313 #define T_BREAK 9 /* Breakpoint */
314 #define T_RES_INST 10 /* Reserved instruction exception */
315 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
316 #define T_OVFLOW 12 /* Arithmetic overflow */
319 * Trap definitions added for r4000 port.
321 #define T_TRAP 13 /* Trap instruction */
322 #define T_VCEI 14 /* Virtual coherency exception */
323 #define T_FPE 15 /* Floating point exception */
324 #define T_WATCH 23 /* Watch address reference */
325 #define T_VCED 31 /* Virtual coherency data */
328 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
329 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
331 #define RESUME_GUEST 0
332 #define RESUME_GUEST_DR RESUME_FLAG_DR
333 #define RESUME_HOST RESUME_FLAG_HOST
335 enum emulation_result
{
336 EMULATE_DONE
, /* no further processing */
337 EMULATE_DO_MMIO
, /* kvm_run filled with MMIO request */
338 EMULATE_FAIL
, /* can't emulate this instruction */
339 EMULATE_WAIT
, /* WAIT instruction */
343 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
344 #define MIPS3_PG_V 0x00000002 /* Valid */
345 #define MIPS3_PG_NV 0x00000000
346 #define MIPS3_PG_D 0x00000004 /* Dirty */
348 #define mips3_paddr_to_tlbpfn(x) \
349 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
350 #define mips3_tlbpfn_to_paddr(x) \
351 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
353 #define MIPS3_PG_SHIFT 6
354 #define MIPS3_PG_FRAME 0x3fffffc0
356 #define VPN2_MASK 0xffffe000
357 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
358 ((x).tlb_lo1 & MIPS3_PG_G))
359 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
360 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
361 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
362 ? ((x).tlb_lo1 & MIPS3_PG_V) \
363 : ((x).tlb_lo0 & MIPS3_PG_V))
364 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
365 ((y) & VPN2_MASK & ~(x).tlb_mask))
366 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
367 TLB_ASID(x) == ((y) & ASID_MASK))
369 struct kvm_mips_tlb
{
376 #define KVM_MIPS_GUEST_TLB_SIZE 64
377 struct kvm_vcpu_arch
{
378 void *host_ebase
, *guest_ebase
;
379 unsigned long host_stack
;
380 unsigned long host_gp
;
382 /* Host CP0 registers used when handling exits from guest */
383 unsigned long host_cp0_badvaddr
;
384 unsigned long host_cp0_cause
;
385 unsigned long host_cp0_epc
;
386 unsigned long host_cp0_entryhi
;
390 unsigned long gprs
[32];
396 struct mips_fpu_struct fpu
;
399 struct mips_coproc
*cop0
;
401 /* Host KSEG0 address of the EI/DI offset */
402 void *kseg0_commpage
;
404 u32 io_gpr
; /* GPR used as IO source/target */
406 struct hrtimer comparecount_timer
;
407 /* Count timer control KVM register */
409 /* Count bias from the raw time */
411 /* Frequency of timer in Hz */
413 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
416 ktime_t count_resume
;
417 /* Period of timer tick in ns */
420 /* Bitmask of exceptions that are pending */
421 unsigned long pending_exceptions
;
423 /* Bitmask of pending exceptions to be cleared */
424 unsigned long pending_exceptions_clr
;
426 unsigned long pending_load_cause
;
428 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
429 unsigned long preempt_entryhi
;
431 /* S/W Based TLB for guest */
432 struct kvm_mips_tlb guest_tlb
[KVM_MIPS_GUEST_TLB_SIZE
];
434 /* Cached guest kernel/user ASIDs */
435 uint32_t guest_user_asid
[NR_CPUS
];
436 uint32_t guest_kernel_asid
[NR_CPUS
];
437 struct mm_struct guest_kernel_mm
, guest_user_mm
;
446 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
447 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
448 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
449 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
450 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
451 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
452 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
453 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
454 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
455 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
456 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
457 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
458 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
459 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
460 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
461 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
462 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
463 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
464 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
465 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
466 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
467 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
468 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
469 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
470 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
471 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
472 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
473 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
474 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
475 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
476 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
477 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
478 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
479 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
480 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
481 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
482 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
483 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
484 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
485 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
486 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
487 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
488 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
489 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
490 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
491 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
494 * Some of the guest registers may be modified asynchronously (e.g. from a
495 * hrtimer callback in hard irq context) and therefore need stronger atomicity
496 * guarantees than other registers.
499 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg
,
504 __asm__
__volatile__(
510 : "=&r" (temp
), "+m" (*reg
)
512 } while (unlikely(!temp
));
515 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg
,
520 __asm__
__volatile__(
526 : "=&r" (temp
), "+m" (*reg
)
528 } while (unlikely(!temp
));
531 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg
,
532 unsigned long change
,
537 __asm__
__volatile__(
544 : "=&r" (temp
), "+m" (*reg
)
545 : "r" (~change
), "r" (val
& change
));
546 } while (unlikely(!temp
));
549 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
550 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
552 /* Cause can be modified asynchronously from hardirq hrtimer callback */
553 #define kvm_set_c0_guest_cause(cop0, val) \
554 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
555 #define kvm_clear_c0_guest_cause(cop0, val) \
556 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
557 #define kvm_change_c0_guest_cause(cop0, change, val) \
558 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
561 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
562 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
563 #define kvm_change_c0_guest_ebase(cop0, change, val) \
565 kvm_clear_c0_guest_ebase(cop0, change); \
566 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
570 struct kvm_mips_callbacks
{
571 int (*handle_cop_unusable
)(struct kvm_vcpu
*vcpu
);
572 int (*handle_tlb_mod
)(struct kvm_vcpu
*vcpu
);
573 int (*handle_tlb_ld_miss
)(struct kvm_vcpu
*vcpu
);
574 int (*handle_tlb_st_miss
)(struct kvm_vcpu
*vcpu
);
575 int (*handle_addr_err_st
)(struct kvm_vcpu
*vcpu
);
576 int (*handle_addr_err_ld
)(struct kvm_vcpu
*vcpu
);
577 int (*handle_syscall
)(struct kvm_vcpu
*vcpu
);
578 int (*handle_res_inst
)(struct kvm_vcpu
*vcpu
);
579 int (*handle_break
)(struct kvm_vcpu
*vcpu
);
580 int (*vm_init
)(struct kvm
*kvm
);
581 int (*vcpu_init
)(struct kvm_vcpu
*vcpu
);
582 int (*vcpu_setup
)(struct kvm_vcpu
*vcpu
);
583 gpa_t (*gva_to_gpa
)(gva_t gva
);
584 void (*queue_timer_int
)(struct kvm_vcpu
*vcpu
);
585 void (*dequeue_timer_int
)(struct kvm_vcpu
*vcpu
);
586 void (*queue_io_int
)(struct kvm_vcpu
*vcpu
,
587 struct kvm_mips_interrupt
*irq
);
588 void (*dequeue_io_int
)(struct kvm_vcpu
*vcpu
,
589 struct kvm_mips_interrupt
*irq
);
590 int (*irq_deliver
)(struct kvm_vcpu
*vcpu
, unsigned int priority
,
592 int (*irq_clear
)(struct kvm_vcpu
*vcpu
, unsigned int priority
,
594 int (*get_one_reg
)(struct kvm_vcpu
*vcpu
,
595 const struct kvm_one_reg
*reg
, s64
*v
);
596 int (*set_one_reg
)(struct kvm_vcpu
*vcpu
,
597 const struct kvm_one_reg
*reg
, s64 v
);
599 extern struct kvm_mips_callbacks
*kvm_mips_callbacks
;
600 int kvm_mips_emulation_init(struct kvm_mips_callbacks
**install_callbacks
);
602 /* Debug: dump vcpu state */
603 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu
*vcpu
);
605 /* Trampoline ASM routine to start running in "Guest" context */
606 extern int __kvm_mips_vcpu_run(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
);
609 uint32_t kvm_get_kernel_asid(struct kvm_vcpu
*vcpu
);
611 uint32_t kvm_get_user_asid(struct kvm_vcpu
*vcpu
);
613 uint32_t kvm_get_commpage_asid (struct kvm_vcpu
*vcpu
);
615 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr
,
616 struct kvm_vcpu
*vcpu
);
618 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr
,
619 struct kvm_vcpu
*vcpu
);
621 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu
*vcpu
,
622 struct kvm_mips_tlb
*tlb
,
624 unsigned long *hpa1
);
626 extern enum emulation_result
kvm_mips_handle_tlbmiss(unsigned long cause
,
629 struct kvm_vcpu
*vcpu
);
631 extern enum emulation_result
kvm_mips_handle_tlbmod(unsigned long cause
,
634 struct kvm_vcpu
*vcpu
);
636 extern void kvm_mips_dump_host_tlbs(void);
637 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu
*vcpu
);
638 extern void kvm_mips_flush_host_tlb(int skip_kseg0
);
639 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu
*vcpu
, unsigned long entryhi
);
640 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu
*vcpu
, int index
);
642 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu
*vcpu
,
643 unsigned long entryhi
);
644 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu
*vcpu
, unsigned long vaddr
);
645 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu
*vcpu
,
647 extern void kvm_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
,
648 struct kvm_vcpu
*vcpu
);
649 extern void kvm_local_flush_tlb_all(void);
650 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu
*vcpu
);
651 extern void kvm_mips_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
);
652 extern void kvm_mips_vcpu_put(struct kvm_vcpu
*vcpu
);
655 uint32_t kvm_get_inst(uint32_t *opc
, struct kvm_vcpu
*vcpu
);
656 enum emulation_result
update_pc(struct kvm_vcpu
*vcpu
, uint32_t cause
);
658 extern enum emulation_result
kvm_mips_emulate_inst(unsigned long cause
,
661 struct kvm_vcpu
*vcpu
);
663 extern enum emulation_result
kvm_mips_emulate_syscall(unsigned long cause
,
666 struct kvm_vcpu
*vcpu
);
668 extern enum emulation_result
kvm_mips_emulate_tlbmiss_ld(unsigned long cause
,
671 struct kvm_vcpu
*vcpu
);
673 extern enum emulation_result
kvm_mips_emulate_tlbinv_ld(unsigned long cause
,
676 struct kvm_vcpu
*vcpu
);
678 extern enum emulation_result
kvm_mips_emulate_tlbmiss_st(unsigned long cause
,
681 struct kvm_vcpu
*vcpu
);
683 extern enum emulation_result
kvm_mips_emulate_tlbinv_st(unsigned long cause
,
686 struct kvm_vcpu
*vcpu
);
688 extern enum emulation_result
kvm_mips_emulate_tlbmod(unsigned long cause
,
691 struct kvm_vcpu
*vcpu
);
693 extern enum emulation_result
kvm_mips_emulate_fpu_exc(unsigned long cause
,
696 struct kvm_vcpu
*vcpu
);
698 extern enum emulation_result
kvm_mips_handle_ri(unsigned long cause
,
701 struct kvm_vcpu
*vcpu
);
703 extern enum emulation_result
kvm_mips_emulate_ri_exc(unsigned long cause
,
706 struct kvm_vcpu
*vcpu
);
708 extern enum emulation_result
kvm_mips_emulate_bp_exc(unsigned long cause
,
711 struct kvm_vcpu
*vcpu
);
713 extern enum emulation_result
kvm_mips_complete_mmio_load(struct kvm_vcpu
*vcpu
,
714 struct kvm_run
*run
);
716 uint32_t kvm_mips_read_count(struct kvm_vcpu
*vcpu
);
717 void kvm_mips_write_count(struct kvm_vcpu
*vcpu
, uint32_t count
);
718 void kvm_mips_write_compare(struct kvm_vcpu
*vcpu
, uint32_t compare
);
719 void kvm_mips_init_count(struct kvm_vcpu
*vcpu
);
720 int kvm_mips_set_count_ctl(struct kvm_vcpu
*vcpu
, s64 count_ctl
);
721 int kvm_mips_set_count_resume(struct kvm_vcpu
*vcpu
, s64 count_resume
);
722 int kvm_mips_set_count_hz(struct kvm_vcpu
*vcpu
, s64 count_hz
);
723 void kvm_mips_count_enable_cause(struct kvm_vcpu
*vcpu
);
724 void kvm_mips_count_disable_cause(struct kvm_vcpu
*vcpu
);
725 enum hrtimer_restart
kvm_mips_count_timeout(struct kvm_vcpu
*vcpu
);
727 enum emulation_result
kvm_mips_check_privilege(unsigned long cause
,
730 struct kvm_vcpu
*vcpu
);
732 enum emulation_result
kvm_mips_emulate_cache(uint32_t inst
,
736 struct kvm_vcpu
*vcpu
);
737 enum emulation_result
kvm_mips_emulate_CP0(uint32_t inst
,
741 struct kvm_vcpu
*vcpu
);
742 enum emulation_result
kvm_mips_emulate_store(uint32_t inst
,
745 struct kvm_vcpu
*vcpu
);
746 enum emulation_result
kvm_mips_emulate_load(uint32_t inst
,
749 struct kvm_vcpu
*vcpu
);
751 /* Dynamic binary translation */
752 extern int kvm_mips_trans_cache_index(uint32_t inst
, uint32_t *opc
,
753 struct kvm_vcpu
*vcpu
);
754 extern int kvm_mips_trans_cache_va(uint32_t inst
, uint32_t *opc
,
755 struct kvm_vcpu
*vcpu
);
756 extern int kvm_mips_trans_mfc0(uint32_t inst
, uint32_t *opc
,
757 struct kvm_vcpu
*vcpu
);
758 extern int kvm_mips_trans_mtc0(uint32_t inst
, uint32_t *opc
,
759 struct kvm_vcpu
*vcpu
);
762 extern void kvm_mips_dump_stats(struct kvm_vcpu
*vcpu
);
763 extern unsigned long kvm_mips_get_ramsize(struct kvm
*kvm
);
765 static inline void kvm_arch_hardware_disable(void) {}
766 static inline void kvm_arch_hardware_unsetup(void) {}
767 static inline void kvm_arch_sync_events(struct kvm
*kvm
) {}
768 static inline void kvm_arch_free_memslot(struct kvm
*kvm
,
769 struct kvm_memory_slot
*free
, struct kvm_memory_slot
*dont
) {}
770 static inline void kvm_arch_memslots_updated(struct kvm
*kvm
) {}
771 static inline void kvm_arch_flush_shadow_all(struct kvm
*kvm
) {}
772 static inline void kvm_arch_flush_shadow_memslot(struct kvm
*kvm
,
773 struct kvm_memory_slot
*slot
) {}
774 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu
*vcpu
) {}
775 static inline void kvm_arch_sched_in(struct kvm_vcpu
*vcpu
, int cpu
) {}
777 #endif /* __MIPS_KVM_HOST_H__ */