arch/mips/include/asm/mach-pb1x00/pb1200.h

   1 /*
   2  * AMD Alchemy Pb1200 Referrence Board
   3  * Board Registers defines.
   4  *
   5  * ########################################################################
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * ########################################################################
  21  *
  22  *
  23  */
  24 #ifndef __ASM_PB1200_H
  25 #define __ASM_PB1200_H
  26
  27 #include <linux/types.h>
  28 #include <asm/mach-au1x00/au1000.h>
  29 #include <asm/mach-au1x00/au1xxx_psc.h>
  30
  31 #define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
  32 #define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
  33 #define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
  34 #define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
  35
  36 /*
  37  * SPI and SMB are muxed on the Pb1200 board.
  38  * Refer to board documentation.
  39  */
  40 #define SPI_PSC_BASE            PSC0_BASE_ADDR
  41 #define SMBUS_PSC_BASE          PSC0_BASE_ADDR
  42 /*
  43  * AC97 and I2S are muxed on the Pb1200 board.
  44  * Refer to board documentation.
  45  */
  46 #define AC97_PSC_BASE       PSC1_BASE_ADDR
  47 #define I2S_PSC_BASE    PSC1_BASE_ADDR
  48
  49
  50 #define BCSR_SYSTEM_VDDI        0x001F
  51 #define BCSR_SYSTEM_POWEROFF    0x4000
  52 #define BCSR_SYSTEM_RESET       0x8000
  53
  54 /* Bit positions for the different interrupt sources */
  55 #define BCSR_INT_IDE            0x0001
  56 #define BCSR_INT_ETH            0x0002
  57 #define BCSR_INT_PC0            0x0004
  58 #define BCSR_INT_PC0STSCHG      0x0008
  59 #define BCSR_INT_PC1            0x0010
  60 #define BCSR_INT_PC1STSCHG      0x0020
  61 #define BCSR_INT_DC             0x0040
  62 #define BCSR_INT_FLASHBUSY      0x0080
  63 #define BCSR_INT_PC0INSERT      0x0100
  64 #define BCSR_INT_PC0EJECT       0x0200
  65 #define BCSR_INT_PC1INSERT      0x0400
  66 #define BCSR_INT_PC1EJECT       0x0800
  67 #define BCSR_INT_SD0INSERT      0x1000
  68 #define BCSR_INT_SD0EJECT       0x2000
  69 #define BCSR_INT_SD1INSERT      0x4000
  70 #define BCSR_INT_SD1EJECT       0x8000
  71
  72 #define SMC91C111_PHYS_ADDR     0x0D000300
  73 #define SMC91C111_INT           PB1200_ETH_INT
  74
  75 #define IDE_PHYS_ADDR           0x0C800000
  76 #define IDE_REG_SHIFT           5
  77 #define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
  78 #define IDE_INT                 PB1200_IDE_INT
  79 #define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
  80 #define IDE_RQSIZE              128
  81
  82 #define NAND_PHYS_ADDR  0x1C000000
  83
  84 /*
  85  * Timing values as described in databook, * ns value stripped of
  86  * lower 2 bits.
  87  * These defines are here rather than an Au1200 generic file because
  88  * the parts chosen on another board may be different and may require
  89  * different timings.
  90  */
  91 #define NAND_T_H                (18 >> 2)
  92 #define NAND_T_PUL              (30 >> 2)
  93 #define NAND_T_SU               (30 >> 2)
  94 #define NAND_T_WH               (30 >> 2)
  95
  96 /* Bitfield shift amounts */
  97 #define NAND_T_H_SHIFT          0
  98 #define NAND_T_PUL_SHIFT        4
  99 #define NAND_T_SU_SHIFT         8
 100 #define NAND_T_WH_SHIFT         12
 101
 102 #define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
 103                          ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
 104                          ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
 105                          ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
 106
 107 /*
 108  * External Interrupts for Pb1200 as of 8/6/2004.
 109  * Bit positions in the CPLD registers can be calculated by taking
 110  * the interrupt define and subtracting the PB1200_INT_BEGIN value.
 111  *
 112  *   Example: IDE bis pos is  = 64 - 64
 113  *            ETH bit pos is  = 65 - 64
 114  */
 115 enum external_pb1200_ints {
 116         PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
 117
 118         PB1200_IDE_INT          = PB1200_INT_BEGIN,
 119         PB1200_ETH_INT,
 120         PB1200_PC0_INT,
 121         PB1200_PC0_STSCHG_INT,
 122         PB1200_PC1_INT,
 123         PB1200_PC1_STSCHG_INT,
 124         PB1200_DC_INT,
 125         PB1200_FLASHBUSY_INT,
 126         PB1200_PC0_INSERT_INT,
 127         PB1200_PC0_EJECT_INT,
 128         PB1200_PC1_INSERT_INT,
 129         PB1200_PC1_EJECT_INT,
 130         PB1200_SD0_INSERT_INT,
 131         PB1200_SD0_EJECT_INT,
 132         PB1200_SD1_INSERT_INT,
 133         PB1200_SD1_EJECT_INT,
 134
 135         PB1200_INT_END          = PB1200_INT_BEGIN + 15
 136 };
 137
 138 /* NAND chip select */
 139 #define NAND_CS 1
 140
 141 #endif /* __ASM_PB1200_H */