arch/mips/include/asm/octeon/cvmx-npi-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_NPI_DEFS_H__
  29 #define __CVMX_NPI_DEFS_H__
  30
  31 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
  32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
  33 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
  34 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
  35 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
  36 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
  37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
  38 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
  39 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
  40 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
  41 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
  42 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
  43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
  44 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
  45 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
  46 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
  47 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
  48 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
  49 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
  50 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
  51 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
  52 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
  53 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
  54 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
  55 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
  56 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
  57 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
  58 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
  59 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
  60 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
  61 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
  62 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
  63 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
  64 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
  65 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
  66 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
  67 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
  68 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
  69 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
  70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
  71 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
  72 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
  73 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
  74 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
  75 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
  76 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
  77 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
  78 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
  79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
  80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
  81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
  82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
  83 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
  84 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
  85 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
  86 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
  87 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
  88 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
  89 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
  90 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
  91 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
  92 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
  93 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
  94 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
  95 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
  96 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
  97 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
  98 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
  99 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
 100 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
 101 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
 102 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
 103 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
 104 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
 105 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
 106 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
 107 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
 108 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
 109 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
 110 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
 111 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
 112 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
 113 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
 114 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
 115 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
 116 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
 117 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
 118 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
 119 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
 120 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
 121 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
 122 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
 123 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
 124 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
 125 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
 126 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
 127 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
 128 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
 129 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
 130 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
 131 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
 132 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
 133 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
 134 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
 135 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
 136 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
 137 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
 138 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
 139 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
 140 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
 141 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
 142 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
 143 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
 144 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
 145 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
 146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
 147 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
 148 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
 149 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
 150 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
 151
 152 union cvmx_npi_base_addr_inputx {
 153         uint64_t u64;
 154         struct cvmx_npi_base_addr_inputx_s {
 155 #ifdef __BIG_ENDIAN_BITFIELD
 156                 uint64_t baddr:61;
 157                 uint64_t reserved_0_2:3;
 158 #else
 159                 uint64_t reserved_0_2:3;
 160                 uint64_t baddr:61;
 161 #endif
 162         } s;
 163         struct cvmx_npi_base_addr_inputx_s cn30xx;
 164         struct cvmx_npi_base_addr_inputx_s cn31xx;
 165         struct cvmx_npi_base_addr_inputx_s cn38xx;
 166         struct cvmx_npi_base_addr_inputx_s cn38xxp2;
 167         struct cvmx_npi_base_addr_inputx_s cn50xx;
 168         struct cvmx_npi_base_addr_inputx_s cn58xx;
 169         struct cvmx_npi_base_addr_inputx_s cn58xxp1;
 170 };
 171
 172 union cvmx_npi_base_addr_outputx {
 173         uint64_t u64;
 174         struct cvmx_npi_base_addr_outputx_s {
 175 #ifdef __BIG_ENDIAN_BITFIELD
 176                 uint64_t baddr:61;
 177                 uint64_t reserved_0_2:3;
 178 #else
 179                 uint64_t reserved_0_2:3;
 180                 uint64_t baddr:61;
 181 #endif
 182         } s;
 183         struct cvmx_npi_base_addr_outputx_s cn30xx;
 184         struct cvmx_npi_base_addr_outputx_s cn31xx;
 185         struct cvmx_npi_base_addr_outputx_s cn38xx;
 186         struct cvmx_npi_base_addr_outputx_s cn38xxp2;
 187         struct cvmx_npi_base_addr_outputx_s cn50xx;
 188         struct cvmx_npi_base_addr_outputx_s cn58xx;
 189         struct cvmx_npi_base_addr_outputx_s cn58xxp1;
 190 };
 191
 192 union cvmx_npi_bist_status {
 193         uint64_t u64;
 194         struct cvmx_npi_bist_status_s {
 195 #ifdef __BIG_ENDIAN_BITFIELD
 196                 uint64_t reserved_20_63:44;
 197                 uint64_t csr_bs:1;
 198                 uint64_t dif_bs:1;
 199                 uint64_t rdp_bs:1;
 200                 uint64_t pcnc_bs:1;
 201                 uint64_t pcn_bs:1;
 202                 uint64_t rdn_bs:1;
 203                 uint64_t pcac_bs:1;
 204                 uint64_t pcad_bs:1;
 205                 uint64_t rdnl_bs:1;
 206                 uint64_t pgf_bs:1;
 207                 uint64_t pig_bs:1;
 208                 uint64_t pof0_bs:1;
 209                 uint64_t pof1_bs:1;
 210                 uint64_t pof2_bs:1;
 211                 uint64_t pof3_bs:1;
 212                 uint64_t pos_bs:1;
 213                 uint64_t nus_bs:1;
 214                 uint64_t dob_bs:1;
 215                 uint64_t pdf_bs:1;
 216                 uint64_t dpi_bs:1;
 217 #else
 218                 uint64_t dpi_bs:1;
 219                 uint64_t pdf_bs:1;
 220                 uint64_t dob_bs:1;
 221                 uint64_t nus_bs:1;
 222                 uint64_t pos_bs:1;
 223                 uint64_t pof3_bs:1;
 224                 uint64_t pof2_bs:1;
 225                 uint64_t pof1_bs:1;
 226                 uint64_t pof0_bs:1;
 227                 uint64_t pig_bs:1;
 228                 uint64_t pgf_bs:1;
 229                 uint64_t rdnl_bs:1;
 230                 uint64_t pcad_bs:1;
 231                 uint64_t pcac_bs:1;
 232                 uint64_t rdn_bs:1;
 233                 uint64_t pcn_bs:1;
 234                 uint64_t pcnc_bs:1;
 235                 uint64_t rdp_bs:1;
 236                 uint64_t dif_bs:1;
 237                 uint64_t csr_bs:1;
 238                 uint64_t reserved_20_63:44;
 239 #endif
 240         } s;
 241         struct cvmx_npi_bist_status_cn30xx {
 242 #ifdef __BIG_ENDIAN_BITFIELD
 243                 uint64_t reserved_20_63:44;
 244                 uint64_t csr_bs:1;
 245                 uint64_t dif_bs:1;
 246                 uint64_t rdp_bs:1;
 247                 uint64_t pcnc_bs:1;
 248                 uint64_t pcn_bs:1;
 249                 uint64_t rdn_bs:1;
 250                 uint64_t pcac_bs:1;
 251                 uint64_t pcad_bs:1;
 252                 uint64_t rdnl_bs:1;
 253                 uint64_t pgf_bs:1;
 254                 uint64_t pig_bs:1;
 255                 uint64_t pof0_bs:1;
 256                 uint64_t reserved_5_7:3;
 257                 uint64_t pos_bs:1;
 258                 uint64_t nus_bs:1;
 259                 uint64_t dob_bs:1;
 260                 uint64_t pdf_bs:1;
 261                 uint64_t dpi_bs:1;
 262 #else
 263                 uint64_t dpi_bs:1;
 264                 uint64_t pdf_bs:1;
 265                 uint64_t dob_bs:1;
 266                 uint64_t nus_bs:1;
 267                 uint64_t pos_bs:1;
 268                 uint64_t reserved_5_7:3;
 269                 uint64_t pof0_bs:1;
 270                 uint64_t pig_bs:1;
 271                 uint64_t pgf_bs:1;
 272                 uint64_t rdnl_bs:1;
 273                 uint64_t pcad_bs:1;
 274                 uint64_t pcac_bs:1;
 275                 uint64_t rdn_bs:1;
 276                 uint64_t pcn_bs:1;
 277                 uint64_t pcnc_bs:1;
 278                 uint64_t rdp_bs:1;
 279                 uint64_t dif_bs:1;
 280                 uint64_t csr_bs:1;
 281                 uint64_t reserved_20_63:44;
 282 #endif
 283         } cn30xx;
 284         struct cvmx_npi_bist_status_s cn31xx;
 285         struct cvmx_npi_bist_status_s cn38xx;
 286         struct cvmx_npi_bist_status_s cn38xxp2;
 287         struct cvmx_npi_bist_status_cn50xx {
 288 #ifdef __BIG_ENDIAN_BITFIELD
 289                 uint64_t reserved_20_63:44;
 290                 uint64_t csr_bs:1;
 291                 uint64_t dif_bs:1;
 292                 uint64_t rdp_bs:1;
 293                 uint64_t pcnc_bs:1;
 294                 uint64_t pcn_bs:1;
 295                 uint64_t rdn_bs:1;
 296                 uint64_t pcac_bs:1;
 297                 uint64_t pcad_bs:1;
 298                 uint64_t rdnl_bs:1;
 299                 uint64_t pgf_bs:1;
 300                 uint64_t pig_bs:1;
 301                 uint64_t pof0_bs:1;
 302                 uint64_t pof1_bs:1;
 303                 uint64_t reserved_5_6:2;
 304                 uint64_t pos_bs:1;
 305                 uint64_t nus_bs:1;
 306                 uint64_t dob_bs:1;
 307                 uint64_t pdf_bs:1;
 308                 uint64_t dpi_bs:1;
 309 #else
 310                 uint64_t dpi_bs:1;
 311                 uint64_t pdf_bs:1;
 312                 uint64_t dob_bs:1;
 313                 uint64_t nus_bs:1;
 314                 uint64_t pos_bs:1;
 315                 uint64_t reserved_5_6:2;
 316                 uint64_t pof1_bs:1;
 317                 uint64_t pof0_bs:1;
 318                 uint64_t pig_bs:1;
 319                 uint64_t pgf_bs:1;
 320                 uint64_t rdnl_bs:1;
 321                 uint64_t pcad_bs:1;
 322                 uint64_t pcac_bs:1;
 323                 uint64_t rdn_bs:1;
 324                 uint64_t pcn_bs:1;
 325                 uint64_t pcnc_bs:1;
 326                 uint64_t rdp_bs:1;
 327                 uint64_t dif_bs:1;
 328                 uint64_t csr_bs:1;
 329                 uint64_t reserved_20_63:44;
 330 #endif
 331         } cn50xx;
 332         struct cvmx_npi_bist_status_s cn58xx;
 333         struct cvmx_npi_bist_status_s cn58xxp1;
 334 };
 335
 336 union cvmx_npi_buff_size_outputx {
 337         uint64_t u64;
 338         struct cvmx_npi_buff_size_outputx_s {
 339 #ifdef __BIG_ENDIAN_BITFIELD
 340                 uint64_t reserved_23_63:41;
 341                 uint64_t isize:7;
 342                 uint64_t bsize:16;
 343 #else
 344                 uint64_t bsize:16;
 345                 uint64_t isize:7;
 346                 uint64_t reserved_23_63:41;
 347 #endif
 348         } s;
 349         struct cvmx_npi_buff_size_outputx_s cn30xx;
 350         struct cvmx_npi_buff_size_outputx_s cn31xx;
 351         struct cvmx_npi_buff_size_outputx_s cn38xx;
 352         struct cvmx_npi_buff_size_outputx_s cn38xxp2;
 353         struct cvmx_npi_buff_size_outputx_s cn50xx;
 354         struct cvmx_npi_buff_size_outputx_s cn58xx;
 355         struct cvmx_npi_buff_size_outputx_s cn58xxp1;
 356 };
 357
 358 union cvmx_npi_comp_ctl {
 359         uint64_t u64;
 360         struct cvmx_npi_comp_ctl_s {
 361 #ifdef __BIG_ENDIAN_BITFIELD
 362                 uint64_t reserved_10_63:54;
 363                 uint64_t pctl:5;
 364                 uint64_t nctl:5;
 365 #else
 366                 uint64_t nctl:5;
 367                 uint64_t pctl:5;
 368                 uint64_t reserved_10_63:54;
 369 #endif
 370         } s;
 371         struct cvmx_npi_comp_ctl_s cn50xx;
 372         struct cvmx_npi_comp_ctl_s cn58xx;
 373         struct cvmx_npi_comp_ctl_s cn58xxp1;
 374 };
 375
 376 union cvmx_npi_ctl_status {
 377         uint64_t u64;
 378         struct cvmx_npi_ctl_status_s {
 379 #ifdef __BIG_ENDIAN_BITFIELD
 380                 uint64_t reserved_63_63:1;
 381                 uint64_t chip_rev:8;
 382                 uint64_t dis_pniw:1;
 383                 uint64_t out3_enb:1;
 384                 uint64_t out2_enb:1;
 385                 uint64_t out1_enb:1;
 386                 uint64_t out0_enb:1;
 387                 uint64_t ins3_enb:1;
 388                 uint64_t ins2_enb:1;
 389                 uint64_t ins1_enb:1;
 390                 uint64_t ins0_enb:1;
 391                 uint64_t ins3_64b:1;
 392                 uint64_t ins2_64b:1;
 393                 uint64_t ins1_64b:1;
 394                 uint64_t ins0_64b:1;
 395                 uint64_t pci_wdis:1;
 396                 uint64_t wait_com:1;
 397                 uint64_t reserved_37_39:3;
 398                 uint64_t max_word:5;
 399                 uint64_t reserved_10_31:22;
 400                 uint64_t timer:10;
 401 #else
 402                 uint64_t timer:10;
 403                 uint64_t reserved_10_31:22;
 404                 uint64_t max_word:5;
 405                 uint64_t reserved_37_39:3;
 406                 uint64_t wait_com:1;
 407                 uint64_t pci_wdis:1;
 408                 uint64_t ins0_64b:1;
 409                 uint64_t ins1_64b:1;
 410                 uint64_t ins2_64b:1;
 411                 uint64_t ins3_64b:1;
 412                 uint64_t ins0_enb:1;
 413                 uint64_t ins1_enb:1;
 414                 uint64_t ins2_enb:1;
 415                 uint64_t ins3_enb:1;
 416                 uint64_t out0_enb:1;
 417                 uint64_t out1_enb:1;
 418                 uint64_t out2_enb:1;
 419                 uint64_t out3_enb:1;
 420                 uint64_t dis_pniw:1;
 421                 uint64_t chip_rev:8;
 422                 uint64_t reserved_63_63:1;
 423 #endif
 424         } s;
 425         struct cvmx_npi_ctl_status_cn30xx {
 426 #ifdef __BIG_ENDIAN_BITFIELD
 427                 uint64_t reserved_63_63:1;
 428                 uint64_t chip_rev:8;
 429                 uint64_t dis_pniw:1;
 430                 uint64_t reserved_51_53:3;
 431                 uint64_t out0_enb:1;
 432                 uint64_t reserved_47_49:3;
 433                 uint64_t ins0_enb:1;
 434                 uint64_t reserved_43_45:3;
 435                 uint64_t ins0_64b:1;
 436                 uint64_t pci_wdis:1;
 437                 uint64_t wait_com:1;
 438                 uint64_t reserved_37_39:3;
 439                 uint64_t max_word:5;
 440                 uint64_t reserved_10_31:22;
 441                 uint64_t timer:10;
 442 #else
 443                 uint64_t timer:10;
 444                 uint64_t reserved_10_31:22;
 445                 uint64_t max_word:5;
 446                 uint64_t reserved_37_39:3;
 447                 uint64_t wait_com:1;
 448                 uint64_t pci_wdis:1;
 449                 uint64_t ins0_64b:1;
 450                 uint64_t reserved_43_45:3;
 451                 uint64_t ins0_enb:1;
 452                 uint64_t reserved_47_49:3;
 453                 uint64_t out0_enb:1;
 454                 uint64_t reserved_51_53:3;
 455                 uint64_t dis_pniw:1;
 456                 uint64_t chip_rev:8;
 457                 uint64_t reserved_63_63:1;
 458 #endif
 459         } cn30xx;
 460         struct cvmx_npi_ctl_status_cn31xx {
 461 #ifdef __BIG_ENDIAN_BITFIELD
 462                 uint64_t reserved_63_63:1;
 463                 uint64_t chip_rev:8;
 464                 uint64_t dis_pniw:1;
 465                 uint64_t reserved_52_53:2;
 466                 uint64_t out1_enb:1;
 467                 uint64_t out0_enb:1;
 468                 uint64_t reserved_48_49:2;
 469                 uint64_t ins1_enb:1;
 470                 uint64_t ins0_enb:1;
 471                 uint64_t reserved_44_45:2;
 472                 uint64_t ins1_64b:1;
 473                 uint64_t ins0_64b:1;
 474                 uint64_t pci_wdis:1;
 475                 uint64_t wait_com:1;
 476                 uint64_t reserved_37_39:3;
 477                 uint64_t max_word:5;
 478                 uint64_t reserved_10_31:22;
 479                 uint64_t timer:10;
 480 #else
 481                 uint64_t timer:10;
 482                 uint64_t reserved_10_31:22;
 483                 uint64_t max_word:5;
 484                 uint64_t reserved_37_39:3;
 485                 uint64_t wait_com:1;
 486                 uint64_t pci_wdis:1;
 487                 uint64_t ins0_64b:1;
 488                 uint64_t ins1_64b:1;
 489                 uint64_t reserved_44_45:2;
 490                 uint64_t ins0_enb:1;
 491                 uint64_t ins1_enb:1;
 492                 uint64_t reserved_48_49:2;
 493                 uint64_t out0_enb:1;
 494                 uint64_t out1_enb:1;
 495                 uint64_t reserved_52_53:2;
 496                 uint64_t dis_pniw:1;
 497                 uint64_t chip_rev:8;
 498                 uint64_t reserved_63_63:1;
 499 #endif
 500         } cn31xx;
 501         struct cvmx_npi_ctl_status_s cn38xx;
 502         struct cvmx_npi_ctl_status_s cn38xxp2;
 503         struct cvmx_npi_ctl_status_cn31xx cn50xx;
 504         struct cvmx_npi_ctl_status_s cn58xx;
 505         struct cvmx_npi_ctl_status_s cn58xxp1;
 506 };
 507
 508 union cvmx_npi_dbg_select {
 509         uint64_t u64;
 510         struct cvmx_npi_dbg_select_s {
 511 #ifdef __BIG_ENDIAN_BITFIELD
 512                 uint64_t reserved_16_63:48;
 513                 uint64_t dbg_sel:16;
 514 #else
 515                 uint64_t dbg_sel:16;
 516                 uint64_t reserved_16_63:48;
 517 #endif
 518         } s;
 519         struct cvmx_npi_dbg_select_s cn30xx;
 520         struct cvmx_npi_dbg_select_s cn31xx;
 521         struct cvmx_npi_dbg_select_s cn38xx;
 522         struct cvmx_npi_dbg_select_s cn38xxp2;
 523         struct cvmx_npi_dbg_select_s cn50xx;
 524         struct cvmx_npi_dbg_select_s cn58xx;
 525         struct cvmx_npi_dbg_select_s cn58xxp1;
 526 };
 527
 528 union cvmx_npi_dma_control {
 529         uint64_t u64;
 530         struct cvmx_npi_dma_control_s {
 531 #ifdef __BIG_ENDIAN_BITFIELD
 532                 uint64_t reserved_36_63:28;
 533                 uint64_t b0_lend:1;
 534                 uint64_t dwb_denb:1;
 535                 uint64_t dwb_ichk:9;
 536                 uint64_t fpa_que:3;
 537                 uint64_t o_add1:1;
 538                 uint64_t o_ro:1;
 539                 uint64_t o_ns:1;
 540                 uint64_t o_es:2;
 541                 uint64_t o_mode:1;
 542                 uint64_t hp_enb:1;
 543                 uint64_t lp_enb:1;
 544                 uint64_t csize:14;
 545 #else
 546                 uint64_t csize:14;
 547                 uint64_t lp_enb:1;
 548                 uint64_t hp_enb:1;
 549                 uint64_t o_mode:1;
 550                 uint64_t o_es:2;
 551                 uint64_t o_ns:1;
 552                 uint64_t o_ro:1;
 553                 uint64_t o_add1:1;
 554                 uint64_t fpa_que:3;
 555                 uint64_t dwb_ichk:9;
 556                 uint64_t dwb_denb:1;
 557                 uint64_t b0_lend:1;
 558                 uint64_t reserved_36_63:28;
 559 #endif
 560         } s;
 561         struct cvmx_npi_dma_control_s cn30xx;
 562         struct cvmx_npi_dma_control_s cn31xx;
 563         struct cvmx_npi_dma_control_s cn38xx;
 564         struct cvmx_npi_dma_control_s cn38xxp2;
 565         struct cvmx_npi_dma_control_s cn50xx;
 566         struct cvmx_npi_dma_control_s cn58xx;
 567         struct cvmx_npi_dma_control_s cn58xxp1;
 568 };
 569
 570 union cvmx_npi_dma_highp_counts {
 571         uint64_t u64;
 572         struct cvmx_npi_dma_highp_counts_s {
 573 #ifdef __BIG_ENDIAN_BITFIELD
 574                 uint64_t reserved_39_63:25;
 575                 uint64_t fcnt:7;
 576                 uint64_t dbell:32;
 577 #else
 578                 uint64_t dbell:32;
 579                 uint64_t fcnt:7;
 580                 uint64_t reserved_39_63:25;
 581 #endif
 582         } s;
 583         struct cvmx_npi_dma_highp_counts_s cn30xx;
 584         struct cvmx_npi_dma_highp_counts_s cn31xx;
 585         struct cvmx_npi_dma_highp_counts_s cn38xx;
 586         struct cvmx_npi_dma_highp_counts_s cn38xxp2;
 587         struct cvmx_npi_dma_highp_counts_s cn50xx;
 588         struct cvmx_npi_dma_highp_counts_s cn58xx;
 589         struct cvmx_npi_dma_highp_counts_s cn58xxp1;
 590 };
 591
 592 union cvmx_npi_dma_highp_naddr {
 593         uint64_t u64;
 594         struct cvmx_npi_dma_highp_naddr_s {
 595 #ifdef __BIG_ENDIAN_BITFIELD
 596                 uint64_t reserved_40_63:24;
 597                 uint64_t state:4;
 598                 uint64_t addr:36;
 599 #else
 600                 uint64_t addr:36;
 601                 uint64_t state:4;
 602                 uint64_t reserved_40_63:24;
 603 #endif
 604         } s;
 605         struct cvmx_npi_dma_highp_naddr_s cn30xx;
 606         struct cvmx_npi_dma_highp_naddr_s cn31xx;
 607         struct cvmx_npi_dma_highp_naddr_s cn38xx;
 608         struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
 609         struct cvmx_npi_dma_highp_naddr_s cn50xx;
 610         struct cvmx_npi_dma_highp_naddr_s cn58xx;
 611         struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
 612 };
 613
 614 union cvmx_npi_dma_lowp_counts {
 615         uint64_t u64;
 616         struct cvmx_npi_dma_lowp_counts_s {
 617 #ifdef __BIG_ENDIAN_BITFIELD
 618                 uint64_t reserved_39_63:25;
 619                 uint64_t fcnt:7;
 620                 uint64_t dbell:32;
 621 #else
 622                 uint64_t dbell:32;
 623                 uint64_t fcnt:7;
 624                 uint64_t reserved_39_63:25;
 625 #endif
 626         } s;
 627         struct cvmx_npi_dma_lowp_counts_s cn30xx;
 628         struct cvmx_npi_dma_lowp_counts_s cn31xx;
 629         struct cvmx_npi_dma_lowp_counts_s cn38xx;
 630         struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
 631         struct cvmx_npi_dma_lowp_counts_s cn50xx;
 632         struct cvmx_npi_dma_lowp_counts_s cn58xx;
 633         struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
 634 };
 635
 636 union cvmx_npi_dma_lowp_naddr {
 637         uint64_t u64;
 638         struct cvmx_npi_dma_lowp_naddr_s {
 639 #ifdef __BIG_ENDIAN_BITFIELD
 640                 uint64_t reserved_40_63:24;
 641                 uint64_t state:4;
 642                 uint64_t addr:36;
 643 #else
 644                 uint64_t addr:36;
 645                 uint64_t state:4;
 646                 uint64_t reserved_40_63:24;
 647 #endif
 648         } s;
 649         struct cvmx_npi_dma_lowp_naddr_s cn30xx;
 650         struct cvmx_npi_dma_lowp_naddr_s cn31xx;
 651         struct cvmx_npi_dma_lowp_naddr_s cn38xx;
 652         struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
 653         struct cvmx_npi_dma_lowp_naddr_s cn50xx;
 654         struct cvmx_npi_dma_lowp_naddr_s cn58xx;
 655         struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
 656 };
 657
 658 union cvmx_npi_highp_dbell {
 659         uint64_t u64;
 660         struct cvmx_npi_highp_dbell_s {
 661 #ifdef __BIG_ENDIAN_BITFIELD
 662                 uint64_t reserved_16_63:48;
 663                 uint64_t dbell:16;
 664 #else
 665                 uint64_t dbell:16;
 666                 uint64_t reserved_16_63:48;
 667 #endif
 668         } s;
 669         struct cvmx_npi_highp_dbell_s cn30xx;
 670         struct cvmx_npi_highp_dbell_s cn31xx;
 671         struct cvmx_npi_highp_dbell_s cn38xx;
 672         struct cvmx_npi_highp_dbell_s cn38xxp2;
 673         struct cvmx_npi_highp_dbell_s cn50xx;
 674         struct cvmx_npi_highp_dbell_s cn58xx;
 675         struct cvmx_npi_highp_dbell_s cn58xxp1;
 676 };
 677
 678 union cvmx_npi_highp_ibuff_saddr {
 679         uint64_t u64;
 680         struct cvmx_npi_highp_ibuff_saddr_s {
 681 #ifdef __BIG_ENDIAN_BITFIELD
 682                 uint64_t reserved_36_63:28;
 683                 uint64_t saddr:36;
 684 #else
 685                 uint64_t saddr:36;
 686                 uint64_t reserved_36_63:28;
 687 #endif
 688         } s;
 689         struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
 690         struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
 691         struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
 692         struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
 693         struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
 694         struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
 695         struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
 696 };
 697
 698 union cvmx_npi_input_control {
 699         uint64_t u64;
 700         struct cvmx_npi_input_control_s {
 701 #ifdef __BIG_ENDIAN_BITFIELD
 702                 uint64_t reserved_23_63:41;
 703                 uint64_t pkt_rr:1;
 704                 uint64_t pbp_dhi:13;
 705                 uint64_t d_nsr:1;
 706                 uint64_t d_esr:2;
 707                 uint64_t d_ror:1;
 708                 uint64_t use_csr:1;
 709                 uint64_t nsr:1;
 710                 uint64_t esr:2;
 711                 uint64_t ror:1;
 712 #else
 713                 uint64_t ror:1;
 714                 uint64_t esr:2;
 715                 uint64_t nsr:1;
 716                 uint64_t use_csr:1;
 717                 uint64_t d_ror:1;
 718                 uint64_t d_esr:2;
 719                 uint64_t d_nsr:1;
 720                 uint64_t pbp_dhi:13;
 721                 uint64_t pkt_rr:1;
 722                 uint64_t reserved_23_63:41;
 723 #endif
 724         } s;
 725         struct cvmx_npi_input_control_cn30xx {
 726 #ifdef __BIG_ENDIAN_BITFIELD
 727                 uint64_t reserved_22_63:42;
 728                 uint64_t pbp_dhi:13;
 729                 uint64_t d_nsr:1;
 730                 uint64_t d_esr:2;
 731                 uint64_t d_ror:1;
 732                 uint64_t use_csr:1;
 733                 uint64_t nsr:1;
 734                 uint64_t esr:2;
 735                 uint64_t ror:1;
 736 #else
 737                 uint64_t ror:1;
 738                 uint64_t esr:2;
 739                 uint64_t nsr:1;
 740                 uint64_t use_csr:1;
 741                 uint64_t d_ror:1;
 742                 uint64_t d_esr:2;
 743                 uint64_t d_nsr:1;
 744                 uint64_t pbp_dhi:13;
 745                 uint64_t reserved_22_63:42;
 746 #endif
 747         } cn30xx;
 748         struct cvmx_npi_input_control_cn30xx cn31xx;
 749         struct cvmx_npi_input_control_s cn38xx;
 750         struct cvmx_npi_input_control_cn30xx cn38xxp2;
 751         struct cvmx_npi_input_control_s cn50xx;
 752         struct cvmx_npi_input_control_s cn58xx;
 753         struct cvmx_npi_input_control_s cn58xxp1;
 754 };
 755
 756 union cvmx_npi_int_enb {
 757         uint64_t u64;
 758         struct cvmx_npi_int_enb_s {
 759 #ifdef __BIG_ENDIAN_BITFIELD
 760                 uint64_t reserved_62_63:2;
 761                 uint64_t q1_a_f:1;
 762                 uint64_t q1_s_e:1;
 763                 uint64_t pdf_p_f:1;
 764                 uint64_t pdf_p_e:1;
 765                 uint64_t pcf_p_f:1;
 766                 uint64_t pcf_p_e:1;
 767                 uint64_t rdx_s_e:1;
 768                 uint64_t rwx_s_e:1;
 769                 uint64_t pnc_a_f:1;
 770                 uint64_t pnc_s_e:1;
 771                 uint64_t com_a_f:1;
 772                 uint64_t com_s_e:1;
 773                 uint64_t q3_a_f:1;
 774                 uint64_t q3_s_e:1;
 775                 uint64_t q2_a_f:1;
 776                 uint64_t q2_s_e:1;
 777                 uint64_t pcr_a_f:1;
 778                 uint64_t pcr_s_e:1;
 779                 uint64_t fcr_a_f:1;
 780                 uint64_t fcr_s_e:1;
 781                 uint64_t iobdma:1;
 782                 uint64_t p_dperr:1;
 783                 uint64_t win_rto:1;
 784                 uint64_t i3_pperr:1;
 785                 uint64_t i2_pperr:1;
 786                 uint64_t i1_pperr:1;
 787                 uint64_t i0_pperr:1;
 788                 uint64_t p3_ptout:1;
 789                 uint64_t p2_ptout:1;
 790                 uint64_t p1_ptout:1;
 791                 uint64_t p0_ptout:1;
 792                 uint64_t p3_pperr:1;
 793                 uint64_t p2_pperr:1;
 794                 uint64_t p1_pperr:1;
 795                 uint64_t p0_pperr:1;
 796                 uint64_t g3_rtout:1;
 797                 uint64_t g2_rtout:1;
 798                 uint64_t g1_rtout:1;
 799                 uint64_t g0_rtout:1;
 800                 uint64_t p3_perr:1;
 801                 uint64_t p2_perr:1;
 802                 uint64_t p1_perr:1;
 803                 uint64_t p0_perr:1;
 804                 uint64_t p3_rtout:1;
 805                 uint64_t p2_rtout:1;
 806                 uint64_t p1_rtout:1;
 807                 uint64_t p0_rtout:1;
 808                 uint64_t i3_overf:1;
 809                 uint64_t i2_overf:1;
 810                 uint64_t i1_overf:1;
 811                 uint64_t i0_overf:1;
 812                 uint64_t i3_rtout:1;
 813                 uint64_t i2_rtout:1;
 814                 uint64_t i1_rtout:1;
 815                 uint64_t i0_rtout:1;
 816                 uint64_t po3_2sml:1;
 817                 uint64_t po2_2sml:1;
 818                 uint64_t po1_2sml:1;
 819                 uint64_t po0_2sml:1;
 820                 uint64_t pci_rsl:1;
 821                 uint64_t rml_wto:1;
 822                 uint64_t rml_rto:1;
 823 #else
 824                 uint64_t rml_rto:1;
 825                 uint64_t rml_wto:1;
 826                 uint64_t pci_rsl:1;
 827                 uint64_t po0_2sml:1;
 828                 uint64_t po1_2sml:1;
 829                 uint64_t po2_2sml:1;
 830                 uint64_t po3_2sml:1;
 831                 uint64_t i0_rtout:1;
 832                 uint64_t i1_rtout:1;
 833                 uint64_t i2_rtout:1;
 834                 uint64_t i3_rtout:1;
 835                 uint64_t i0_overf:1;
 836                 uint64_t i1_overf:1;
 837                 uint64_t i2_overf:1;
 838                 uint64_t i3_overf:1;
 839                 uint64_t p0_rtout:1;
 840                 uint64_t p1_rtout:1;
 841                 uint64_t p2_rtout:1;
 842                 uint64_t p3_rtout:1;
 843                 uint64_t p0_perr:1;
 844                 uint64_t p1_perr:1;
 845                 uint64_t p2_perr:1;
 846                 uint64_t p3_perr:1;
 847                 uint64_t g0_rtout:1;
 848                 uint64_t g1_rtout:1;
 849                 uint64_t g2_rtout:1;
 850                 uint64_t g3_rtout:1;
 851                 uint64_t p0_pperr:1;
 852                 uint64_t p1_pperr:1;
 853                 uint64_t p2_pperr:1;
 854                 uint64_t p3_pperr:1;
 855                 uint64_t p0_ptout:1;
 856                 uint64_t p1_ptout:1;
 857                 uint64_t p2_ptout:1;
 858                 uint64_t p3_ptout:1;
 859                 uint64_t i0_pperr:1;
 860                 uint64_t i1_pperr:1;
 861                 uint64_t i2_pperr:1;
 862                 uint64_t i3_pperr:1;
 863                 uint64_t win_rto:1;
 864                 uint64_t p_dperr:1;
 865                 uint64_t iobdma:1;
 866                 uint64_t fcr_s_e:1;
 867                 uint64_t fcr_a_f:1;
 868                 uint64_t pcr_s_e:1;
 869                 uint64_t pcr_a_f:1;
 870                 uint64_t q2_s_e:1;
 871                 uint64_t q2_a_f:1;
 872                 uint64_t q3_s_e:1;
 873                 uint64_t q3_a_f:1;
 874                 uint64_t com_s_e:1;
 875                 uint64_t com_a_f:1;
 876                 uint64_t pnc_s_e:1;
 877                 uint64_t pnc_a_f:1;
 878                 uint64_t rwx_s_e:1;
 879                 uint64_t rdx_s_e:1;
 880                 uint64_t pcf_p_e:1;
 881                 uint64_t pcf_p_f:1;
 882                 uint64_t pdf_p_e:1;
 883                 uint64_t pdf_p_f:1;
 884                 uint64_t q1_s_e:1;
 885                 uint64_t q1_a_f:1;
 886                 uint64_t reserved_62_63:2;
 887 #endif
 888         } s;
 889         struct cvmx_npi_int_enb_cn30xx {
 890 #ifdef __BIG_ENDIAN_BITFIELD
 891                 uint64_t reserved_62_63:2;
 892                 uint64_t q1_a_f:1;
 893                 uint64_t q1_s_e:1;
 894                 uint64_t pdf_p_f:1;
 895                 uint64_t pdf_p_e:1;
 896                 uint64_t pcf_p_f:1;
 897                 uint64_t pcf_p_e:1;
 898                 uint64_t rdx_s_e:1;
 899                 uint64_t rwx_s_e:1;
 900                 uint64_t pnc_a_f:1;
 901                 uint64_t pnc_s_e:1;
 902                 uint64_t com_a_f:1;
 903                 uint64_t com_s_e:1;
 904                 uint64_t q3_a_f:1;
 905                 uint64_t q3_s_e:1;
 906                 uint64_t q2_a_f:1;
 907                 uint64_t q2_s_e:1;
 908                 uint64_t pcr_a_f:1;
 909                 uint64_t pcr_s_e:1;
 910                 uint64_t fcr_a_f:1;
 911                 uint64_t fcr_s_e:1;
 912                 uint64_t iobdma:1;
 913                 uint64_t p_dperr:1;
 914                 uint64_t win_rto:1;
 915                 uint64_t reserved_36_38:3;
 916                 uint64_t i0_pperr:1;
 917                 uint64_t reserved_32_34:3;
 918                 uint64_t p0_ptout:1;
 919                 uint64_t reserved_28_30:3;
 920                 uint64_t p0_pperr:1;
 921                 uint64_t reserved_24_26:3;
 922                 uint64_t g0_rtout:1;
 923                 uint64_t reserved_20_22:3;
 924                 uint64_t p0_perr:1;
 925                 uint64_t reserved_16_18:3;
 926                 uint64_t p0_rtout:1;
 927                 uint64_t reserved_12_14:3;
 928                 uint64_t i0_overf:1;
 929                 uint64_t reserved_8_10:3;
 930                 uint64_t i0_rtout:1;
 931                 uint64_t reserved_4_6:3;
 932                 uint64_t po0_2sml:1;
 933                 uint64_t pci_rsl:1;
 934                 uint64_t rml_wto:1;
 935                 uint64_t rml_rto:1;
 936 #else
 937                 uint64_t rml_rto:1;
 938                 uint64_t rml_wto:1;
 939                 uint64_t pci_rsl:1;
 940                 uint64_t po0_2sml:1;
 941                 uint64_t reserved_4_6:3;
 942                 uint64_t i0_rtout:1;
 943                 uint64_t reserved_8_10:3;
 944                 uint64_t i0_overf:1;
 945                 uint64_t reserved_12_14:3;
 946                 uint64_t p0_rtout:1;
 947                 uint64_t reserved_16_18:3;
 948                 uint64_t p0_perr:1;
 949                 uint64_t reserved_20_22:3;
 950                 uint64_t g0_rtout:1;
 951                 uint64_t reserved_24_26:3;
 952                 uint64_t p0_pperr:1;
 953                 uint64_t reserved_28_30:3;
 954                 uint64_t p0_ptout:1;
 955                 uint64_t reserved_32_34:3;
 956                 uint64_t i0_pperr:1;
 957                 uint64_t reserved_36_38:3;
 958                 uint64_t win_rto:1;
 959                 uint64_t p_dperr:1;
 960                 uint64_t iobdma:1;
 961                 uint64_t fcr_s_e:1;
 962                 uint64_t fcr_a_f:1;
 963                 uint64_t pcr_s_e:1;
 964                 uint64_t pcr_a_f:1;
 965                 uint64_t q2_s_e:1;
 966                 uint64_t q2_a_f:1;
 967                 uint64_t q3_s_e:1;
 968                 uint64_t q3_a_f:1;
 969                 uint64_t com_s_e:1;
 970                 uint64_t com_a_f:1;
 971                 uint64_t pnc_s_e:1;
 972                 uint64_t pnc_a_f:1;
 973                 uint64_t rwx_s_e:1;
 974                 uint64_t rdx_s_e:1;
 975                 uint64_t pcf_p_e:1;
 976                 uint64_t pcf_p_f:1;
 977                 uint64_t pdf_p_e:1;
 978                 uint64_t pdf_p_f:1;
 979                 uint64_t q1_s_e:1;
 980                 uint64_t q1_a_f:1;
 981                 uint64_t reserved_62_63:2;
 982 #endif
 983         } cn30xx;
 984         struct cvmx_npi_int_enb_cn31xx {
 985 #ifdef __BIG_ENDIAN_BITFIELD
 986                 uint64_t reserved_62_63:2;
 987                 uint64_t q1_a_f:1;
 988                 uint64_t q1_s_e:1;
 989                 uint64_t pdf_p_f:1;
 990                 uint64_t pdf_p_e:1;
 991                 uint64_t pcf_p_f:1;
 992                 uint64_t pcf_p_e:1;
 993                 uint64_t rdx_s_e:1;
 994                 uint64_t rwx_s_e:1;
 995                 uint64_t pnc_a_f:1;
 996                 uint64_t pnc_s_e:1;
 997                 uint64_t com_a_f:1;
 998                 uint64_t com_s_e:1;
 999                 uint64_t q3_a_f:1;
1000                 uint64_t q3_s_e:1;
1001                 uint64_t q2_a_f:1;
1002                 uint64_t q2_s_e:1;
1003                 uint64_t pcr_a_f:1;
1004                 uint64_t pcr_s_e:1;
1005                 uint64_t fcr_a_f:1;
1006                 uint64_t fcr_s_e:1;
1007                 uint64_t iobdma:1;
1008                 uint64_t p_dperr:1;
1009                 uint64_t win_rto:1;
1010                 uint64_t reserved_37_38:2;
1011                 uint64_t i1_pperr:1;
1012                 uint64_t i0_pperr:1;
1013                 uint64_t reserved_33_34:2;
1014                 uint64_t p1_ptout:1;
1015                 uint64_t p0_ptout:1;
1016                 uint64_t reserved_29_30:2;
1017                 uint64_t p1_pperr:1;
1018                 uint64_t p0_pperr:1;
1019                 uint64_t reserved_25_26:2;
1020                 uint64_t g1_rtout:1;
1021                 uint64_t g0_rtout:1;
1022                 uint64_t reserved_21_22:2;
1023                 uint64_t p1_perr:1;
1024                 uint64_t p0_perr:1;
1025                 uint64_t reserved_17_18:2;
1026                 uint64_t p1_rtout:1;
1027                 uint64_t p0_rtout:1;
1028                 uint64_t reserved_13_14:2;
1029                 uint64_t i1_overf:1;
1030                 uint64_t i0_overf:1;
1031                 uint64_t reserved_9_10:2;
1032                 uint64_t i1_rtout:1;
1033                 uint64_t i0_rtout:1;
1034                 uint64_t reserved_5_6:2;
1035                 uint64_t po1_2sml:1;
1036                 uint64_t po0_2sml:1;
1037                 uint64_t pci_rsl:1;
1038                 uint64_t rml_wto:1;
1039                 uint64_t rml_rto:1;
1040 #else
1041                 uint64_t rml_rto:1;
1042                 uint64_t rml_wto:1;
1043                 uint64_t pci_rsl:1;
1044                 uint64_t po0_2sml:1;
1045                 uint64_t po1_2sml:1;
1046                 uint64_t reserved_5_6:2;
1047                 uint64_t i0_rtout:1;
1048                 uint64_t i1_rtout:1;
1049                 uint64_t reserved_9_10:2;
1050                 uint64_t i0_overf:1;
1051                 uint64_t i1_overf:1;
1052                 uint64_t reserved_13_14:2;
1053                 uint64_t p0_rtout:1;
1054                 uint64_t p1_rtout:1;
1055                 uint64_t reserved_17_18:2;
1056                 uint64_t p0_perr:1;
1057                 uint64_t p1_perr:1;
1058                 uint64_t reserved_21_22:2;
1059                 uint64_t g0_rtout:1;
1060                 uint64_t g1_rtout:1;
1061                 uint64_t reserved_25_26:2;
1062                 uint64_t p0_pperr:1;
1063                 uint64_t p1_pperr:1;
1064                 uint64_t reserved_29_30:2;
1065                 uint64_t p0_ptout:1;
1066                 uint64_t p1_ptout:1;
1067                 uint64_t reserved_33_34:2;
1068                 uint64_t i0_pperr:1;
1069                 uint64_t i1_pperr:1;
1070                 uint64_t reserved_37_38:2;
1071                 uint64_t win_rto:1;
1072                 uint64_t p_dperr:1;
1073                 uint64_t iobdma:1;
1074                 uint64_t fcr_s_e:1;
1075                 uint64_t fcr_a_f:1;
1076                 uint64_t pcr_s_e:1;
1077                 uint64_t pcr_a_f:1;
1078                 uint64_t q2_s_e:1;
1079                 uint64_t q2_a_f:1;
1080                 uint64_t q3_s_e:1;
1081                 uint64_t q3_a_f:1;
1082                 uint64_t com_s_e:1;
1083                 uint64_t com_a_f:1;
1084                 uint64_t pnc_s_e:1;
1085                 uint64_t pnc_a_f:1;
1086                 uint64_t rwx_s_e:1;
1087                 uint64_t rdx_s_e:1;
1088                 uint64_t pcf_p_e:1;
1089                 uint64_t pcf_p_f:1;
1090                 uint64_t pdf_p_e:1;
1091                 uint64_t pdf_p_f:1;
1092                 uint64_t q1_s_e:1;
1093                 uint64_t q1_a_f:1;
1094                 uint64_t reserved_62_63:2;
1095 #endif
1096         } cn31xx;
1097         struct cvmx_npi_int_enb_s cn38xx;
1098         struct cvmx_npi_int_enb_cn38xxp2 {
1099 #ifdef __BIG_ENDIAN_BITFIELD
1100                 uint64_t reserved_42_63:22;
1101                 uint64_t iobdma:1;
1102                 uint64_t p_dperr:1;
1103                 uint64_t win_rto:1;
1104                 uint64_t i3_pperr:1;
1105                 uint64_t i2_pperr:1;
1106                 uint64_t i1_pperr:1;
1107                 uint64_t i0_pperr:1;
1108                 uint64_t p3_ptout:1;
1109                 uint64_t p2_ptout:1;
1110                 uint64_t p1_ptout:1;
1111                 uint64_t p0_ptout:1;
1112                 uint64_t p3_pperr:1;
1113                 uint64_t p2_pperr:1;
1114                 uint64_t p1_pperr:1;
1115                 uint64_t p0_pperr:1;
1116                 uint64_t g3_rtout:1;
1117                 uint64_t g2_rtout:1;
1118                 uint64_t g1_rtout:1;
1119                 uint64_t g0_rtout:1;
1120                 uint64_t p3_perr:1;
1121                 uint64_t p2_perr:1;
1122                 uint64_t p1_perr:1;
1123                 uint64_t p0_perr:1;
1124                 uint64_t p3_rtout:1;
1125                 uint64_t p2_rtout:1;
1126                 uint64_t p1_rtout:1;
1127                 uint64_t p0_rtout:1;
1128                 uint64_t i3_overf:1;
1129                 uint64_t i2_overf:1;
1130                 uint64_t i1_overf:1;
1131                 uint64_t i0_overf:1;
1132                 uint64_t i3_rtout:1;
1133                 uint64_t i2_rtout:1;
1134                 uint64_t i1_rtout:1;
1135                 uint64_t i0_rtout:1;
1136                 uint64_t po3_2sml:1;
1137                 uint64_t po2_2sml:1;
1138                 uint64_t po1_2sml:1;
1139                 uint64_t po0_2sml:1;
1140                 uint64_t pci_rsl:1;
1141                 uint64_t rml_wto:1;
1142                 uint64_t rml_rto:1;
1143 #else
1144                 uint64_t rml_rto:1;
1145                 uint64_t rml_wto:1;
1146                 uint64_t pci_rsl:1;
1147                 uint64_t po0_2sml:1;
1148                 uint64_t po1_2sml:1;
1149                 uint64_t po2_2sml:1;
1150                 uint64_t po3_2sml:1;
1151                 uint64_t i0_rtout:1;
1152                 uint64_t i1_rtout:1;
1153                 uint64_t i2_rtout:1;
1154                 uint64_t i3_rtout:1;
1155                 uint64_t i0_overf:1;
1156                 uint64_t i1_overf:1;
1157                 uint64_t i2_overf:1;
1158                 uint64_t i3_overf:1;
1159                 uint64_t p0_rtout:1;
1160                 uint64_t p1_rtout:1;
1161                 uint64_t p2_rtout:1;
1162                 uint64_t p3_rtout:1;
1163                 uint64_t p0_perr:1;
1164                 uint64_t p1_perr:1;
1165                 uint64_t p2_perr:1;
1166                 uint64_t p3_perr:1;
1167                 uint64_t g0_rtout:1;
1168                 uint64_t g1_rtout:1;
1169                 uint64_t g2_rtout:1;
1170                 uint64_t g3_rtout:1;
1171                 uint64_t p0_pperr:1;
1172                 uint64_t p1_pperr:1;
1173                 uint64_t p2_pperr:1;
1174                 uint64_t p3_pperr:1;
1175                 uint64_t p0_ptout:1;
1176                 uint64_t p1_ptout:1;
1177                 uint64_t p2_ptout:1;
1178                 uint64_t p3_ptout:1;
1179                 uint64_t i0_pperr:1;
1180                 uint64_t i1_pperr:1;
1181                 uint64_t i2_pperr:1;
1182                 uint64_t i3_pperr:1;
1183                 uint64_t win_rto:1;
1184                 uint64_t p_dperr:1;
1185                 uint64_t iobdma:1;
1186                 uint64_t reserved_42_63:22;
1187 #endif
1188         } cn38xxp2;
1189         struct cvmx_npi_int_enb_cn31xx cn50xx;
1190         struct cvmx_npi_int_enb_s cn58xx;
1191         struct cvmx_npi_int_enb_s cn58xxp1;
1192 };
1193
1194 union cvmx_npi_int_sum {
1195         uint64_t u64;
1196         struct cvmx_npi_int_sum_s {
1197 #ifdef __BIG_ENDIAN_BITFIELD
1198                 uint64_t reserved_62_63:2;
1199                 uint64_t q1_a_f:1;
1200                 uint64_t q1_s_e:1;
1201                 uint64_t pdf_p_f:1;
1202                 uint64_t pdf_p_e:1;
1203                 uint64_t pcf_p_f:1;
1204                 uint64_t pcf_p_e:1;
1205                 uint64_t rdx_s_e:1;
1206                 uint64_t rwx_s_e:1;
1207                 uint64_t pnc_a_f:1;
1208                 uint64_t pnc_s_e:1;
1209                 uint64_t com_a_f:1;
1210                 uint64_t com_s_e:1;
1211                 uint64_t q3_a_f:1;
1212                 uint64_t q3_s_e:1;
1213                 uint64_t q2_a_f:1;
1214                 uint64_t q2_s_e:1;
1215                 uint64_t pcr_a_f:1;
1216                 uint64_t pcr_s_e:1;
1217                 uint64_t fcr_a_f:1;
1218                 uint64_t fcr_s_e:1;
1219                 uint64_t iobdma:1;
1220                 uint64_t p_dperr:1;
1221                 uint64_t win_rto:1;
1222                 uint64_t i3_pperr:1;
1223                 uint64_t i2_pperr:1;
1224                 uint64_t i1_pperr:1;
1225                 uint64_t i0_pperr:1;
1226                 uint64_t p3_ptout:1;
1227                 uint64_t p2_ptout:1;
1228                 uint64_t p1_ptout:1;
1229                 uint64_t p0_ptout:1;
1230                 uint64_t p3_pperr:1;
1231                 uint64_t p2_pperr:1;
1232                 uint64_t p1_pperr:1;
1233                 uint64_t p0_pperr:1;
1234                 uint64_t g3_rtout:1;
1235                 uint64_t g2_rtout:1;
1236                 uint64_t g1_rtout:1;
1237                 uint64_t g0_rtout:1;
1238                 uint64_t p3_perr:1;
1239                 uint64_t p2_perr:1;
1240                 uint64_t p1_perr:1;
1241                 uint64_t p0_perr:1;
1242                 uint64_t p3_rtout:1;
1243                 uint64_t p2_rtout:1;
1244                 uint64_t p1_rtout:1;
1245                 uint64_t p0_rtout:1;
1246                 uint64_t i3_overf:1;
1247                 uint64_t i2_overf:1;
1248                 uint64_t i1_overf:1;
1249                 uint64_t i0_overf:1;
1250                 uint64_t i3_rtout:1;
1251                 uint64_t i2_rtout:1;
1252                 uint64_t i1_rtout:1;
1253                 uint64_t i0_rtout:1;
1254                 uint64_t po3_2sml:1;
1255                 uint64_t po2_2sml:1;
1256                 uint64_t po1_2sml:1;
1257                 uint64_t po0_2sml:1;
1258                 uint64_t pci_rsl:1;
1259                 uint64_t rml_wto:1;
1260                 uint64_t rml_rto:1;
1261 #else
1262                 uint64_t rml_rto:1;
1263                 uint64_t rml_wto:1;
1264                 uint64_t pci_rsl:1;
1265                 uint64_t po0_2sml:1;
1266                 uint64_t po1_2sml:1;
1267                 uint64_t po2_2sml:1;
1268                 uint64_t po3_2sml:1;
1269                 uint64_t i0_rtout:1;
1270                 uint64_t i1_rtout:1;
1271                 uint64_t i2_rtout:1;
1272                 uint64_t i3_rtout:1;
1273                 uint64_t i0_overf:1;
1274                 uint64_t i1_overf:1;
1275                 uint64_t i2_overf:1;
1276                 uint64_t i3_overf:1;
1277                 uint64_t p0_rtout:1;
1278                 uint64_t p1_rtout:1;
1279                 uint64_t p2_rtout:1;
1280                 uint64_t p3_rtout:1;
1281                 uint64_t p0_perr:1;
1282                 uint64_t p1_perr:1;
1283                 uint64_t p2_perr:1;
1284                 uint64_t p3_perr:1;
1285                 uint64_t g0_rtout:1;
1286                 uint64_t g1_rtout:1;
1287                 uint64_t g2_rtout:1;
1288                 uint64_t g3_rtout:1;
1289                 uint64_t p0_pperr:1;
1290                 uint64_t p1_pperr:1;
1291                 uint64_t p2_pperr:1;
1292                 uint64_t p3_pperr:1;
1293                 uint64_t p0_ptout:1;
1294                 uint64_t p1_ptout:1;
1295                 uint64_t p2_ptout:1;
1296                 uint64_t p3_ptout:1;
1297                 uint64_t i0_pperr:1;
1298                 uint64_t i1_pperr:1;
1299                 uint64_t i2_pperr:1;
1300                 uint64_t i3_pperr:1;
1301                 uint64_t win_rto:1;
1302                 uint64_t p_dperr:1;
1303                 uint64_t iobdma:1;
1304                 uint64_t fcr_s_e:1;
1305                 uint64_t fcr_a_f:1;
1306                 uint64_t pcr_s_e:1;
1307                 uint64_t pcr_a_f:1;
1308                 uint64_t q2_s_e:1;
1309                 uint64_t q2_a_f:1;
1310                 uint64_t q3_s_e:1;
1311                 uint64_t q3_a_f:1;
1312                 uint64_t com_s_e:1;
1313                 uint64_t com_a_f:1;
1314                 uint64_t pnc_s_e:1;
1315                 uint64_t pnc_a_f:1;
1316                 uint64_t rwx_s_e:1;
1317                 uint64_t rdx_s_e:1;
1318                 uint64_t pcf_p_e:1;
1319                 uint64_t pcf_p_f:1;
1320                 uint64_t pdf_p_e:1;
1321                 uint64_t pdf_p_f:1;
1322                 uint64_t q1_s_e:1;
1323                 uint64_t q1_a_f:1;
1324                 uint64_t reserved_62_63:2;
1325 #endif
1326         } s;
1327         struct cvmx_npi_int_sum_cn30xx {
1328 #ifdef __BIG_ENDIAN_BITFIELD
1329                 uint64_t reserved_62_63:2;
1330                 uint64_t q1_a_f:1;
1331                 uint64_t q1_s_e:1;
1332                 uint64_t pdf_p_f:1;
1333                 uint64_t pdf_p_e:1;
1334                 uint64_t pcf_p_f:1;
1335                 uint64_t pcf_p_e:1;
1336                 uint64_t rdx_s_e:1;
1337                 uint64_t rwx_s_e:1;
1338                 uint64_t pnc_a_f:1;
1339                 uint64_t pnc_s_e:1;
1340                 uint64_t com_a_f:1;
1341                 uint64_t com_s_e:1;
1342                 uint64_t q3_a_f:1;
1343                 uint64_t q3_s_e:1;
1344                 uint64_t q2_a_f:1;
1345                 uint64_t q2_s_e:1;
1346                 uint64_t pcr_a_f:1;
1347                 uint64_t pcr_s_e:1;
1348                 uint64_t fcr_a_f:1;
1349                 uint64_t fcr_s_e:1;
1350                 uint64_t iobdma:1;
1351                 uint64_t p_dperr:1;
1352                 uint64_t win_rto:1;
1353                 uint64_t reserved_36_38:3;
1354                 uint64_t i0_pperr:1;
1355                 uint64_t reserved_32_34:3;
1356                 uint64_t p0_ptout:1;
1357                 uint64_t reserved_28_30:3;
1358                 uint64_t p0_pperr:1;
1359                 uint64_t reserved_24_26:3;
1360                 uint64_t g0_rtout:1;
1361                 uint64_t reserved_20_22:3;
1362                 uint64_t p0_perr:1;
1363                 uint64_t reserved_16_18:3;
1364                 uint64_t p0_rtout:1;
1365                 uint64_t reserved_12_14:3;
1366                 uint64_t i0_overf:1;
1367                 uint64_t reserved_8_10:3;
1368                 uint64_t i0_rtout:1;
1369                 uint64_t reserved_4_6:3;
1370                 uint64_t po0_2sml:1;
1371                 uint64_t pci_rsl:1;
1372                 uint64_t rml_wto:1;
1373                 uint64_t rml_rto:1;
1374 #else
1375                 uint64_t rml_rto:1;
1376                 uint64_t rml_wto:1;
1377                 uint64_t pci_rsl:1;
1378                 uint64_t po0_2sml:1;
1379                 uint64_t reserved_4_6:3;
1380                 uint64_t i0_rtout:1;
1381                 uint64_t reserved_8_10:3;
1382                 uint64_t i0_overf:1;
1383                 uint64_t reserved_12_14:3;
1384                 uint64_t p0_rtout:1;
1385                 uint64_t reserved_16_18:3;
1386                 uint64_t p0_perr:1;
1387                 uint64_t reserved_20_22:3;
1388                 uint64_t g0_rtout:1;
1389                 uint64_t reserved_24_26:3;
1390                 uint64_t p0_pperr:1;
1391                 uint64_t reserved_28_30:3;
1392                 uint64_t p0_ptout:1;
1393                 uint64_t reserved_32_34:3;
1394                 uint64_t i0_pperr:1;
1395                 uint64_t reserved_36_38:3;
1396                 uint64_t win_rto:1;
1397                 uint64_t p_dperr:1;
1398                 uint64_t iobdma:1;
1399                 uint64_t fcr_s_e:1;
1400                 uint64_t fcr_a_f:1;
1401                 uint64_t pcr_s_e:1;
1402                 uint64_t pcr_a_f:1;
1403                 uint64_t q2_s_e:1;
1404                 uint64_t q2_a_f:1;
1405                 uint64_t q3_s_e:1;
1406                 uint64_t q3_a_f:1;
1407                 uint64_t com_s_e:1;
1408                 uint64_t com_a_f:1;
1409                 uint64_t pnc_s_e:1;
1410                 uint64_t pnc_a_f:1;
1411                 uint64_t rwx_s_e:1;
1412                 uint64_t rdx_s_e:1;
1413                 uint64_t pcf_p_e:1;
1414                 uint64_t pcf_p_f:1;
1415                 uint64_t pdf_p_e:1;
1416                 uint64_t pdf_p_f:1;
1417                 uint64_t q1_s_e:1;
1418                 uint64_t q1_a_f:1;
1419                 uint64_t reserved_62_63:2;
1420 #endif
1421         } cn30xx;
1422         struct cvmx_npi_int_sum_cn31xx {
1423 #ifdef __BIG_ENDIAN_BITFIELD
1424                 uint64_t reserved_62_63:2;
1425                 uint64_t q1_a_f:1;
1426                 uint64_t q1_s_e:1;
1427                 uint64_t pdf_p_f:1;
1428                 uint64_t pdf_p_e:1;
1429                 uint64_t pcf_p_f:1;
1430                 uint64_t pcf_p_e:1;
1431                 uint64_t rdx_s_e:1;
1432                 uint64_t rwx_s_e:1;
1433                 uint64_t pnc_a_f:1;
1434                 uint64_t pnc_s_e:1;
1435                 uint64_t com_a_f:1;
1436                 uint64_t com_s_e:1;
1437                 uint64_t q3_a_f:1;
1438                 uint64_t q3_s_e:1;
1439                 uint64_t q2_a_f:1;
1440                 uint64_t q2_s_e:1;
1441                 uint64_t pcr_a_f:1;
1442                 uint64_t pcr_s_e:1;
1443                 uint64_t fcr_a_f:1;
1444                 uint64_t fcr_s_e:1;
1445                 uint64_t iobdma:1;
1446                 uint64_t p_dperr:1;
1447                 uint64_t win_rto:1;
1448                 uint64_t reserved_37_38:2;
1449                 uint64_t i1_pperr:1;
1450                 uint64_t i0_pperr:1;
1451                 uint64_t reserved_33_34:2;
1452                 uint64_t p1_ptout:1;
1453                 uint64_t p0_ptout:1;
1454                 uint64_t reserved_29_30:2;
1455                 uint64_t p1_pperr:1;
1456                 uint64_t p0_pperr:1;
1457                 uint64_t reserved_25_26:2;
1458                 uint64_t g1_rtout:1;
1459                 uint64_t g0_rtout:1;
1460                 uint64_t reserved_21_22:2;
1461                 uint64_t p1_perr:1;
1462                 uint64_t p0_perr:1;
1463                 uint64_t reserved_17_18:2;
1464                 uint64_t p1_rtout:1;
1465                 uint64_t p0_rtout:1;
1466                 uint64_t reserved_13_14:2;
1467                 uint64_t i1_overf:1;
1468                 uint64_t i0_overf:1;
1469                 uint64_t reserved_9_10:2;
1470                 uint64_t i1_rtout:1;
1471                 uint64_t i0_rtout:1;
1472                 uint64_t reserved_5_6:2;
1473                 uint64_t po1_2sml:1;
1474                 uint64_t po0_2sml:1;
1475                 uint64_t pci_rsl:1;
1476                 uint64_t rml_wto:1;
1477                 uint64_t rml_rto:1;
1478 #else
1479                 uint64_t rml_rto:1;
1480                 uint64_t rml_wto:1;
1481                 uint64_t pci_rsl:1;
1482                 uint64_t po0_2sml:1;
1483                 uint64_t po1_2sml:1;
1484                 uint64_t reserved_5_6:2;
1485                 uint64_t i0_rtout:1;
1486                 uint64_t i1_rtout:1;
1487                 uint64_t reserved_9_10:2;
1488                 uint64_t i0_overf:1;
1489                 uint64_t i1_overf:1;
1490                 uint64_t reserved_13_14:2;
1491                 uint64_t p0_rtout:1;
1492                 uint64_t p1_rtout:1;
1493                 uint64_t reserved_17_18:2;
1494                 uint64_t p0_perr:1;
1495                 uint64_t p1_perr:1;
1496                 uint64_t reserved_21_22:2;
1497                 uint64_t g0_rtout:1;
1498                 uint64_t g1_rtout:1;
1499                 uint64_t reserved_25_26:2;
1500                 uint64_t p0_pperr:1;
1501                 uint64_t p1_pperr:1;
1502                 uint64_t reserved_29_30:2;
1503                 uint64_t p0_ptout:1;
1504                 uint64_t p1_ptout:1;
1505                 uint64_t reserved_33_34:2;
1506                 uint64_t i0_pperr:1;
1507                 uint64_t i1_pperr:1;
1508                 uint64_t reserved_37_38:2;
1509                 uint64_t win_rto:1;
1510                 uint64_t p_dperr:1;
1511                 uint64_t iobdma:1;
1512                 uint64_t fcr_s_e:1;
1513                 uint64_t fcr_a_f:1;
1514                 uint64_t pcr_s_e:1;
1515                 uint64_t pcr_a_f:1;
1516                 uint64_t q2_s_e:1;
1517                 uint64_t q2_a_f:1;
1518                 uint64_t q3_s_e:1;
1519                 uint64_t q3_a_f:1;
1520                 uint64_t com_s_e:1;
1521                 uint64_t com_a_f:1;
1522                 uint64_t pnc_s_e:1;
1523                 uint64_t pnc_a_f:1;
1524                 uint64_t rwx_s_e:1;
1525                 uint64_t rdx_s_e:1;
1526                 uint64_t pcf_p_e:1;
1527                 uint64_t pcf_p_f:1;
1528                 uint64_t pdf_p_e:1;
1529                 uint64_t pdf_p_f:1;
1530                 uint64_t q1_s_e:1;
1531                 uint64_t q1_a_f:1;
1532                 uint64_t reserved_62_63:2;
1533 #endif
1534         } cn31xx;
1535         struct cvmx_npi_int_sum_s cn38xx;
1536         struct cvmx_npi_int_sum_cn38xxp2 {
1537 #ifdef __BIG_ENDIAN_BITFIELD
1538                 uint64_t reserved_42_63:22;
1539                 uint64_t iobdma:1;
1540                 uint64_t p_dperr:1;
1541                 uint64_t win_rto:1;
1542                 uint64_t i3_pperr:1;
1543                 uint64_t i2_pperr:1;
1544                 uint64_t i1_pperr:1;
1545                 uint64_t i0_pperr:1;
1546                 uint64_t p3_ptout:1;
1547                 uint64_t p2_ptout:1;
1548                 uint64_t p1_ptout:1;
1549                 uint64_t p0_ptout:1;
1550                 uint64_t p3_pperr:1;
1551                 uint64_t p2_pperr:1;
1552                 uint64_t p1_pperr:1;
1553                 uint64_t p0_pperr:1;
1554                 uint64_t g3_rtout:1;
1555                 uint64_t g2_rtout:1;
1556                 uint64_t g1_rtout:1;
1557                 uint64_t g0_rtout:1;
1558                 uint64_t p3_perr:1;
1559                 uint64_t p2_perr:1;
1560                 uint64_t p1_perr:1;
1561                 uint64_t p0_perr:1;
1562                 uint64_t p3_rtout:1;
1563                 uint64_t p2_rtout:1;
1564                 uint64_t p1_rtout:1;
1565                 uint64_t p0_rtout:1;
1566                 uint64_t i3_overf:1;
1567                 uint64_t i2_overf:1;
1568                 uint64_t i1_overf:1;
1569                 uint64_t i0_overf:1;
1570                 uint64_t i3_rtout:1;
1571                 uint64_t i2_rtout:1;
1572                 uint64_t i1_rtout:1;
1573                 uint64_t i0_rtout:1;
1574                 uint64_t po3_2sml:1;
1575                 uint64_t po2_2sml:1;
1576                 uint64_t po1_2sml:1;
1577                 uint64_t po0_2sml:1;
1578                 uint64_t pci_rsl:1;
1579                 uint64_t rml_wto:1;
1580                 uint64_t rml_rto:1;
1581 #else
1582                 uint64_t rml_rto:1;
1583                 uint64_t rml_wto:1;
1584                 uint64_t pci_rsl:1;
1585                 uint64_t po0_2sml:1;
1586                 uint64_t po1_2sml:1;
1587                 uint64_t po2_2sml:1;
1588                 uint64_t po3_2sml:1;
1589                 uint64_t i0_rtout:1;
1590                 uint64_t i1_rtout:1;
1591                 uint64_t i2_rtout:1;
1592                 uint64_t i3_rtout:1;
1593                 uint64_t i0_overf:1;
1594                 uint64_t i1_overf:1;
1595                 uint64_t i2_overf:1;
1596                 uint64_t i3_overf:1;
1597                 uint64_t p0_rtout:1;
1598                 uint64_t p1_rtout:1;
1599                 uint64_t p2_rtout:1;
1600                 uint64_t p3_rtout:1;
1601                 uint64_t p0_perr:1;
1602                 uint64_t p1_perr:1;
1603                 uint64_t p2_perr:1;
1604                 uint64_t p3_perr:1;
1605                 uint64_t g0_rtout:1;
1606                 uint64_t g1_rtout:1;
1607                 uint64_t g2_rtout:1;
1608                 uint64_t g3_rtout:1;
1609                 uint64_t p0_pperr:1;
1610                 uint64_t p1_pperr:1;
1611                 uint64_t p2_pperr:1;
1612                 uint64_t p3_pperr:1;
1613                 uint64_t p0_ptout:1;
1614                 uint64_t p1_ptout:1;
1615                 uint64_t p2_ptout:1;
1616                 uint64_t p3_ptout:1;
1617                 uint64_t i0_pperr:1;
1618                 uint64_t i1_pperr:1;
1619                 uint64_t i2_pperr:1;
1620                 uint64_t i3_pperr:1;
1621                 uint64_t win_rto:1;
1622                 uint64_t p_dperr:1;
1623                 uint64_t iobdma:1;
1624                 uint64_t reserved_42_63:22;
1625 #endif
1626         } cn38xxp2;
1627         struct cvmx_npi_int_sum_cn31xx cn50xx;
1628         struct cvmx_npi_int_sum_s cn58xx;
1629         struct cvmx_npi_int_sum_s cn58xxp1;
1630 };
1631
1632 union cvmx_npi_lowp_dbell {
1633         uint64_t u64;
1634         struct cvmx_npi_lowp_dbell_s {
1635 #ifdef __BIG_ENDIAN_BITFIELD
1636                 uint64_t reserved_16_63:48;
1637                 uint64_t dbell:16;
1638 #else
1639                 uint64_t dbell:16;
1640                 uint64_t reserved_16_63:48;
1641 #endif
1642         } s;
1643         struct cvmx_npi_lowp_dbell_s cn30xx;
1644         struct cvmx_npi_lowp_dbell_s cn31xx;
1645         struct cvmx_npi_lowp_dbell_s cn38xx;
1646         struct cvmx_npi_lowp_dbell_s cn38xxp2;
1647         struct cvmx_npi_lowp_dbell_s cn50xx;
1648         struct cvmx_npi_lowp_dbell_s cn58xx;
1649         struct cvmx_npi_lowp_dbell_s cn58xxp1;
1650 };
1651
1652 union cvmx_npi_lowp_ibuff_saddr {
1653         uint64_t u64;
1654         struct cvmx_npi_lowp_ibuff_saddr_s {
1655 #ifdef __BIG_ENDIAN_BITFIELD
1656                 uint64_t reserved_36_63:28;
1657                 uint64_t saddr:36;
1658 #else
1659                 uint64_t saddr:36;
1660                 uint64_t reserved_36_63:28;
1661 #endif
1662         } s;
1663         struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1664         struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1665         struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1666         struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1667         struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1668         struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1669         struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1670 };
1671
1672 union cvmx_npi_mem_access_subidx {
1673         uint64_t u64;
1674         struct cvmx_npi_mem_access_subidx_s {
1675 #ifdef __BIG_ENDIAN_BITFIELD
1676                 uint64_t reserved_38_63:26;
1677                 uint64_t shortl:1;
1678                 uint64_t nmerge:1;
1679                 uint64_t esr:2;
1680                 uint64_t esw:2;
1681                 uint64_t nsr:1;
1682                 uint64_t nsw:1;
1683                 uint64_t ror:1;
1684                 uint64_t row:1;
1685                 uint64_t ba:28;
1686 #else
1687                 uint64_t ba:28;
1688                 uint64_t row:1;
1689                 uint64_t ror:1;
1690                 uint64_t nsw:1;
1691                 uint64_t nsr:1;
1692                 uint64_t esw:2;
1693                 uint64_t esr:2;
1694                 uint64_t nmerge:1;
1695                 uint64_t shortl:1;
1696                 uint64_t reserved_38_63:26;
1697 #endif
1698         } s;
1699         struct cvmx_npi_mem_access_subidx_s cn30xx;
1700         struct cvmx_npi_mem_access_subidx_cn31xx {
1701 #ifdef __BIG_ENDIAN_BITFIELD
1702                 uint64_t reserved_36_63:28;
1703                 uint64_t esr:2;
1704                 uint64_t esw:2;
1705                 uint64_t nsr:1;
1706                 uint64_t nsw:1;
1707                 uint64_t ror:1;
1708                 uint64_t row:1;
1709                 uint64_t ba:28;
1710 #else
1711                 uint64_t ba:28;
1712                 uint64_t row:1;
1713                 uint64_t ror:1;
1714                 uint64_t nsw:1;
1715                 uint64_t nsr:1;
1716                 uint64_t esw:2;
1717                 uint64_t esr:2;
1718                 uint64_t reserved_36_63:28;
1719 #endif
1720         } cn31xx;
1721         struct cvmx_npi_mem_access_subidx_s cn38xx;
1722         struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1723         struct cvmx_npi_mem_access_subidx_s cn50xx;
1724         struct cvmx_npi_mem_access_subidx_s cn58xx;
1725         struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1726 };
1727
1728 union cvmx_npi_msi_rcv {
1729         uint64_t u64;
1730         struct cvmx_npi_msi_rcv_s {
1731 #ifdef __BIG_ENDIAN_BITFIELD
1732                 uint64_t int_vec:64;
1733 #else
1734                 uint64_t int_vec:64;
1735 #endif
1736         } s;
1737         struct cvmx_npi_msi_rcv_s cn30xx;
1738         struct cvmx_npi_msi_rcv_s cn31xx;
1739         struct cvmx_npi_msi_rcv_s cn38xx;
1740         struct cvmx_npi_msi_rcv_s cn38xxp2;
1741         struct cvmx_npi_msi_rcv_s cn50xx;
1742         struct cvmx_npi_msi_rcv_s cn58xx;
1743         struct cvmx_npi_msi_rcv_s cn58xxp1;
1744 };
1745
1746 union cvmx_npi_num_desc_outputx {
1747         uint64_t u64;
1748         struct cvmx_npi_num_desc_outputx_s {
1749 #ifdef __BIG_ENDIAN_BITFIELD
1750                 uint64_t reserved_32_63:32;
1751                 uint64_t size:32;
1752 #else
1753                 uint64_t size:32;
1754                 uint64_t reserved_32_63:32;
1755 #endif
1756         } s;
1757         struct cvmx_npi_num_desc_outputx_s cn30xx;
1758         struct cvmx_npi_num_desc_outputx_s cn31xx;
1759         struct cvmx_npi_num_desc_outputx_s cn38xx;
1760         struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1761         struct cvmx_npi_num_desc_outputx_s cn50xx;
1762         struct cvmx_npi_num_desc_outputx_s cn58xx;
1763         struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1764 };
1765
1766 union cvmx_npi_output_control {
1767         uint64_t u64;
1768         struct cvmx_npi_output_control_s {
1769 #ifdef __BIG_ENDIAN_BITFIELD
1770                 uint64_t reserved_49_63:15;
1771                 uint64_t pkt_rr:1;
1772                 uint64_t p3_bmode:1;
1773                 uint64_t p2_bmode:1;
1774                 uint64_t p1_bmode:1;
1775                 uint64_t p0_bmode:1;
1776                 uint64_t o3_es:2;
1777                 uint64_t o3_ns:1;
1778                 uint64_t o3_ro:1;
1779                 uint64_t o2_es:2;
1780                 uint64_t o2_ns:1;
1781                 uint64_t o2_ro:1;
1782                 uint64_t o1_es:2;
1783                 uint64_t o1_ns:1;
1784                 uint64_t o1_ro:1;
1785                 uint64_t o0_es:2;
1786                 uint64_t o0_ns:1;
1787                 uint64_t o0_ro:1;
1788                 uint64_t o3_csrm:1;
1789                 uint64_t o2_csrm:1;
1790                 uint64_t o1_csrm:1;
1791                 uint64_t o0_csrm:1;
1792                 uint64_t reserved_20_23:4;
1793                 uint64_t iptr_o3:1;
1794                 uint64_t iptr_o2:1;
1795                 uint64_t iptr_o1:1;
1796                 uint64_t iptr_o0:1;
1797                 uint64_t esr_sl3:2;
1798                 uint64_t nsr_sl3:1;
1799                 uint64_t ror_sl3:1;
1800                 uint64_t esr_sl2:2;
1801                 uint64_t nsr_sl2:1;
1802                 uint64_t ror_sl2:1;
1803                 uint64_t esr_sl1:2;
1804                 uint64_t nsr_sl1:1;
1805                 uint64_t ror_sl1:1;
1806                 uint64_t esr_sl0:2;
1807                 uint64_t nsr_sl0:1;
1808                 uint64_t ror_sl0:1;
1809 #else
1810                 uint64_t ror_sl0:1;
1811                 uint64_t nsr_sl0:1;
1812                 uint64_t esr_sl0:2;
1813                 uint64_t ror_sl1:1;
1814                 uint64_t nsr_sl1:1;
1815                 uint64_t esr_sl1:2;
1816                 uint64_t ror_sl2:1;
1817                 uint64_t nsr_sl2:1;
1818                 uint64_t esr_sl2:2;
1819                 uint64_t ror_sl3:1;
1820                 uint64_t nsr_sl3:1;
1821                 uint64_t esr_sl3:2;
1822                 uint64_t iptr_o0:1;
1823                 uint64_t iptr_o1:1;
1824                 uint64_t iptr_o2:1;
1825                 uint64_t iptr_o3:1;
1826                 uint64_t reserved_20_23:4;
1827                 uint64_t o0_csrm:1;
1828                 uint64_t o1_csrm:1;
1829                 uint64_t o2_csrm:1;
1830                 uint64_t o3_csrm:1;
1831                 uint64_t o0_ro:1;
1832                 uint64_t o0_ns:1;
1833                 uint64_t o0_es:2;
1834                 uint64_t o1_ro:1;
1835                 uint64_t o1_ns:1;
1836                 uint64_t o1_es:2;
1837                 uint64_t o2_ro:1;
1838                 uint64_t o2_ns:1;
1839                 uint64_t o2_es:2;
1840                 uint64_t o3_ro:1;
1841                 uint64_t o3_ns:1;
1842                 uint64_t o3_es:2;
1843                 uint64_t p0_bmode:1;
1844                 uint64_t p1_bmode:1;
1845                 uint64_t p2_bmode:1;
1846                 uint64_t p3_bmode:1;
1847                 uint64_t pkt_rr:1;
1848                 uint64_t reserved_49_63:15;
1849 #endif
1850         } s;
1851         struct cvmx_npi_output_control_cn30xx {
1852 #ifdef __BIG_ENDIAN_BITFIELD
1853                 uint64_t reserved_45_63:19;
1854                 uint64_t p0_bmode:1;
1855                 uint64_t reserved_32_43:12;
1856                 uint64_t o0_es:2;
1857                 uint64_t o0_ns:1;
1858                 uint64_t o0_ro:1;
1859                 uint64_t reserved_25_27:3;
1860                 uint64_t o0_csrm:1;
1861                 uint64_t reserved_17_23:7;
1862                 uint64_t iptr_o0:1;
1863                 uint64_t reserved_4_15:12;
1864                 uint64_t esr_sl0:2;
1865                 uint64_t nsr_sl0:1;
1866                 uint64_t ror_sl0:1;
1867 #else
1868                 uint64_t ror_sl0:1;
1869                 uint64_t nsr_sl0:1;
1870                 uint64_t esr_sl0:2;
1871                 uint64_t reserved_4_15:12;
1872                 uint64_t iptr_o0:1;
1873                 uint64_t reserved_17_23:7;
1874                 uint64_t o0_csrm:1;
1875                 uint64_t reserved_25_27:3;
1876                 uint64_t o0_ro:1;
1877                 uint64_t o0_ns:1;
1878                 uint64_t o0_es:2;
1879                 uint64_t reserved_32_43:12;
1880                 uint64_t p0_bmode:1;
1881                 uint64_t reserved_45_63:19;
1882 #endif
1883         } cn30xx;
1884         struct cvmx_npi_output_control_cn31xx {
1885 #ifdef __BIG_ENDIAN_BITFIELD
1886                 uint64_t reserved_46_63:18;
1887                 uint64_t p1_bmode:1;
1888                 uint64_t p0_bmode:1;
1889                 uint64_t reserved_36_43:8;
1890                 uint64_t o1_es:2;
1891                 uint64_t o1_ns:1;
1892                 uint64_t o1_ro:1;
1893                 uint64_t o0_es:2;
1894                 uint64_t o0_ns:1;
1895                 uint64_t o0_ro:1;
1896                 uint64_t reserved_26_27:2;
1897                 uint64_t o1_csrm:1;
1898                 uint64_t o0_csrm:1;
1899                 uint64_t reserved_18_23:6;
1900                 uint64_t iptr_o1:1;
1901                 uint64_t iptr_o0:1;
1902                 uint64_t reserved_8_15:8;
1903                 uint64_t esr_sl1:2;
1904                 uint64_t nsr_sl1:1;
1905                 uint64_t ror_sl1:1;
1906                 uint64_t esr_sl0:2;
1907                 uint64_t nsr_sl0:1;
1908                 uint64_t ror_sl0:1;
1909 #else
1910                 uint64_t ror_sl0:1;
1911                 uint64_t nsr_sl0:1;
1912                 uint64_t esr_sl0:2;
1913                 uint64_t ror_sl1:1;
1914                 uint64_t nsr_sl1:1;
1915                 uint64_t esr_sl1:2;
1916                 uint64_t reserved_8_15:8;
1917                 uint64_t iptr_o0:1;
1918                 uint64_t iptr_o1:1;
1919                 uint64_t reserved_18_23:6;
1920                 uint64_t o0_csrm:1;
1921                 uint64_t o1_csrm:1;
1922                 uint64_t reserved_26_27:2;
1923                 uint64_t o0_ro:1;
1924                 uint64_t o0_ns:1;
1925                 uint64_t o0_es:2;
1926                 uint64_t o1_ro:1;
1927                 uint64_t o1_ns:1;
1928                 uint64_t o1_es:2;
1929                 uint64_t reserved_36_43:8;
1930                 uint64_t p0_bmode:1;
1931                 uint64_t p1_bmode:1;
1932                 uint64_t reserved_46_63:18;
1933 #endif
1934         } cn31xx;
1935         struct cvmx_npi_output_control_s cn38xx;
1936         struct cvmx_npi_output_control_cn38xxp2 {
1937 #ifdef __BIG_ENDIAN_BITFIELD
1938                 uint64_t reserved_48_63:16;
1939                 uint64_t p3_bmode:1;
1940                 uint64_t p2_bmode:1;
1941                 uint64_t p1_bmode:1;
1942                 uint64_t p0_bmode:1;
1943                 uint64_t o3_es:2;
1944                 uint64_t o3_ns:1;
1945                 uint64_t o3_ro:1;
1946                 uint64_t o2_es:2;
1947                 uint64_t o2_ns:1;
1948                 uint64_t o2_ro:1;
1949                 uint64_t o1_es:2;
1950                 uint64_t o1_ns:1;
1951                 uint64_t o1_ro:1;
1952                 uint64_t o0_es:2;
1953                 uint64_t o0_ns:1;
1954                 uint64_t o0_ro:1;
1955                 uint64_t o3_csrm:1;
1956                 uint64_t o2_csrm:1;
1957                 uint64_t o1_csrm:1;
1958                 uint64_t o0_csrm:1;
1959                 uint64_t reserved_20_23:4;
1960                 uint64_t iptr_o3:1;
1961                 uint64_t iptr_o2:1;
1962                 uint64_t iptr_o1:1;
1963                 uint64_t iptr_o0:1;
1964                 uint64_t esr_sl3:2;
1965                 uint64_t nsr_sl3:1;
1966                 uint64_t ror_sl3:1;
1967                 uint64_t esr_sl2:2;
1968                 uint64_t nsr_sl2:1;
1969                 uint64_t ror_sl2:1;
1970                 uint64_t esr_sl1:2;
1971                 uint64_t nsr_sl1:1;
1972                 uint64_t ror_sl1:1;
1973                 uint64_t esr_sl0:2;
1974                 uint64_t nsr_sl0:1;
1975                 uint64_t ror_sl0:1;
1976 #else
1977                 uint64_t ror_sl0:1;
1978                 uint64_t nsr_sl0:1;
1979                 uint64_t esr_sl0:2;
1980                 uint64_t ror_sl1:1;
1981                 uint64_t nsr_sl1:1;
1982                 uint64_t esr_sl1:2;
1983                 uint64_t ror_sl2:1;
1984                 uint64_t nsr_sl2:1;
1985                 uint64_t esr_sl2:2;
1986                 uint64_t ror_sl3:1;
1987                 uint64_t nsr_sl3:1;
1988                 uint64_t esr_sl3:2;
1989                 uint64_t iptr_o0:1;
1990                 uint64_t iptr_o1:1;
1991                 uint64_t iptr_o2:1;
1992                 uint64_t iptr_o3:1;
1993                 uint64_t reserved_20_23:4;
1994                 uint64_t o0_csrm:1;
1995                 uint64_t o1_csrm:1;
1996                 uint64_t o2_csrm:1;
1997                 uint64_t o3_csrm:1;
1998                 uint64_t o0_ro:1;
1999                 uint64_t o0_ns:1;
2000                 uint64_t o0_es:2;
2001                 uint64_t o1_ro:1;
2002                 uint64_t o1_ns:1;
2003                 uint64_t o1_es:2;
2004                 uint64_t o2_ro:1;
2005                 uint64_t o2_ns:1;
2006                 uint64_t o2_es:2;
2007                 uint64_t o3_ro:1;
2008                 uint64_t o3_ns:1;
2009                 uint64_t o3_es:2;
2010                 uint64_t p0_bmode:1;
2011                 uint64_t p1_bmode:1;
2012                 uint64_t p2_bmode:1;
2013                 uint64_t p3_bmode:1;
2014                 uint64_t reserved_48_63:16;
2015 #endif
2016         } cn38xxp2;
2017         struct cvmx_npi_output_control_cn50xx {
2018 #ifdef __BIG_ENDIAN_BITFIELD
2019                 uint64_t reserved_49_63:15;
2020                 uint64_t pkt_rr:1;
2021                 uint64_t reserved_46_47:2;
2022                 uint64_t p1_bmode:1;
2023                 uint64_t p0_bmode:1;
2024                 uint64_t reserved_36_43:8;
2025                 uint64_t o1_es:2;
2026                 uint64_t o1_ns:1;
2027                 uint64_t o1_ro:1;
2028                 uint64_t o0_es:2;
2029                 uint64_t o0_ns:1;
2030                 uint64_t o0_ro:1;
2031                 uint64_t reserved_26_27:2;
2032                 uint64_t o1_csrm:1;
2033                 uint64_t o0_csrm:1;
2034                 uint64_t reserved_18_23:6;
2035                 uint64_t iptr_o1:1;
2036                 uint64_t iptr_o0:1;
2037                 uint64_t reserved_8_15:8;
2038                 uint64_t esr_sl1:2;
2039                 uint64_t nsr_sl1:1;
2040                 uint64_t ror_sl1:1;
2041                 uint64_t esr_sl0:2;
2042                 uint64_t nsr_sl0:1;
2043                 uint64_t ror_sl0:1;
2044 #else
2045                 uint64_t ror_sl0:1;
2046                 uint64_t nsr_sl0:1;
2047                 uint64_t esr_sl0:2;
2048                 uint64_t ror_sl1:1;
2049                 uint64_t nsr_sl1:1;
2050                 uint64_t esr_sl1:2;
2051                 uint64_t reserved_8_15:8;
2052                 uint64_t iptr_o0:1;
2053                 uint64_t iptr_o1:1;
2054                 uint64_t reserved_18_23:6;
2055                 uint64_t o0_csrm:1;
2056                 uint64_t o1_csrm:1;
2057                 uint64_t reserved_26_27:2;
2058                 uint64_t o0_ro:1;
2059                 uint64_t o0_ns:1;
2060                 uint64_t o0_es:2;
2061                 uint64_t o1_ro:1;
2062                 uint64_t o1_ns:1;
2063                 uint64_t o1_es:2;
2064                 uint64_t reserved_36_43:8;
2065                 uint64_t p0_bmode:1;
2066                 uint64_t p1_bmode:1;
2067                 uint64_t reserved_46_47:2;
2068                 uint64_t pkt_rr:1;
2069                 uint64_t reserved_49_63:15;
2070 #endif
2071         } cn50xx;
2072         struct cvmx_npi_output_control_s cn58xx;
2073         struct cvmx_npi_output_control_s cn58xxp1;
2074 };
2075
2076 union cvmx_npi_px_dbpair_addr {
2077         uint64_t u64;
2078         struct cvmx_npi_px_dbpair_addr_s {
2079 #ifdef __BIG_ENDIAN_BITFIELD
2080                 uint64_t reserved_63_63:1;
2081                 uint64_t state:2;
2082                 uint64_t naddr:61;
2083 #else
2084                 uint64_t naddr:61;
2085                 uint64_t state:2;
2086                 uint64_t reserved_63_63:1;
2087 #endif
2088         } s;
2089         struct cvmx_npi_px_dbpair_addr_s cn30xx;
2090         struct cvmx_npi_px_dbpair_addr_s cn31xx;
2091         struct cvmx_npi_px_dbpair_addr_s cn38xx;
2092         struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
2093         struct cvmx_npi_px_dbpair_addr_s cn50xx;
2094         struct cvmx_npi_px_dbpair_addr_s cn58xx;
2095         struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
2096 };
2097
2098 union cvmx_npi_px_instr_addr {
2099         uint64_t u64;
2100         struct cvmx_npi_px_instr_addr_s {
2101 #ifdef __BIG_ENDIAN_BITFIELD
2102                 uint64_t state:3;
2103                 uint64_t naddr:61;
2104 #else
2105                 uint64_t naddr:61;
2106                 uint64_t state:3;
2107 #endif
2108         } s;
2109         struct cvmx_npi_px_instr_addr_s cn30xx;
2110         struct cvmx_npi_px_instr_addr_s cn31xx;
2111         struct cvmx_npi_px_instr_addr_s cn38xx;
2112         struct cvmx_npi_px_instr_addr_s cn38xxp2;
2113         struct cvmx_npi_px_instr_addr_s cn50xx;
2114         struct cvmx_npi_px_instr_addr_s cn58xx;
2115         struct cvmx_npi_px_instr_addr_s cn58xxp1;
2116 };
2117
2118 union cvmx_npi_px_instr_cnts {
2119         uint64_t u64;
2120         struct cvmx_npi_px_instr_cnts_s {
2121 #ifdef __BIG_ENDIAN_BITFIELD
2122                 uint64_t reserved_38_63:26;
2123                 uint64_t fcnt:6;
2124                 uint64_t avail:32;
2125 #else
2126                 uint64_t avail:32;
2127                 uint64_t fcnt:6;
2128                 uint64_t reserved_38_63:26;
2129 #endif
2130         } s;
2131         struct cvmx_npi_px_instr_cnts_s cn30xx;
2132         struct cvmx_npi_px_instr_cnts_s cn31xx;
2133         struct cvmx_npi_px_instr_cnts_s cn38xx;
2134         struct cvmx_npi_px_instr_cnts_s cn38xxp2;
2135         struct cvmx_npi_px_instr_cnts_s cn50xx;
2136         struct cvmx_npi_px_instr_cnts_s cn58xx;
2137         struct cvmx_npi_px_instr_cnts_s cn58xxp1;
2138 };
2139
2140 union cvmx_npi_px_pair_cnts {
2141         uint64_t u64;
2142         struct cvmx_npi_px_pair_cnts_s {
2143 #ifdef __BIG_ENDIAN_BITFIELD
2144                 uint64_t reserved_37_63:27;
2145                 uint64_t fcnt:5;
2146                 uint64_t avail:32;
2147 #else
2148                 uint64_t avail:32;
2149                 uint64_t fcnt:5;
2150                 uint64_t reserved_37_63:27;
2151 #endif
2152         } s;
2153         struct cvmx_npi_px_pair_cnts_s cn30xx;
2154         struct cvmx_npi_px_pair_cnts_s cn31xx;
2155         struct cvmx_npi_px_pair_cnts_s cn38xx;
2156         struct cvmx_npi_px_pair_cnts_s cn38xxp2;
2157         struct cvmx_npi_px_pair_cnts_s cn50xx;
2158         struct cvmx_npi_px_pair_cnts_s cn58xx;
2159         struct cvmx_npi_px_pair_cnts_s cn58xxp1;
2160 };
2161
2162 union cvmx_npi_pci_burst_size {
2163         uint64_t u64;
2164         struct cvmx_npi_pci_burst_size_s {
2165 #ifdef __BIG_ENDIAN_BITFIELD
2166                 uint64_t reserved_14_63:50;
2167                 uint64_t wr_brst:7;
2168                 uint64_t rd_brst:7;
2169 #else
2170                 uint64_t rd_brst:7;
2171                 uint64_t wr_brst:7;
2172                 uint64_t reserved_14_63:50;
2173 #endif
2174         } s;
2175         struct cvmx_npi_pci_burst_size_s cn30xx;
2176         struct cvmx_npi_pci_burst_size_s cn31xx;
2177         struct cvmx_npi_pci_burst_size_s cn38xx;
2178         struct cvmx_npi_pci_burst_size_s cn38xxp2;
2179         struct cvmx_npi_pci_burst_size_s cn50xx;
2180         struct cvmx_npi_pci_burst_size_s cn58xx;
2181         struct cvmx_npi_pci_burst_size_s cn58xxp1;
2182 };
2183
2184 union cvmx_npi_pci_int_arb_cfg {
2185         uint64_t u64;
2186         struct cvmx_npi_pci_int_arb_cfg_s {
2187 #ifdef __BIG_ENDIAN_BITFIELD
2188                 uint64_t reserved_13_63:51;
2189                 uint64_t hostmode:1;
2190                 uint64_t pci_ovr:4;
2191                 uint64_t reserved_5_7:3;
2192                 uint64_t en:1;
2193                 uint64_t park_mod:1;
2194                 uint64_t park_dev:3;
2195 #else
2196                 uint64_t park_dev:3;
2197                 uint64_t park_mod:1;
2198                 uint64_t en:1;
2199                 uint64_t reserved_5_7:3;
2200                 uint64_t pci_ovr:4;
2201                 uint64_t hostmode:1;
2202                 uint64_t reserved_13_63:51;
2203 #endif
2204         } s;
2205         struct cvmx_npi_pci_int_arb_cfg_cn30xx {
2206 #ifdef __BIG_ENDIAN_BITFIELD
2207                 uint64_t reserved_5_63:59;
2208                 uint64_t en:1;
2209                 uint64_t park_mod:1;
2210                 uint64_t park_dev:3;
2211 #else
2212                 uint64_t park_dev:3;
2213                 uint64_t park_mod:1;
2214                 uint64_t en:1;
2215                 uint64_t reserved_5_63:59;
2216 #endif
2217         } cn30xx;
2218         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
2219         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
2220         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
2221         struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
2222         struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
2223         struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
2224 };
2225
2226 union cvmx_npi_pci_read_cmd {
2227         uint64_t u64;
2228         struct cvmx_npi_pci_read_cmd_s {
2229 #ifdef __BIG_ENDIAN_BITFIELD
2230                 uint64_t reserved_11_63:53;
2231                 uint64_t cmd_size:11;
2232 #else
2233                 uint64_t cmd_size:11;
2234                 uint64_t reserved_11_63:53;
2235 #endif
2236         } s;
2237         struct cvmx_npi_pci_read_cmd_s cn30xx;
2238         struct cvmx_npi_pci_read_cmd_s cn31xx;
2239         struct cvmx_npi_pci_read_cmd_s cn38xx;
2240         struct cvmx_npi_pci_read_cmd_s cn38xxp2;
2241         struct cvmx_npi_pci_read_cmd_s cn50xx;
2242         struct cvmx_npi_pci_read_cmd_s cn58xx;
2243         struct cvmx_npi_pci_read_cmd_s cn58xxp1;
2244 };
2245
2246 union cvmx_npi_port32_instr_hdr {
2247         uint64_t u64;
2248         struct cvmx_npi_port32_instr_hdr_s {
2249 #ifdef __BIG_ENDIAN_BITFIELD
2250                 uint64_t reserved_44_63:20;
2251                 uint64_t pbp:1;
2252                 uint64_t rsv_f:5;
2253                 uint64_t rparmode:2;
2254                 uint64_t rsv_e:1;
2255                 uint64_t rskp_len:7;
2256                 uint64_t rsv_d:6;
2257                 uint64_t use_ihdr:1;
2258                 uint64_t rsv_c:5;
2259                 uint64_t par_mode:2;
2260                 uint64_t rsv_b:1;
2261                 uint64_t skp_len:7;
2262                 uint64_t rsv_a:6;
2263 #else
2264                 uint64_t rsv_a:6;
2265                 uint64_t skp_len:7;
2266                 uint64_t rsv_b:1;
2267                 uint64_t par_mode:2;
2268                 uint64_t rsv_c:5;
2269                 uint64_t use_ihdr:1;
2270                 uint64_t rsv_d:6;
2271                 uint64_t rskp_len:7;
2272                 uint64_t rsv_e:1;
2273                 uint64_t rparmode:2;
2274                 uint64_t rsv_f:5;
2275                 uint64_t pbp:1;
2276                 uint64_t reserved_44_63:20;
2277 #endif
2278         } s;
2279         struct cvmx_npi_port32_instr_hdr_s cn30xx;
2280         struct cvmx_npi_port32_instr_hdr_s cn31xx;
2281         struct cvmx_npi_port32_instr_hdr_s cn38xx;
2282         struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
2283         struct cvmx_npi_port32_instr_hdr_s cn50xx;
2284         struct cvmx_npi_port32_instr_hdr_s cn58xx;
2285         struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
2286 };
2287
2288 union cvmx_npi_port33_instr_hdr {
2289         uint64_t u64;
2290         struct cvmx_npi_port33_instr_hdr_s {
2291 #ifdef __BIG_ENDIAN_BITFIELD
2292                 uint64_t reserved_44_63:20;
2293                 uint64_t pbp:1;
2294                 uint64_t rsv_f:5;
2295                 uint64_t rparmode:2;
2296                 uint64_t rsv_e:1;
2297                 uint64_t rskp_len:7;
2298                 uint64_t rsv_d:6;
2299                 uint64_t use_ihdr:1;
2300                 uint64_t rsv_c:5;
2301                 uint64_t par_mode:2;
2302                 uint64_t rsv_b:1;
2303                 uint64_t skp_len:7;
2304                 uint64_t rsv_a:6;
2305 #else
2306                 uint64_t rsv_a:6;
2307                 uint64_t skp_len:7;
2308                 uint64_t rsv_b:1;
2309                 uint64_t par_mode:2;
2310                 uint64_t rsv_c:5;
2311                 uint64_t use_ihdr:1;
2312                 uint64_t rsv_d:6;
2313                 uint64_t rskp_len:7;
2314                 uint64_t rsv_e:1;
2315                 uint64_t rparmode:2;
2316                 uint64_t rsv_f:5;
2317                 uint64_t pbp:1;
2318                 uint64_t reserved_44_63:20;
2319 #endif
2320         } s;
2321         struct cvmx_npi_port33_instr_hdr_s cn31xx;
2322         struct cvmx_npi_port33_instr_hdr_s cn38xx;
2323         struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
2324         struct cvmx_npi_port33_instr_hdr_s cn50xx;
2325         struct cvmx_npi_port33_instr_hdr_s cn58xx;
2326         struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
2327 };
2328
2329 union cvmx_npi_port34_instr_hdr {
2330         uint64_t u64;
2331         struct cvmx_npi_port34_instr_hdr_s {
2332 #ifdef __BIG_ENDIAN_BITFIELD
2333                 uint64_t reserved_44_63:20;
2334                 uint64_t pbp:1;
2335                 uint64_t rsv_f:5;
2336                 uint64_t rparmode:2;
2337                 uint64_t rsv_e:1;
2338                 uint64_t rskp_len:7;
2339                 uint64_t rsv_d:6;
2340                 uint64_t use_ihdr:1;
2341                 uint64_t rsv_c:5;
2342                 uint64_t par_mode:2;
2343                 uint64_t rsv_b:1;
2344                 uint64_t skp_len:7;
2345                 uint64_t rsv_a:6;
2346 #else
2347                 uint64_t rsv_a:6;
2348                 uint64_t skp_len:7;
2349                 uint64_t rsv_b:1;
2350                 uint64_t par_mode:2;
2351                 uint64_t rsv_c:5;
2352                 uint64_t use_ihdr:1;
2353                 uint64_t rsv_d:6;
2354                 uint64_t rskp_len:7;
2355                 uint64_t rsv_e:1;
2356                 uint64_t rparmode:2;
2357                 uint64_t rsv_f:5;
2358                 uint64_t pbp:1;
2359                 uint64_t reserved_44_63:20;
2360 #endif
2361         } s;
2362         struct cvmx_npi_port34_instr_hdr_s cn38xx;
2363         struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
2364         struct cvmx_npi_port34_instr_hdr_s cn58xx;
2365         struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
2366 };
2367
2368 union cvmx_npi_port35_instr_hdr {
2369         uint64_t u64;
2370         struct cvmx_npi_port35_instr_hdr_s {
2371 #ifdef __BIG_ENDIAN_BITFIELD
2372                 uint64_t reserved_44_63:20;
2373                 uint64_t pbp:1;
2374                 uint64_t rsv_f:5;
2375                 uint64_t rparmode:2;
2376                 uint64_t rsv_e:1;
2377                 uint64_t rskp_len:7;
2378                 uint64_t rsv_d:6;
2379                 uint64_t use_ihdr:1;
2380                 uint64_t rsv_c:5;
2381                 uint64_t par_mode:2;
2382                 uint64_t rsv_b:1;
2383                 uint64_t skp_len:7;
2384                 uint64_t rsv_a:6;
2385 #else
2386                 uint64_t rsv_a:6;
2387                 uint64_t skp_len:7;
2388                 uint64_t rsv_b:1;
2389                 uint64_t par_mode:2;
2390                 uint64_t rsv_c:5;
2391                 uint64_t use_ihdr:1;
2392                 uint64_t rsv_d:6;
2393                 uint64_t rskp_len:7;
2394                 uint64_t rsv_e:1;
2395                 uint64_t rparmode:2;
2396                 uint64_t rsv_f:5;
2397                 uint64_t pbp:1;
2398                 uint64_t reserved_44_63:20;
2399 #endif
2400         } s;
2401         struct cvmx_npi_port35_instr_hdr_s cn38xx;
2402         struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
2403         struct cvmx_npi_port35_instr_hdr_s cn58xx;
2404         struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
2405 };
2406
2407 union cvmx_npi_port_bp_control {
2408         uint64_t u64;
2409         struct cvmx_npi_port_bp_control_s {
2410 #ifdef __BIG_ENDIAN_BITFIELD
2411                 uint64_t reserved_8_63:56;
2412                 uint64_t bp_on:4;
2413                 uint64_t enb:4;
2414 #else
2415                 uint64_t enb:4;
2416                 uint64_t bp_on:4;
2417                 uint64_t reserved_8_63:56;
2418 #endif
2419         } s;
2420         struct cvmx_npi_port_bp_control_s cn30xx;
2421         struct cvmx_npi_port_bp_control_s cn31xx;
2422         struct cvmx_npi_port_bp_control_s cn38xx;
2423         struct cvmx_npi_port_bp_control_s cn38xxp2;
2424         struct cvmx_npi_port_bp_control_s cn50xx;
2425         struct cvmx_npi_port_bp_control_s cn58xx;
2426         struct cvmx_npi_port_bp_control_s cn58xxp1;
2427 };
2428
2429 union cvmx_npi_rsl_int_blocks {
2430         uint64_t u64;
2431         struct cvmx_npi_rsl_int_blocks_s {
2432 #ifdef __BIG_ENDIAN_BITFIELD
2433                 uint64_t reserved_32_63:32;
2434                 uint64_t rint_31:1;
2435                 uint64_t iob:1;
2436                 uint64_t reserved_28_29:2;
2437                 uint64_t rint_27:1;
2438                 uint64_t rint_26:1;
2439                 uint64_t rint_25:1;
2440                 uint64_t rint_24:1;
2441                 uint64_t asx1:1;
2442                 uint64_t asx0:1;
2443                 uint64_t rint_21:1;
2444                 uint64_t pip:1;
2445                 uint64_t spx1:1;
2446                 uint64_t spx0:1;
2447                 uint64_t lmc:1;
2448                 uint64_t l2c:1;
2449                 uint64_t rint_15:1;
2450                 uint64_t reserved_13_14:2;
2451                 uint64_t pow:1;
2452                 uint64_t tim:1;
2453                 uint64_t pko:1;
2454                 uint64_t ipd:1;
2455                 uint64_t rint_8:1;
2456                 uint64_t zip:1;
2457                 uint64_t dfa:1;
2458                 uint64_t fpa:1;
2459                 uint64_t key:1;
2460                 uint64_t npi:1;
2461                 uint64_t gmx1:1;
2462                 uint64_t gmx0:1;
2463                 uint64_t mio:1;
2464 #else
2465                 uint64_t mio:1;
2466                 uint64_t gmx0:1;
2467                 uint64_t gmx1:1;
2468                 uint64_t npi:1;
2469                 uint64_t key:1;
2470                 uint64_t fpa:1;
2471                 uint64_t dfa:1;
2472                 uint64_t zip:1;
2473                 uint64_t rint_8:1;
2474                 uint64_t ipd:1;
2475                 uint64_t pko:1;
2476                 uint64_t tim:1;
2477                 uint64_t pow:1;
2478                 uint64_t reserved_13_14:2;
2479                 uint64_t rint_15:1;
2480                 uint64_t l2c:1;
2481                 uint64_t lmc:1;
2482                 uint64_t spx0:1;
2483                 uint64_t spx1:1;
2484                 uint64_t pip:1;
2485                 uint64_t rint_21:1;
2486                 uint64_t asx0:1;
2487                 uint64_t asx1:1;
2488                 uint64_t rint_24:1;
2489                 uint64_t rint_25:1;
2490                 uint64_t rint_26:1;
2491                 uint64_t rint_27:1;
2492                 uint64_t reserved_28_29:2;
2493                 uint64_t iob:1;
2494                 uint64_t rint_31:1;
2495                 uint64_t reserved_32_63:32;
2496 #endif
2497         } s;
2498         struct cvmx_npi_rsl_int_blocks_cn30xx {
2499 #ifdef __BIG_ENDIAN_BITFIELD
2500                 uint64_t reserved_32_63:32;
2501                 uint64_t rint_31:1;
2502                 uint64_t iob:1;
2503                 uint64_t rint_29:1;
2504                 uint64_t rint_28:1;
2505                 uint64_t rint_27:1;
2506                 uint64_t rint_26:1;
2507                 uint64_t rint_25:1;
2508                 uint64_t rint_24:1;
2509                 uint64_t asx1:1;
2510                 uint64_t asx0:1;
2511                 uint64_t rint_21:1;
2512                 uint64_t pip:1;
2513                 uint64_t spx1:1;
2514                 uint64_t spx0:1;
2515                 uint64_t lmc:1;
2516                 uint64_t l2c:1;
2517                 uint64_t rint_15:1;
2518                 uint64_t rint_14:1;
2519                 uint64_t usb:1;
2520                 uint64_t pow:1;
2521                 uint64_t tim:1;
2522                 uint64_t pko:1;
2523                 uint64_t ipd:1;
2524                 uint64_t rint_8:1;
2525                 uint64_t zip:1;
2526                 uint64_t dfa:1;
2527                 uint64_t fpa:1;
2528                 uint64_t key:1;
2529                 uint64_t npi:1;
2530                 uint64_t gmx1:1;
2531                 uint64_t gmx0:1;
2532                 uint64_t mio:1;
2533 #else
2534                 uint64_t mio:1;
2535                 uint64_t gmx0:1;
2536                 uint64_t gmx1:1;
2537                 uint64_t npi:1;
2538                 uint64_t key:1;
2539                 uint64_t fpa:1;
2540                 uint64_t dfa:1;
2541                 uint64_t zip:1;
2542                 uint64_t rint_8:1;
2543                 uint64_t ipd:1;
2544                 uint64_t pko:1;
2545                 uint64_t tim:1;
2546                 uint64_t pow:1;
2547                 uint64_t usb:1;
2548                 uint64_t rint_14:1;
2549                 uint64_t rint_15:1;
2550                 uint64_t l2c:1;
2551                 uint64_t lmc:1;
2552                 uint64_t spx0:1;
2553                 uint64_t spx1:1;
2554                 uint64_t pip:1;
2555                 uint64_t rint_21:1;
2556                 uint64_t asx0:1;
2557                 uint64_t asx1:1;
2558                 uint64_t rint_24:1;
2559                 uint64_t rint_25:1;
2560                 uint64_t rint_26:1;
2561                 uint64_t rint_27:1;
2562                 uint64_t rint_28:1;
2563                 uint64_t rint_29:1;
2564                 uint64_t iob:1;
2565                 uint64_t rint_31:1;
2566                 uint64_t reserved_32_63:32;
2567 #endif
2568         } cn30xx;
2569         struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
2570         struct cvmx_npi_rsl_int_blocks_cn38xx {
2571 #ifdef __BIG_ENDIAN_BITFIELD
2572                 uint64_t reserved_32_63:32;
2573                 uint64_t rint_31:1;
2574                 uint64_t iob:1;
2575                 uint64_t rint_29:1;
2576                 uint64_t rint_28:1;
2577                 uint64_t rint_27:1;
2578                 uint64_t rint_26:1;
2579                 uint64_t rint_25:1;
2580                 uint64_t rint_24:1;
2581                 uint64_t asx1:1;
2582                 uint64_t asx0:1;
2583                 uint64_t rint_21:1;
2584                 uint64_t pip:1;
2585                 uint64_t spx1:1;
2586                 uint64_t spx0:1;
2587                 uint64_t lmc:1;
2588                 uint64_t l2c:1;
2589                 uint64_t rint_15:1;
2590                 uint64_t rint_14:1;
2591                 uint64_t rint_13:1;
2592                 uint64_t pow:1;
2593                 uint64_t tim:1;
2594                 uint64_t pko:1;
2595                 uint64_t ipd:1;
2596                 uint64_t rint_8:1;
2597                 uint64_t zip:1;
2598                 uint64_t dfa:1;
2599                 uint64_t fpa:1;
2600                 uint64_t key:1;
2601                 uint64_t npi:1;
2602                 uint64_t gmx1:1;
2603                 uint64_t gmx0:1;
2604                 uint64_t mio:1;
2605 #else
2606                 uint64_t mio:1;
2607                 uint64_t gmx0:1;
2608                 uint64_t gmx1:1;
2609                 uint64_t npi:1;
2610                 uint64_t key:1;
2611                 uint64_t fpa:1;
2612                 uint64_t dfa:1;
2613                 uint64_t zip:1;
2614                 uint64_t rint_8:1;
2615                 uint64_t ipd:1;
2616                 uint64_t pko:1;
2617                 uint64_t tim:1;
2618                 uint64_t pow:1;
2619                 uint64_t rint_13:1;
2620                 uint64_t rint_14:1;
2621                 uint64_t rint_15:1;
2622                 uint64_t l2c:1;
2623                 uint64_t lmc:1;
2624                 uint64_t spx0:1;
2625                 uint64_t spx1:1;
2626                 uint64_t pip:1;
2627                 uint64_t rint_21:1;
2628                 uint64_t asx0:1;
2629                 uint64_t asx1:1;
2630                 uint64_t rint_24:1;
2631                 uint64_t rint_25:1;
2632                 uint64_t rint_26:1;
2633                 uint64_t rint_27:1;
2634                 uint64_t rint_28:1;
2635                 uint64_t rint_29:1;
2636                 uint64_t iob:1;
2637                 uint64_t rint_31:1;
2638                 uint64_t reserved_32_63:32;
2639 #endif
2640         } cn38xx;
2641         struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
2642         struct cvmx_npi_rsl_int_blocks_cn50xx {
2643 #ifdef __BIG_ENDIAN_BITFIELD
2644                 uint64_t reserved_31_63:33;
2645                 uint64_t iob:1;
2646                 uint64_t lmc1:1;
2647                 uint64_t agl:1;
2648                 uint64_t reserved_24_27:4;
2649                 uint64_t asx1:1;
2650                 uint64_t asx0:1;
2651                 uint64_t reserved_21_21:1;
2652                 uint64_t pip:1;
2653                 uint64_t spx1:1;
2654                 uint64_t spx0:1;
2655                 uint64_t lmc:1;
2656                 uint64_t l2c:1;
2657                 uint64_t reserved_15_15:1;
2658                 uint64_t rad:1;
2659                 uint64_t usb:1;
2660                 uint64_t pow:1;
2661                 uint64_t tim:1;
2662                 uint64_t pko:1;
2663                 uint64_t ipd:1;
2664                 uint64_t reserved_8_8:1;
2665                 uint64_t zip:1;
2666                 uint64_t dfa:1;
2667                 uint64_t fpa:1;
2668                 uint64_t key:1;
2669                 uint64_t npi:1;
2670                 uint64_t gmx1:1;
2671                 uint64_t gmx0:1;
2672                 uint64_t mio:1;
2673 #else
2674                 uint64_t mio:1;
2675                 uint64_t gmx0:1;
2676                 uint64_t gmx1:1;
2677                 uint64_t npi:1;
2678                 uint64_t key:1;
2679                 uint64_t fpa:1;
2680                 uint64_t dfa:1;
2681                 uint64_t zip:1;
2682                 uint64_t reserved_8_8:1;
2683                 uint64_t ipd:1;
2684                 uint64_t pko:1;
2685                 uint64_t tim:1;
2686                 uint64_t pow:1;
2687                 uint64_t usb:1;
2688                 uint64_t rad:1;
2689                 uint64_t reserved_15_15:1;
2690                 uint64_t l2c:1;
2691                 uint64_t lmc:1;
2692                 uint64_t spx0:1;
2693                 uint64_t spx1:1;
2694                 uint64_t pip:1;
2695                 uint64_t reserved_21_21:1;
2696                 uint64_t asx0:1;
2697                 uint64_t asx1:1;
2698                 uint64_t reserved_24_27:4;
2699                 uint64_t agl:1;
2700                 uint64_t lmc1:1;
2701                 uint64_t iob:1;
2702                 uint64_t reserved_31_63:33;
2703 #endif
2704         } cn50xx;
2705         struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
2706         struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
2707 };
2708
2709 union cvmx_npi_size_inputx {
2710         uint64_t u64;
2711         struct cvmx_npi_size_inputx_s {
2712 #ifdef __BIG_ENDIAN_BITFIELD
2713                 uint64_t reserved_32_63:32;
2714                 uint64_t size:32;
2715 #else
2716                 uint64_t size:32;
2717                 uint64_t reserved_32_63:32;
2718 #endif
2719         } s;
2720         struct cvmx_npi_size_inputx_s cn30xx;
2721         struct cvmx_npi_size_inputx_s cn31xx;
2722         struct cvmx_npi_size_inputx_s cn38xx;
2723         struct cvmx_npi_size_inputx_s cn38xxp2;
2724         struct cvmx_npi_size_inputx_s cn50xx;
2725         struct cvmx_npi_size_inputx_s cn58xx;
2726         struct cvmx_npi_size_inputx_s cn58xxp1;
2727 };
2728
2729 union cvmx_npi_win_read_to {
2730         uint64_t u64;
2731         struct cvmx_npi_win_read_to_s {
2732 #ifdef __BIG_ENDIAN_BITFIELD
2733                 uint64_t reserved_32_63:32;
2734                 uint64_t time:32;
2735 #else
2736                 uint64_t time:32;
2737                 uint64_t reserved_32_63:32;
2738 #endif
2739         } s;
2740         struct cvmx_npi_win_read_to_s cn30xx;
2741         struct cvmx_npi_win_read_to_s cn31xx;
2742         struct cvmx_npi_win_read_to_s cn38xx;
2743         struct cvmx_npi_win_read_to_s cn38xxp2;
2744         struct cvmx_npi_win_read_to_s cn50xx;
2745         struct cvmx_npi_win_read_to_s cn58xx;
2746         struct cvmx_npi_win_read_to_s cn58xxp1;
2747 };
2748
2749 #endif