2 * Format of an instruction in memory.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2014 Imagination Technologies Ltd.
13 #ifndef _UAPI_ASM_INST_H
14 #define _UAPI_ASM_INST_H
16 #include <asm/bitfield.h>
19 * Major opcodes; before MIPS IV cop1x was called cop3.
22 spec_op
, bcond_op
, j_op
, jal_op
,
23 beq_op
, bne_op
, blez_op
, bgtz_op
,
24 addi_op
, cbcond0_op
= addi_op
, addiu_op
, slti_op
, sltiu_op
,
25 andi_op
, ori_op
, xori_op
, lui_op
,
26 cop0_op
, cop1_op
, cop2_op
, cop1x_op
,
27 beql_op
, bnel_op
, blezl_op
, bgtzl_op
,
28 daddi_op
, cbcond1_op
= daddi_op
, daddiu_op
, ldl_op
, ldr_op
,
29 spec2_op
, jalx_op
, mdmx_op
, msa_op
= mdmx_op
, spec3_op
,
30 lb_op
, lh_op
, lwl_op
, lw_op
,
31 lbu_op
, lhu_op
, lwr_op
, lwu_op
,
32 sb_op
, sh_op
, swl_op
, sw_op
,
33 sdl_op
, sdr_op
, swr_op
, cache_op
,
34 ll_op
, lwc1_op
, lwc2_op
, bc6_op
= lwc2_op
, pref_op
,
35 lld_op
, ldc1_op
, ldc2_op
, beqzcjic_op
= ldc2_op
, ld_op
,
36 sc_op
, swc1_op
, swc2_op
, balc6_op
= swc2_op
, major_3b_op
,
37 scd_op
, sdc1_op
, sdc2_op
, bnezcjialc_op
= sdc2_op
, sd_op
41 * func field of spec opcode.
44 sll_op
, movc_op
, srl_op
, sra_op
,
45 sllv_op
, pmon_op
, srlv_op
, srav_op
,
46 jr_op
, jalr_op
, movz_op
, movn_op
,
47 syscall_op
, break_op
, spim_op
, sync_op
,
48 mfhi_op
, mthi_op
, mflo_op
, mtlo_op
,
49 dsllv_op
, spec2_unused_op
, dsrlv_op
, dsrav_op
,
50 mult_op
, multu_op
, div_op
, divu_op
,
51 dmult_op
, dmultu_op
, ddiv_op
, ddivu_op
,
52 add_op
, addu_op
, sub_op
, subu_op
,
53 and_op
, or_op
, xor_op
, nor_op
,
54 spec3_unused_op
, spec4_unused_op
, slt_op
, sltu_op
,
55 dadd_op
, daddu_op
, dsub_op
, dsubu_op
,
56 tge_op
, tgeu_op
, tlt_op
, tltu_op
,
57 teq_op
, spec5_unused_op
, tne_op
, spec6_unused_op
,
58 dsll_op
, spec7_unused_op
, dsrl_op
, dsra_op
,
59 dsll32_op
, spec8_unused_op
, dsrl32_op
, dsra32_op
63 * func field of spec2 opcode.
66 madd_op
, maddu_op
, mul_op
, spec2_3_unused_op
,
67 msub_op
, msubu_op
, /* more unused ops */
68 clz_op
= 0x20, clo_op
,
69 dclz_op
= 0x24, dclo_op
,
74 * func field of spec3 opcode.
77 ext_op
, dextm_op
, dextu_op
, dext_op
,
78 ins_op
, dinsm_op
, dinsu_op
, dins_op
,
79 yield_op
= 0x09, lx_op
= 0x0a,
80 lwle_op
= 0x19, lwre_op
= 0x1a,
81 cachee_op
= 0x1b, sbe_op
= 0x1c,
82 she_op
= 0x1d, sce_op
= 0x1e,
83 swe_op
= 0x1f, bshfl_op
= 0x20,
84 swle_op
= 0x21, swre_op
= 0x22,
85 prefe_op
= 0x23, dbshfl_op
= 0x24,
86 cache6_op
= 0x25, sc6_op
= 0x26,
87 scd6_op
= 0x27, lbue_op
= 0x28,
88 lhue_op
= 0x29, lbe_op
= 0x2c,
89 lhe_op
= 0x2d, lle_op
= 0x2e,
90 lwe_op
= 0x2f, pref6_op
= 0x35,
91 ll6_op
= 0x36, lld6_op
= 0x37,
96 * rt field of bcond opcodes.
99 bltz_op
, bgez_op
, bltzl_op
, bgezl_op
,
100 spimi_op
, unused_rt_op_0x05
, unused_rt_op_0x06
, unused_rt_op_0x07
,
101 tgei_op
, tgeiu_op
, tlti_op
, tltiu_op
,
102 teqi_op
, unused_0x0d_rt_op
, tnei_op
, unused_0x0f_rt_op
,
103 bltzal_op
, bgezal_op
, bltzall_op
, bgezall_op
,
104 rt_op_0x14
, rt_op_0x15
, rt_op_0x16
, rt_op_0x17
,
105 rt_op_0x18
, rt_op_0x19
, rt_op_0x1a
, rt_op_0x1b
,
106 bposge32_op
, rt_op_0x1d
, rt_op_0x1e
, rt_op_0x1f
110 * rs field of cop opcodes.
113 mfc_op
= 0x00, dmfc_op
= 0x01,
114 cfc_op
= 0x02, mfhc0_op
= 0x02,
115 mfhc_op
= 0x03, mtc_op
= 0x04,
116 dmtc_op
= 0x05, ctc_op
= 0x06,
117 mthc0_op
= 0x06, mthc_op
= 0x07,
118 bc_op
= 0x08, bc1eqz_op
= 0x09,
119 mfmc0_op
= 0x0b, bc1nez_op
= 0x0d,
120 wrpgpr_op
= 0x0e, cop_op
= 0x10,
125 * rt field of cop.bc_op opcodes
128 bcf_op
, bct_op
, bcfl_op
, bctl_op
132 * func field of cop0 coi opcodes.
135 tlbr_op
= 0x01, tlbwi_op
= 0x02,
136 tlbwr_op
= 0x06, tlbp_op
= 0x08,
137 rfe_op
= 0x10, eret_op
= 0x18,
142 * func field of cop0 com opcodes.
145 tlbr1_op
= 0x01, tlbw_op
= 0x02,
146 tlbp1_op
= 0x08, dctr_op
= 0x09,
151 * fmt field of cop1 opcodes.
154 s_fmt
, d_fmt
, e_fmt
, q_fmt
,
159 * func field of cop1 instructions using d, s or w format.
162 fadd_op
= 0x00, fsub_op
= 0x01,
163 fmul_op
= 0x02, fdiv_op
= 0x03,
164 fsqrt_op
= 0x04, fabs_op
= 0x05,
165 fmov_op
= 0x06, fneg_op
= 0x07,
166 froundl_op
= 0x08, ftruncl_op
= 0x09,
167 fceill_op
= 0x0a, ffloorl_op
= 0x0b,
168 fround_op
= 0x0c, ftrunc_op
= 0x0d,
169 fceil_op
= 0x0e, ffloor_op
= 0x0f,
171 fmovc_op
= 0x11, fmovz_op
= 0x12,
172 fmovn_op
= 0x13, fseleqz_op
= 0x14,
173 frecip_op
= 0x15, frsqrt_op
= 0x16,
174 fselnez_op
= 0x17, fmaddf_op
= 0x18,
175 fmsubf_op
= 0x19, frint_op
= 0x1a,
176 fclass_op
= 0x1b, fmin_op
= 0x1c,
177 fmina_op
= 0x1d, fmax_op
= 0x1e,
178 fmaxa_op
= 0x1f, fcvts_op
= 0x20,
179 fcvtd_op
= 0x21, fcvte_op
= 0x22,
180 fcvtw_op
= 0x24, fcvtl_op
= 0x25,
185 * func field of cop1x opcodes (MIPS IV).
188 lwxc1_op
= 0x00, ldxc1_op
= 0x01,
189 swxc1_op
= 0x08, sdxc1_op
= 0x09,
190 pfetch_op
= 0x0f, madd_s_op
= 0x20,
191 madd_d_op
= 0x21, madd_e_op
= 0x22,
192 msub_s_op
= 0x28, msub_d_op
= 0x29,
193 msub_e_op
= 0x2a, nmadd_s_op
= 0x30,
194 nmadd_d_op
= 0x31, nmadd_e_op
= 0x32,
195 nmsub_s_op
= 0x38, nmsub_d_op
= 0x39,
200 * func field for mad opcodes (MIPS IV).
203 madd_fp_op
= 0x08, msub_fp_op
= 0x0a,
204 nmadd_fp_op
= 0x0c, nmsub_fp_op
= 0x0e
208 * func field for page table walker (Loongson-3).
218 * func field for special3 lx opcodes (Cavium Octeon).
241 * func field for MSA MI10 format.
249 * MSA 2 bit format fields.
259 * (microMIPS) Major opcodes.
262 mm_pool32a_op
, mm_pool16a_op
, mm_lbu16_op
, mm_move16_op
,
263 mm_addi32_op
, mm_lbu32_op
, mm_sb32_op
, mm_lb32_op
,
264 mm_pool32b_op
, mm_pool16b_op
, mm_lhu16_op
, mm_andi16_op
,
265 mm_addiu32_op
, mm_lhu32_op
, mm_sh32_op
, mm_lh32_op
,
266 mm_pool32i_op
, mm_pool16c_op
, mm_lwsp16_op
, mm_pool16d_op
,
267 mm_ori32_op
, mm_pool32f_op
, mm_reserved1_op
, mm_reserved2_op
,
268 mm_pool32c_op
, mm_lwgp16_op
, mm_lw16_op
, mm_pool16e_op
,
269 mm_xori32_op
, mm_jals32_op
, mm_addiupc_op
, mm_reserved3_op
,
270 mm_reserved4_op
, mm_pool16f_op
, mm_sb16_op
, mm_beqz16_op
,
271 mm_slti32_op
, mm_beq32_op
, mm_swc132_op
, mm_lwc132_op
,
272 mm_reserved5_op
, mm_reserved6_op
, mm_sh16_op
, mm_bnez16_op
,
273 mm_sltiu32_op
, mm_bne32_op
, mm_sdc132_op
, mm_ldc132_op
,
274 mm_reserved7_op
, mm_reserved8_op
, mm_swsp16_op
, mm_b16_op
,
275 mm_andi32_op
, mm_j32_op
, mm_sd32_op
, mm_ld32_op
,
276 mm_reserved11_op
, mm_reserved12_op
, mm_sw16_op
, mm_li16_op
,
277 mm_jalx32_op
, mm_jal32_op
, mm_sw32_op
, mm_lw32_op
,
281 * (microMIPS) POOL32I minor opcodes.
283 enum mm_32i_minor_op
{
284 mm_bltz_op
, mm_bltzal_op
, mm_bgez_op
, mm_bgezal_op
,
285 mm_blez_op
, mm_bnezc_op
, mm_bgtz_op
, mm_beqzc_op
,
286 mm_tlti_op
, mm_tgei_op
, mm_tltiu_op
, mm_tgeiu_op
,
287 mm_tnei_op
, mm_lui_op
, mm_teqi_op
, mm_reserved13_op
,
288 mm_synci_op
, mm_bltzals_op
, mm_reserved14_op
, mm_bgezals_op
,
289 mm_bc2f_op
, mm_bc2t_op
, mm_reserved15_op
, mm_reserved16_op
,
290 mm_reserved17_op
, mm_reserved18_op
, mm_bposge64_op
, mm_bposge32_op
,
291 mm_bc1f_op
, mm_bc1t_op
, mm_reserved19_op
, mm_reserved20_op
,
292 mm_bc1any2f_op
, mm_bc1any2t_op
, mm_bc1any4f_op
, mm_bc1any4t_op
,
296 * (microMIPS) POOL32A minor opcodes.
298 enum mm_32a_minor_op
{
301 mm_sllv32_op
= 0x010,
303 mm_pool32axf_op
= 0x03c,
306 mm_srlv32_op
= 0x090,
309 mm_addu32_op
= 0x150,
310 mm_subu32_op
= 0x1d0,
321 * (microMIPS) POOL32B functions.
340 * (microMIPS) POOL32C functions.
351 * (microMIPS) POOL32AXF minor opcodes.
353 enum mm_32axf_minor_op
{
357 mm_mfhi32_op
= 0x035,
360 mm_mflo32_op
= 0x075,
361 mm_jalrhb_op
= 0x07c,
365 mm_jalrshb_op
= 0x17c,
367 mm_syscall_op
= 0x22d,
374 * (microMIPS) POOL32F minor opcodes.
376 enum mm_32f_minor_op
{
398 * (microMIPS) POOL32F secondary minor opcodes.
400 enum mm_32f_10_minor_op
{
410 mm_lwxc1_func
= 0x048,
411 mm_swxc1_func
= 0x088,
412 mm_ldxc1_func
= 0x0c8,
413 mm_sdxc1_func
= 0x108,
417 * (microMIPS) POOL32F secondary minor opcodes.
419 enum mm_32f_40_minor_op
{
425 * (microMIPS) POOL32F secondary minor opcodes.
427 enum mm_32f_60_minor_op
{
435 * (microMIPS) POOL32F secondary minor opcodes.
437 enum mm_32f_70_minor_op
{
443 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
445 enum mm_32f_73_minor_op
{
450 mm_ffloorl_op
= 0x0c,
455 mm_ffloorw_op
= 0x2c,
467 mm_ftruncl_op
= 0x8c,
471 mm_ftruncw_op
= 0xac,
474 mm_froundl_op
= 0xcc,
477 mm_froundw_op
= 0xec,
482 * (microMIPS) POOL16C minor opcodes.
484 enum mm_16c_minor_op
{
490 mm_jalrs16_op
= 0x0f,
491 mm_jraddiusp_op
= 0x18,
495 * (microMIPS) POOL16D minor opcodes.
497 enum mm_16d_minor_op
{
506 MIPS16e_jal_op
= 003,
512 MIPS16e_lwsp_op
= 022,
514 MIPS16e_lbu_op
= 024,
515 MIPS16e_lhu_op
= 025,
516 MIPS16e_lwpc_op
= 026,
517 MIPS16e_lwu_op
= 027,
520 MIPS16e_swsp_op
= 032,
523 MIPS16e_extend_op
= 036,
524 MIPS16e_i64_op
= 037,
527 enum MIPS16e_i64_func
{
535 enum MIPS16e_rr_func
{
539 enum MIPS6e_i8_func
{
540 MIPS16e_swrasp_func
= 02,
544 * (microMIPS) NOP instruction.
546 #define MM_NOP16 0x0c00
549 __BITFIELD_FIELD(unsigned int opcode
: 6, /* Jump format */
550 __BITFIELD_FIELD(unsigned int target
: 26,
554 struct i_format
{ /* signed immediate format */
555 __BITFIELD_FIELD(unsigned int opcode
: 6,
556 __BITFIELD_FIELD(unsigned int rs
: 5,
557 __BITFIELD_FIELD(unsigned int rt
: 5,
558 __BITFIELD_FIELD(signed int simmediate
: 16,
562 struct u_format
{ /* unsigned immediate format */
563 __BITFIELD_FIELD(unsigned int opcode
: 6,
564 __BITFIELD_FIELD(unsigned int rs
: 5,
565 __BITFIELD_FIELD(unsigned int rt
: 5,
566 __BITFIELD_FIELD(unsigned int uimmediate
: 16,
570 struct c_format
{ /* Cache (>= R6000) format */
571 __BITFIELD_FIELD(unsigned int opcode
: 6,
572 __BITFIELD_FIELD(unsigned int rs
: 5,
573 __BITFIELD_FIELD(unsigned int c_op
: 3,
574 __BITFIELD_FIELD(unsigned int cache
: 2,
575 __BITFIELD_FIELD(unsigned int simmediate
: 16,
579 struct r_format
{ /* Register format */
580 __BITFIELD_FIELD(unsigned int opcode
: 6,
581 __BITFIELD_FIELD(unsigned int rs
: 5,
582 __BITFIELD_FIELD(unsigned int rt
: 5,
583 __BITFIELD_FIELD(unsigned int rd
: 5,
584 __BITFIELD_FIELD(unsigned int re
: 5,
585 __BITFIELD_FIELD(unsigned int func
: 6,
589 struct p_format
{ /* Performance counter format (R10000) */
590 __BITFIELD_FIELD(unsigned int opcode
: 6,
591 __BITFIELD_FIELD(unsigned int rs
: 5,
592 __BITFIELD_FIELD(unsigned int rt
: 5,
593 __BITFIELD_FIELD(unsigned int rd
: 5,
594 __BITFIELD_FIELD(unsigned int re
: 5,
595 __BITFIELD_FIELD(unsigned int func
: 6,
599 struct f_format
{ /* FPU register format */
600 __BITFIELD_FIELD(unsigned int opcode
: 6,
601 __BITFIELD_FIELD(unsigned int : 1,
602 __BITFIELD_FIELD(unsigned int fmt
: 4,
603 __BITFIELD_FIELD(unsigned int rt
: 5,
604 __BITFIELD_FIELD(unsigned int rd
: 5,
605 __BITFIELD_FIELD(unsigned int re
: 5,
606 __BITFIELD_FIELD(unsigned int func
: 6,
610 struct ma_format
{ /* FPU multiply and add format (MIPS IV) */
611 __BITFIELD_FIELD(unsigned int opcode
: 6,
612 __BITFIELD_FIELD(unsigned int fr
: 5,
613 __BITFIELD_FIELD(unsigned int ft
: 5,
614 __BITFIELD_FIELD(unsigned int fs
: 5,
615 __BITFIELD_FIELD(unsigned int fd
: 5,
616 __BITFIELD_FIELD(unsigned int func
: 4,
617 __BITFIELD_FIELD(unsigned int fmt
: 2,
621 struct b_format
{ /* BREAK and SYSCALL */
622 __BITFIELD_FIELD(unsigned int opcode
: 6,
623 __BITFIELD_FIELD(unsigned int code
: 20,
624 __BITFIELD_FIELD(unsigned int func
: 6,
628 struct ps_format
{ /* MIPS-3D / paired single format */
629 __BITFIELD_FIELD(unsigned int opcode
: 6,
630 __BITFIELD_FIELD(unsigned int rs
: 5,
631 __BITFIELD_FIELD(unsigned int ft
: 5,
632 __BITFIELD_FIELD(unsigned int fs
: 5,
633 __BITFIELD_FIELD(unsigned int fd
: 5,
634 __BITFIELD_FIELD(unsigned int func
: 6,
638 struct v_format
{ /* MDMX vector format */
639 __BITFIELD_FIELD(unsigned int opcode
: 6,
640 __BITFIELD_FIELD(unsigned int sel
: 4,
641 __BITFIELD_FIELD(unsigned int fmt
: 1,
642 __BITFIELD_FIELD(unsigned int vt
: 5,
643 __BITFIELD_FIELD(unsigned int vs
: 5,
644 __BITFIELD_FIELD(unsigned int vd
: 5,
645 __BITFIELD_FIELD(unsigned int func
: 6,
649 struct msa_mi10_format
{ /* MSA MI10 */
650 __BITFIELD_FIELD(unsigned int opcode
: 6,
651 __BITFIELD_FIELD(signed int s10
: 10,
652 __BITFIELD_FIELD(unsigned int rs
: 5,
653 __BITFIELD_FIELD(unsigned int wd
: 5,
654 __BITFIELD_FIELD(unsigned int func
: 4,
655 __BITFIELD_FIELD(unsigned int df
: 2,
659 struct spec3_format
{ /* SPEC3 */
660 __BITFIELD_FIELD(unsigned int opcode
:6,
661 __BITFIELD_FIELD(unsigned int rs
:5,
662 __BITFIELD_FIELD(unsigned int rt
:5,
663 __BITFIELD_FIELD(signed int simmediate
:9,
664 __BITFIELD_FIELD(unsigned int func
:7,
669 * microMIPS instruction formats (32-bit length)
672 * Parenthesis denote whether the format is a microMIPS instruction or
673 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
675 struct fb_format
{ /* FPU branch format (MIPS32) */
676 __BITFIELD_FIELD(unsigned int opcode
: 6,
677 __BITFIELD_FIELD(unsigned int bc
: 5,
678 __BITFIELD_FIELD(unsigned int cc
: 3,
679 __BITFIELD_FIELD(unsigned int flag
: 2,
680 __BITFIELD_FIELD(signed int simmediate
: 16,
684 struct fp0_format
{ /* FPU multiply and add format (MIPS32) */
685 __BITFIELD_FIELD(unsigned int opcode
: 6,
686 __BITFIELD_FIELD(unsigned int fmt
: 5,
687 __BITFIELD_FIELD(unsigned int ft
: 5,
688 __BITFIELD_FIELD(unsigned int fs
: 5,
689 __BITFIELD_FIELD(unsigned int fd
: 5,
690 __BITFIELD_FIELD(unsigned int func
: 6,
694 struct mm_fp0_format
{ /* FPU multiply and add format (microMIPS) */
695 __BITFIELD_FIELD(unsigned int opcode
: 6,
696 __BITFIELD_FIELD(unsigned int ft
: 5,
697 __BITFIELD_FIELD(unsigned int fs
: 5,
698 __BITFIELD_FIELD(unsigned int fd
: 5,
699 __BITFIELD_FIELD(unsigned int fmt
: 3,
700 __BITFIELD_FIELD(unsigned int op
: 2,
701 __BITFIELD_FIELD(unsigned int func
: 6,
705 struct fp1_format
{ /* FPU mfc1 and cfc1 format (MIPS32) */
706 __BITFIELD_FIELD(unsigned int opcode
: 6,
707 __BITFIELD_FIELD(unsigned int op
: 5,
708 __BITFIELD_FIELD(unsigned int rt
: 5,
709 __BITFIELD_FIELD(unsigned int fs
: 5,
710 __BITFIELD_FIELD(unsigned int fd
: 5,
711 __BITFIELD_FIELD(unsigned int func
: 6,
715 struct mm_fp1_format
{ /* FPU mfc1 and cfc1 format (microMIPS) */
716 __BITFIELD_FIELD(unsigned int opcode
: 6,
717 __BITFIELD_FIELD(unsigned int rt
: 5,
718 __BITFIELD_FIELD(unsigned int fs
: 5,
719 __BITFIELD_FIELD(unsigned int fmt
: 2,
720 __BITFIELD_FIELD(unsigned int op
: 8,
721 __BITFIELD_FIELD(unsigned int func
: 6,
725 struct mm_fp2_format
{ /* FPU movt and movf format (microMIPS) */
726 __BITFIELD_FIELD(unsigned int opcode
: 6,
727 __BITFIELD_FIELD(unsigned int fd
: 5,
728 __BITFIELD_FIELD(unsigned int fs
: 5,
729 __BITFIELD_FIELD(unsigned int cc
: 3,
730 __BITFIELD_FIELD(unsigned int zero
: 2,
731 __BITFIELD_FIELD(unsigned int fmt
: 2,
732 __BITFIELD_FIELD(unsigned int op
: 3,
733 __BITFIELD_FIELD(unsigned int func
: 6,
737 struct mm_fp3_format
{ /* FPU abs and neg format (microMIPS) */
738 __BITFIELD_FIELD(unsigned int opcode
: 6,
739 __BITFIELD_FIELD(unsigned int rt
: 5,
740 __BITFIELD_FIELD(unsigned int fs
: 5,
741 __BITFIELD_FIELD(unsigned int fmt
: 3,
742 __BITFIELD_FIELD(unsigned int op
: 7,
743 __BITFIELD_FIELD(unsigned int func
: 6,
747 struct mm_fp4_format
{ /* FPU c.cond format (microMIPS) */
748 __BITFIELD_FIELD(unsigned int opcode
: 6,
749 __BITFIELD_FIELD(unsigned int rt
: 5,
750 __BITFIELD_FIELD(unsigned int fs
: 5,
751 __BITFIELD_FIELD(unsigned int cc
: 3,
752 __BITFIELD_FIELD(unsigned int fmt
: 3,
753 __BITFIELD_FIELD(unsigned int cond
: 4,
754 __BITFIELD_FIELD(unsigned int func
: 6,
758 struct mm_fp5_format
{ /* FPU lwxc1 and swxc1 format (microMIPS) */
759 __BITFIELD_FIELD(unsigned int opcode
: 6,
760 __BITFIELD_FIELD(unsigned int index
: 5,
761 __BITFIELD_FIELD(unsigned int base
: 5,
762 __BITFIELD_FIELD(unsigned int fd
: 5,
763 __BITFIELD_FIELD(unsigned int op
: 5,
764 __BITFIELD_FIELD(unsigned int func
: 6,
768 struct fp6_format
{ /* FPU madd and msub format (MIPS IV) */
769 __BITFIELD_FIELD(unsigned int opcode
: 6,
770 __BITFIELD_FIELD(unsigned int fr
: 5,
771 __BITFIELD_FIELD(unsigned int ft
: 5,
772 __BITFIELD_FIELD(unsigned int fs
: 5,
773 __BITFIELD_FIELD(unsigned int fd
: 5,
774 __BITFIELD_FIELD(unsigned int func
: 6,
778 struct mm_fp6_format
{ /* FPU madd and msub format (microMIPS) */
779 __BITFIELD_FIELD(unsigned int opcode
: 6,
780 __BITFIELD_FIELD(unsigned int ft
: 5,
781 __BITFIELD_FIELD(unsigned int fs
: 5,
782 __BITFIELD_FIELD(unsigned int fd
: 5,
783 __BITFIELD_FIELD(unsigned int fr
: 5,
784 __BITFIELD_FIELD(unsigned int func
: 6,
788 struct mm_i_format
{ /* Immediate format (microMIPS) */
789 __BITFIELD_FIELD(unsigned int opcode
: 6,
790 __BITFIELD_FIELD(unsigned int rt
: 5,
791 __BITFIELD_FIELD(unsigned int rs
: 5,
792 __BITFIELD_FIELD(signed int simmediate
: 16,
796 struct mm_m_format
{ /* Multi-word load/store format (microMIPS) */
797 __BITFIELD_FIELD(unsigned int opcode
: 6,
798 __BITFIELD_FIELD(unsigned int rd
: 5,
799 __BITFIELD_FIELD(unsigned int base
: 5,
800 __BITFIELD_FIELD(unsigned int func
: 4,
801 __BITFIELD_FIELD(signed int simmediate
: 12,
805 struct mm_x_format
{ /* Scaled indexed load format (microMIPS) */
806 __BITFIELD_FIELD(unsigned int opcode
: 6,
807 __BITFIELD_FIELD(unsigned int index
: 5,
808 __BITFIELD_FIELD(unsigned int base
: 5,
809 __BITFIELD_FIELD(unsigned int rd
: 5,
810 __BITFIELD_FIELD(unsigned int func
: 11,
814 struct mm_a_format
{ /* ADDIUPC format (microMIPS) */
815 __BITFIELD_FIELD(unsigned int opcode
: 6,
816 __BITFIELD_FIELD(unsigned int rs
: 3,
817 __BITFIELD_FIELD(signed int simmediate
: 23,
822 * microMIPS instruction formats (16-bit length)
824 struct mm_b0_format
{ /* Unconditional branch format (microMIPS) */
825 __BITFIELD_FIELD(unsigned int opcode
: 6,
826 __BITFIELD_FIELD(signed int simmediate
: 10,
827 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
831 struct mm_b1_format
{ /* Conditional branch format (microMIPS) */
832 __BITFIELD_FIELD(unsigned int opcode
: 6,
833 __BITFIELD_FIELD(unsigned int rs
: 3,
834 __BITFIELD_FIELD(signed int simmediate
: 7,
835 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
839 struct mm16_m_format
{ /* Multi-word load/store format */
840 __BITFIELD_FIELD(unsigned int opcode
: 6,
841 __BITFIELD_FIELD(unsigned int func
: 4,
842 __BITFIELD_FIELD(unsigned int rlist
: 2,
843 __BITFIELD_FIELD(unsigned int imm
: 4,
844 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
848 struct mm16_rb_format
{ /* Signed immediate format */
849 __BITFIELD_FIELD(unsigned int opcode
: 6,
850 __BITFIELD_FIELD(unsigned int rt
: 3,
851 __BITFIELD_FIELD(unsigned int base
: 3,
852 __BITFIELD_FIELD(signed int simmediate
: 4,
853 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
857 struct mm16_r3_format
{ /* Load from global pointer format */
858 __BITFIELD_FIELD(unsigned int opcode
: 6,
859 __BITFIELD_FIELD(unsigned int rt
: 3,
860 __BITFIELD_FIELD(signed int simmediate
: 7,
861 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
865 struct mm16_r5_format
{ /* Load/store from stack pointer format */
866 __BITFIELD_FIELD(unsigned int opcode
: 6,
867 __BITFIELD_FIELD(unsigned int rt
: 5,
868 __BITFIELD_FIELD(signed int simmediate
: 5,
869 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
874 * MIPS16e instruction formats (16-bit length)
877 __BITFIELD_FIELD(unsigned int opcode
: 5,
878 __BITFIELD_FIELD(unsigned int rx
: 3,
879 __BITFIELD_FIELD(unsigned int nd
: 1,
880 __BITFIELD_FIELD(unsigned int l
: 1,
881 __BITFIELD_FIELD(unsigned int ra
: 1,
882 __BITFIELD_FIELD(unsigned int func
: 5,
887 __BITFIELD_FIELD(unsigned int opcode
: 5,
888 __BITFIELD_FIELD(unsigned int x
: 1,
889 __BITFIELD_FIELD(unsigned int imm20_16
: 5,
890 __BITFIELD_FIELD(signed int imm25_21
: 5,
895 __BITFIELD_FIELD(unsigned int opcode
: 5,
896 __BITFIELD_FIELD(unsigned int func
: 3,
897 __BITFIELD_FIELD(unsigned int imm
: 8,
902 __BITFIELD_FIELD(unsigned int opcode
: 5,
903 __BITFIELD_FIELD(unsigned int func
: 3,
904 __BITFIELD_FIELD(unsigned int ry
: 3,
905 __BITFIELD_FIELD(unsigned int imm
: 5,
910 __BITFIELD_FIELD(unsigned int opcode
: 5,
911 __BITFIELD_FIELD(unsigned int rx
: 3,
912 __BITFIELD_FIELD(unsigned int imm
: 8,
917 __BITFIELD_FIELD(unsigned int opcode
: 5,
918 __BITFIELD_FIELD(unsigned int rx
: 3,
919 __BITFIELD_FIELD(unsigned int ry
: 3,
920 __BITFIELD_FIELD(unsigned int imm
: 5,
925 __BITFIELD_FIELD(unsigned int opcode
: 5,
926 __BITFIELD_FIELD(unsigned int func
: 3,
927 __BITFIELD_FIELD(unsigned int imm
: 8,
931 union mips_instruction
{
933 unsigned short halfword
[2];
934 unsigned char byte
[4];
935 struct j_format j_format
;
936 struct i_format i_format
;
937 struct u_format u_format
;
938 struct c_format c_format
;
939 struct r_format r_format
;
940 struct p_format p_format
;
941 struct f_format f_format
;
942 struct ma_format ma_format
;
943 struct msa_mi10_format msa_mi10_format
;
944 struct b_format b_format
;
945 struct ps_format ps_format
;
946 struct v_format v_format
;
947 struct spec3_format spec3_format
;
948 struct fb_format fb_format
;
949 struct fp0_format fp0_format
;
950 struct mm_fp0_format mm_fp0_format
;
951 struct fp1_format fp1_format
;
952 struct mm_fp1_format mm_fp1_format
;
953 struct mm_fp2_format mm_fp2_format
;
954 struct mm_fp3_format mm_fp3_format
;
955 struct mm_fp4_format mm_fp4_format
;
956 struct mm_fp5_format mm_fp5_format
;
957 struct fp6_format fp6_format
;
958 struct mm_fp6_format mm_fp6_format
;
959 struct mm_i_format mm_i_format
;
960 struct mm_m_format mm_m_format
;
961 struct mm_x_format mm_x_format
;
962 struct mm_a_format mm_a_format
;
963 struct mm_b0_format mm_b0_format
;
964 struct mm_b1_format mm_b1_format
;
965 struct mm16_m_format mm16_m_format
;
966 struct mm16_rb_format mm16_rb_format
;
967 struct mm16_r3_format mm16_r3_format
;
968 struct mm16_r5_format mm16_r5_format
;
971 union mips16e_instruction
{
972 unsigned int full
: 16;
976 struct m16e_ri64 ri64
;
982 #endif /* _UAPI_ASM_INST_H */