arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/kdev_t.h>
  39 #include <linux/types.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/ide.h>
  43 #include <linux/irq.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47 #include <linux/pm.h>
  48 #include <linux/platform_device.h>
  49 #ifdef CONFIG_SERIAL_TXX9
  50 #include <linux/tty.h>
  51 #include <linux/serial.h>
  52 #include <linux/serial_core.h>
  53 #endif
  54
  55 #include <asm/addrspace.h>
  56 #include <asm/time.h>
  57 #include <asm/reboot.h>
  58 #include <asm/jmr3927/jmr3927.h>
  59 #include <asm/mipsregs.h>
  60
  61 extern void puts(const char *cp);
  62
  63 /* Tick Timer divider */
  64 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  65 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  66
  67 /* don't enable - see errata */
  68 static int jmr3927_ccfg_toeon;
  69
  70 static inline void do_reset(void)
  71 {
  72 #if 1   /* Resetting PCI bus */
  73         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  74         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
  75         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
  76         mdelay(1);
  77         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  78 #endif
  79         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
  80 }
  81
  82 static void jmr3927_machine_restart(char *command)
  83 {
  84         local_irq_disable();
  85         puts("Rebooting...");
  86         do_reset();
  87 }
  88
  89 static void jmr3927_machine_halt(void)
  90 {
  91         puts("JMR-TX3927 halted.\n");
  92         while (1);
  93 }
  94
  95 static void jmr3927_machine_power_off(void)
  96 {
  97         puts("JMR-TX3927 halted. Please turn off the power.\n");
  98         while (1);
  99 }
 100
 101 static cycle_t jmr3927_hpt_read(void)
 102 {
 103         /* We assume this function is called xtime_lock held. */
 104         return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
 105 }
 106
 107 static void jmr3927_timer_ack(void)
 108 {
 109         jmr3927_tmrptr->tisr = 0;       /* ack interrupt */
 110 }
 111
 112 void __init plat_time_init(void)
 113 {
 114         clocksource_mips.read = jmr3927_hpt_read;
 115         mips_timer_ack = jmr3927_timer_ack;
 116         mips_hpt_frequency = JMR3927_TIMER_CLK;
 117 }
 118
 119 void __init plat_timer_setup(struct irqaction *irq)
 120 {
 121         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 122         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 123         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 124         jmr3927_tmrptr->tcr =
 125                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 126
 127         setup_irq(JMR3927_IRQ_TICK, irq);
 128 }
 129
 130 #define DO_WRITE_THROUGH
 131 #define DO_ENABLE_CACHE
 132
 133 extern char * __init prom_getcmdline(void);
 134 static void jmr3927_board_init(void);
 135 extern struct resource pci_io_resource;
 136 extern struct resource pci_mem_resource;
 137
 138 void __init plat_mem_setup(void)
 139 {
 140         char *argptr;
 141
 142         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 143
 144         _machine_restart = jmr3927_machine_restart;
 145         _machine_halt = jmr3927_machine_halt;
 146         pm_power_off = jmr3927_machine_power_off;
 147
 148         /*
 149          * IO/MEM resources.
 150          */
 151         ioport_resource.start = pci_io_resource.start;
 152         ioport_resource.end = pci_io_resource.end;
 153         iomem_resource.start = 0;
 154         iomem_resource.end = 0xffffffff;
 155
 156         /* Reboot on panic */
 157         panic_timeout = 180;
 158
 159         /* cache setup */
 160         {
 161                 unsigned int conf;
 162 #ifdef DO_ENABLE_CACHE
 163                 int mips_ic_disable = 0, mips_dc_disable = 0;
 164 #else
 165                 int mips_ic_disable = 1, mips_dc_disable = 1;
 166 #endif
 167 #ifdef DO_WRITE_THROUGH
 168                 int mips_config_cwfon = 0;
 169                 int mips_config_wbon = 0;
 170 #else
 171                 int mips_config_cwfon = 1;
 172                 int mips_config_wbon = 1;
 173 #endif
 174
 175                 conf = read_c0_conf();
 176                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 177                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 178                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 179                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 180                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 181
 182                 write_c0_conf(conf);
 183                 write_c0_cache(0);
 184         }
 185
 186         /* initialize board */
 187         jmr3927_board_init();
 188
 189         argptr = prom_getcmdline();
 190
 191         if ((argptr = strstr(argptr, "toeon")) != NULL)
 192                 jmr3927_ccfg_toeon = 1;
 193         argptr = prom_getcmdline();
 194         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 195                 argptr = prom_getcmdline();
 196                 strcat(argptr, " ip=bootp");
 197         }
 198
 199 #ifdef CONFIG_SERIAL_TXX9
 200         {
 201                 extern int early_serial_txx9_setup(struct uart_port *port);
 202                 int i;
 203                 struct uart_port req;
 204                 for(i = 0; i < 2; i++) {
 205                         memset(&req, 0, sizeof(req));
 206                         req.line = i;
 207                         req.iotype = UPIO_MEM;
 208                         req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
 209                         req.mapbase = TX3927_SIO_REG(i);
 210                         req.irq = i == 0 ?
 211                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 212                         if (i == 0)
 213                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 214                         req.uartclk = JMR3927_IMCLK;
 215                         early_serial_txx9_setup(&req);
 216                 }
 217         }
 218 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 219         argptr = prom_getcmdline();
 220         if ((argptr = strstr(argptr, "console=")) == NULL) {
 221                 argptr = prom_getcmdline();
 222                 strcat(argptr, " console=ttyS1,115200");
 223         }
 224 #endif
 225 #endif
 226 }
 227
 228 static void tx3927_setup(void);
 229
 230 static void __init jmr3927_board_init(void)
 231 {
 232         tx3927_setup();
 233
 234         /* SIO0 DTR on */
 235         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 236
 237         jmr3927_led_set(0);
 238
 239         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 240                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 241                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 242                jmr3927_dipsw1(), jmr3927_dipsw2(),
 243                jmr3927_dipsw3(), jmr3927_dipsw4());
 244 }
 245
 246 static void __init tx3927_setup(void)
 247 {
 248         int i;
 249 #ifdef CONFIG_PCI
 250         unsigned long mips_pci_io_base = JMR3927_PCIIO;
 251         unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
 252         unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
 253         unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 254         /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 255         unsigned long mips_pci_io_pciaddr = 0;
 256 #endif
 257
 258         /* SDRAMC are configured by PROM */
 259
 260         /* ROMC */
 261         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 262         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 263         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 264         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 265
 266         /* CCFG */
 267         /* enable Timeout BusError */
 268         if (jmr3927_ccfg_toeon)
 269                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 270
 271         /* clear BusErrorOnWrite flag */
 272         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 273         /* Disable PCI snoop */
 274         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 275
 276 #ifdef DO_WRITE_THROUGH
 277         /* Enable PCI SNOOP - with write through only */
 278         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 279 #endif
 280
 281         /* Pin selection */
 282         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 283         tx3927_ccfgptr->pcfg |=
 284                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 285                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 286
 287         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 288                tx3927_ccfgptr->crir,
 289                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 290
 291         /* TMR */
 292         /* disable all timers */
 293         for (i = 0; i < TX3927_NR_TMR; i++) {
 294                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 295                 tx3927_tmrptr(i)->tisr = 0;
 296                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 297                 tx3927_tmrptr(i)->itmr = 0;
 298                 tx3927_tmrptr(i)->ccdr = 0;
 299                 tx3927_tmrptr(i)->pgmr = 0;
 300         }
 301
 302         /* DMA */
 303         tx3927_dmaptr->mcr = 0;
 304         for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
 305                 /* reset channel */
 306                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 307                 tx3927_dmaptr->ch[i].ccr = 0;
 308         }
 309         /* enable DMA */
 310 #ifdef __BIG_ENDIAN
 311         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 312 #else
 313         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 314 #endif
 315
 316 #ifdef CONFIG_PCI
 317         /* PCIC */
 318         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 319                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 320                tx3927_pcicptr->rid);
 321         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 322                 printk("External\n");
 323                 /* XXX */
 324         } else {
 325                 printk("Internal\n");
 326
 327                 /* Reset PCI Bus */
 328                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 329                 udelay(100);
 330                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 331                                     JMR3927_IOC_RESET_ADDR);
 332                 udelay(100);
 333                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 334
 335
 336                 /* Disable External PCI Config. Access */
 337                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 338 #ifdef __BIG_ENDIAN
 339                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 340                         TX3927_PCIC_LBC_TIBSE |
 341                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 342 #endif
 343                 /* LB->PCI mappings */
 344                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 345                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 346                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 347                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 348                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 349                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 350                 /* PCI->LB mappings */
 351                 tx3927_pcicptr->iobas = 0xffffffff;
 352                 tx3927_pcicptr->ioba = 0;
 353                 tx3927_pcicptr->tlbioma = 0;
 354                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 355                 tx3927_pcicptr->mba = 0;
 356                 tx3927_pcicptr->tlbmma = 0;
 357                 /* Enable Direct mapping Address Space Decoder */
 358                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 359
 360                 /* Clear All Local Bus Status */
 361                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 362                 /* Enable All Local Bus Interrupts */
 363                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 364                 /* Clear All PCI Status Error */
 365                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 366                 /* Enable All PCI Status Error Interrupts */
 367                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 368
 369                 /* PCIC Int => IRC IRQ10 */
 370                 tx3927_pcicptr->il = TX3927_IR_PCI;
 371                 /* Target Control (per errata) */
 372                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 373
 374                 /* Enable Bus Arbiter */
 375                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 376
 377                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 378                         PCI_COMMAND_MEMORY |
 379                         PCI_COMMAND_IO |
 380                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 381         }
 382 #endif /* CONFIG_PCI */
 383
 384         /* PIO */
 385         /* PIO[15:12] connected to LEDs */
 386         tx3927_pioptr->dir = 0x0000f000;
 387         tx3927_pioptr->maskcpu = 0;
 388         tx3927_pioptr->maskext = 0;
 389         {
 390                 unsigned int conf;
 391
 392         conf = read_c0_conf();
 393                if (!(conf & TX39_CONF_ICE))
 394                        printk("TX3927 I-Cache disabled.\n");
 395                if (!(conf & TX39_CONF_DCE))
 396                        printk("TX3927 D-Cache disabled.\n");
 397                else if (!(conf & TX39_CONF_WBON))
 398                        printk("TX3927 D-Cache WriteThrough.\n");
 399                else if (!(conf & TX39_CONF_CWFON))
 400                        printk("TX3927 D-Cache WriteBack.\n");
 401                else
 402                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 403         }
 404 }
 405
 406 /* This trick makes rtc-ds1742 driver usable as is. */
 407 unsigned long __swizzle_addr_b(unsigned long port)
 408 {
 409         if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
 410                 return port;
 411         port = (port & 0xffff0000) | (port & 0x7fff << 1);
 412 #ifdef __BIG_ENDIAN
 413         return port;
 414 #else
 415         return port | 1;
 416 #endif
 417 }
 418 EXPORT_SYMBOL(__swizzle_addr_b);
 419
 420 static int __init jmr3927_rtc_init(void)
 421 {
 422         static struct resource __initdata res = {
 423                 .start  = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
 424                 .end    = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
 425                 .flags  = IORESOURCE_MEM,
 426         };
 427         struct platform_device *dev;
 428         dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 429         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 430 }
 431 device_initcall(jmr3927_rtc_init);