arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/sched.h>
  42 #include <linux/pci.h>
  43 #include <linux/ide.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47 #ifdef CONFIG_SERIAL_TXX9
  48 #include <linux/tty.h>
  49 #include <linux/serial.h>
  50 #include <linux/serial_core.h>
  51 #endif
  52
  53 #include <asm/addrspace.h>
  54 #include <asm/time.h>
  55 #include <asm/bcache.h>
  56 #include <asm/irq.h>
  57 #include <asm/reboot.h>
  58 #include <asm/gdb-stub.h>
  59 #include <asm/jmr3927/jmr3927.h>
  60 #include <asm/mipsregs.h>
  61 #include <asm/traps.h>
  62
  63 /* Tick Timer divider */
  64 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  65 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  66
  67 unsigned char led_state = 0xf;
  68
  69 struct {
  70     struct resource ram0;
  71     struct resource ram1;
  72     struct resource pcimem;
  73     struct resource iob;
  74     struct resource ioc;
  75     struct resource pciio;
  76     struct resource jmy1394;
  77     struct resource rom1;
  78     struct resource rom0;
  79     struct resource sio0;
  80     struct resource sio1;
  81 } jmr3927_resources = {
  82     { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
  83     { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
  84     { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
  85     { "IOB",           0x10000000, 0x13FFFFFF                  },
  86     { "IOC",           0x14000000, 0x14FFFFFF                  },
  87     { "PCIIO",         0x15000000, 0x15FFFFFF                  },
  88     { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
  89     { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
  90     { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
  91     { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
  92     { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
  93 };
  94
  95 /* don't enable - see errata */
  96 int jmr3927_ccfg_toeon = 0;
  97
  98 static inline void do_reset(void)
  99 {
 100 #ifdef CONFIG_TC35815
 101         extern void tc35815_killall(void);
 102         tc35815_killall();
 103 #endif
 104 #if 1   /* Resetting PCI bus */
 105         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 106         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 107         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 108         mdelay(1);
 109         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 110 #endif
 111         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 112 }
 113
 114 static void jmr3927_machine_restart(char *command)
 115 {
 116         local_irq_disable();
 117         puts("Rebooting...");
 118         do_reset();
 119 }
 120
 121 static void jmr3927_machine_halt(void)
 122 {
 123         puts("JMR-TX3927 halted.\n");
 124         while (1);
 125 }
 126
 127 static void jmr3927_machine_power_off(void)
 128 {
 129         puts("JMR-TX3927 halted. Please turn off the power.\n");
 130         while (1);
 131 }
 132
 133 #define USE_RTC_DS1742
 134 #ifdef USE_RTC_DS1742
 135 extern void rtc_ds1742_init(unsigned long base);
 136 #endif
 137 static void __init jmr3927_time_init(void)
 138 {
 139 #ifdef USE_RTC_DS1742
 140         if (jmr3927_have_nvram()) {
 141                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 142         }
 143 #endif
 144 }
 145
 146 unsigned long jmr3927_do_gettimeoffset(void);
 147 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 148
 149 static void __init jmr3927_timer_setup(struct irqaction *irq)
 150 {
 151         do_gettimeoffset = jmr3927_do_gettimeoffset;
 152
 153         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 154         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 155         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 156         jmr3927_tmrptr->tcr =
 157                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 158
 159         setup_irq(JMR3927_IRQ_TICK, irq);
 160 }
 161
 162 #define USECS_PER_JIFFY (1000000/HZ)
 163
 164 unsigned long jmr3927_do_gettimeoffset(void)
 165 {
 166        unsigned long count;
 167        unsigned long res = 0;
 168
 169        /* MUST read TRR before TISR. */
 170        count = jmr3927_tmrptr->trr;
 171
 172        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 173                /* timer interrupt is pending.  use Max value. */
 174                res = USECS_PER_JIFFY - 1;
 175        } else {
 176                /* convert to usec */
 177                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 178                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 179
 180                /*
 181                 * Due to possible jiffies inconsistencies, we need to check
 182                 * the result so that we'll get a timer that is monotonic.
 183                 */
 184                if (res >= USECS_PER_JIFFY)
 185                        res = USECS_PER_JIFFY-1;
 186        }
 187
 188        return res;
 189 }
 190
 191
 192 //#undef DO_WRITE_THROUGH
 193 #define DO_WRITE_THROUGH
 194 #define DO_ENABLE_CACHE
 195
 196 extern char * __init prom_getcmdline(void);
 197 static void jmr3927_board_init(void);
 198 extern struct resource pci_io_resource;
 199 extern struct resource pci_mem_resource;
 200
 201 void __init plat_setup(void)
 202 {
 203         char *argptr;
 204
 205         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 206
 207         board_time_init = jmr3927_time_init;
 208         board_timer_setup = jmr3927_timer_setup;
 209
 210         _machine_restart = jmr3927_machine_restart;
 211         _machine_halt = jmr3927_machine_halt;
 212         _machine_power_off = jmr3927_machine_power_off;
 213
 214         /*
 215          * IO/MEM resources.
 216          */
 217         ioport_resource.start = pci_io_resource.start;
 218         ioport_resource.end = pci_io_resource.end;
 219         iomem_resource.start = 0;
 220         iomem_resource.end = 0xffffffff;
 221
 222         /* Reboot on panic */
 223         panic_timeout = 180;
 224
 225         {
 226                 unsigned int conf;
 227                 conf = read_c0_conf();
 228         }
 229
 230 #if 1
 231         /* cache setup */
 232         {
 233                 unsigned int conf;
 234 #ifdef DO_ENABLE_CACHE
 235                 int mips_ic_disable = 0, mips_dc_disable = 0;
 236 #else
 237                 int mips_ic_disable = 1, mips_dc_disable = 1;
 238 #endif
 239 #ifdef DO_WRITE_THROUGH
 240                 int mips_config_cwfon = 0;
 241                 int mips_config_wbon = 0;
 242 #else
 243                 int mips_config_cwfon = 1;
 244                 int mips_config_wbon = 1;
 245 #endif
 246
 247                 conf = read_c0_conf();
 248                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 249                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 250                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 251                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 252                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 253
 254                 write_c0_conf(conf);
 255                 write_c0_cache(0);
 256         }
 257 #endif
 258
 259         /* initialize board */
 260         jmr3927_board_init();
 261
 262         argptr = prom_getcmdline();
 263
 264         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 265                         jmr3927_ccfg_toeon = 1;
 266         }
 267         argptr = prom_getcmdline();
 268         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 269                 argptr = prom_getcmdline();
 270                 strcat(argptr, " ip=bootp");
 271         }
 272
 273 #ifdef CONFIG_SERIAL_TXX9
 274         {
 275                 extern int early_serial_txx9_setup(struct uart_port *port);
 276                 int i;
 277                 struct uart_port req;
 278                 for(i = 0; i < 2; i++) {
 279                         memset(&req, 0, sizeof(req));
 280                         req.line = i;
 281                         req.iotype = UPIO_MEM;
 282                         req.membase = (char *)TX3927_SIO_REG(i);
 283                         req.mapbase = TX3927_SIO_REG(i);
 284                         req.irq = i == 0 ?
 285                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 286                         if (i == 0)
 287                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 288                         req.uartclk = JMR3927_IMCLK;
 289                         early_serial_txx9_setup(&req);
 290                 }
 291         }
 292 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 293         argptr = prom_getcmdline();
 294         if ((argptr = strstr(argptr, "console=")) == NULL) {
 295                 argptr = prom_getcmdline();
 296                 strcat(argptr, " console=ttyS1,115200");
 297         }
 298 #endif
 299 #endif
 300 }
 301
 302 static void tx3927_setup(void);
 303
 304 #ifdef CONFIG_PCI
 305 unsigned long mips_pci_io_base;
 306 unsigned long mips_pci_io_size;
 307 unsigned long mips_pci_mem_base;
 308 unsigned long mips_pci_mem_size;
 309 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 310 unsigned long mips_pci_io_pciaddr = 0;
 311 #endif
 312
 313 static void __init jmr3927_board_init(void)
 314 {
 315         char *argptr;
 316
 317 #ifdef CONFIG_PCI
 318         mips_pci_io_base = JMR3927_PCIIO;
 319         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 320         mips_pci_mem_base = JMR3927_PCIMEM;
 321         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 322 #endif
 323
 324         tx3927_setup();
 325
 326         if (jmr3927_have_isac()) {
 327
 328 #ifdef CONFIG_FB_E1355
 329                 argptr = prom_getcmdline();
 330                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 331                         argptr = prom_getcmdline();
 332                         strcat(argptr, " video=e1355fb:crt16h");
 333                 }
 334 #endif
 335
 336 #ifdef CONFIG_BLK_DEV_IDE
 337                 /* overrides PCI-IDE */
 338 #endif
 339         }
 340
 341         /* SIO0 DTR on */
 342         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 343
 344         jmr3927_led_set(0);
 345
 346
 347         if (jmr3927_have_isac())
 348                 jmr3927_io_led_set(0);
 349         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 350                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 351                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 352                jmr3927_dipsw1(), jmr3927_dipsw2(),
 353                jmr3927_dipsw3(), jmr3927_dipsw4());
 354         if (jmr3927_have_isac())
 355                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 356                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 357                        jmr3927_io_dipsw());
 358 }
 359
 360 void __init plat_setup(void)
 361 {
 362         int i;
 363
 364         /* SDRAMC are configured by PROM */
 365
 366         /* ROMC */
 367         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 368         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 369         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 370         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 371
 372         /* CCFG */
 373         /* enable Timeout BusError */
 374         if (jmr3927_ccfg_toeon)
 375                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 376
 377         /* clear BusErrorOnWrite flag */
 378         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 379         /* Disable PCI snoop */
 380         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 381
 382 #ifdef DO_WRITE_THROUGH
 383         /* Enable PCI SNOOP - with write through only */
 384         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 385 #endif
 386
 387         /* Pin selection */
 388         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 389         tx3927_ccfgptr->pcfg |=
 390                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 391                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 392
 393         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 394                tx3927_ccfgptr->crir,
 395                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 396
 397         /* IRC */
 398         /* disable interrupt control */
 399         tx3927_ircptr->cer = 0;
 400         /* mask all IRC interrupts */
 401         tx3927_ircptr->imr = 0;
 402         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 403                 tx3927_ircptr->ilr[i] = 0;
 404         }
 405         /* setup IRC interrupt mode (Low Active) */
 406         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 407                 tx3927_ircptr->cr[i] = 0;
 408         }
 409
 410         /* TMR */
 411         /* disable all timers */
 412         for (i = 0; i < TX3927_NR_TMR; i++) {
 413                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 414                 tx3927_tmrptr(i)->tisr = 0;
 415                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 416                 tx3927_tmrptr(i)->itmr = 0;
 417                 tx3927_tmrptr(i)->ccdr = 0;
 418                 tx3927_tmrptr(i)->pgmr = 0;
 419         }
 420
 421         /* DMA */
 422         tx3927_dmaptr->mcr = 0;
 423         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 424                 /* reset channel */
 425                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 426                 tx3927_dmaptr->ch[i].ccr = 0;
 427         }
 428         /* enable DMA */
 429 #ifdef __BIG_ENDIAN
 430         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 431 #else
 432         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 433 #endif
 434
 435 #ifdef CONFIG_PCI
 436         /* PCIC */
 437         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 438                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 439                tx3927_pcicptr->rid);
 440         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 441                 printk("External\n");
 442                 /* XXX */
 443         } else {
 444                 printk("Internal\n");
 445
 446                 /* Reset PCI Bus */
 447                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 448                 udelay(100);
 449                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 450                                     JMR3927_IOC_RESET_ADDR);
 451                 udelay(100);
 452                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 453
 454
 455                 /* Disable External PCI Config. Access */
 456                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 457 #ifdef __BIG_ENDIAN
 458                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 459                         TX3927_PCIC_LBC_TIBSE |
 460                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 461 #endif
 462                 /* LB->PCI mappings */
 463                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 464                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 465                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 466                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 467                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 468                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 469                 /* PCI->LB mappings */
 470                 tx3927_pcicptr->iobas = 0xffffffff;
 471                 tx3927_pcicptr->ioba = 0;
 472                 tx3927_pcicptr->tlbioma = 0;
 473                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 474                 tx3927_pcicptr->mba = 0;
 475                 tx3927_pcicptr->tlbmma = 0;
 476 #ifndef JMR3927_INIT_INDIRECT_PCI
 477                 /* Enable Direct mapping Address Space Decoder */
 478                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 479 #endif
 480
 481                 /* Clear All Local Bus Status */
 482                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 483                 /* Enable All Local Bus Interrupts */
 484                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 485                 /* Clear All PCI Status Error */
 486                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 487                 /* Enable All PCI Status Error Interrupts */
 488                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 489
 490                 /* PCIC Int => IRC IRQ10 */
 491                 tx3927_pcicptr->il = TX3927_IR_PCI;
 492 #if 1
 493                 /* Target Control (per errata) */
 494                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 495 #endif
 496
 497                 /* Enable Bus Arbiter */
 498 #if 0
 499                 tx3927_pcicptr->req_trace = 0x73737373;
 500 #endif
 501                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 502
 503                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 504                         PCI_COMMAND_MEMORY |
 505 #if 1
 506                         PCI_COMMAND_IO |
 507 #endif
 508                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 509         }
 510 #endif /* CONFIG_PCI */
 511
 512         /* PIO */
 513         /* PIO[15:12] connected to LEDs */
 514         tx3927_pioptr->dir = 0x0000f000;
 515         tx3927_pioptr->maskcpu = 0;
 516         tx3927_pioptr->maskext = 0;
 517         {
 518                 unsigned int conf;
 519
 520         conf = read_c0_conf();
 521                if (!(conf & TX39_CONF_ICE))
 522                        printk("TX3927 I-Cache disabled.\n");
 523                if (!(conf & TX39_CONF_DCE))
 524                        printk("TX3927 D-Cache disabled.\n");
 525                else if (!(conf & TX39_CONF_WBON))
 526                        printk("TX3927 D-Cache WriteThrough.\n");
 527                else if (!(conf & TX39_CONF_CWFON))
 528                        printk("TX3927 D-Cache WriteBack.\n");
 529                else
 530                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 531         }
 532 }