2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/signal.h>
12 #include <linux/module.h>
13 #include <asm/branch.h>
15 #include <asm/cpu-features.h>
17 #include <asm/fpu_emulator.h>
19 #include <asm/mips-r2-to-r6-emul.h>
20 #include <asm/ptrace.h>
21 #include <asm/uaccess.h>
24 * Calculate and return exception PC in case of branch delay slot
25 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
27 int __isa_exception_epc(struct pt_regs
*regs
)
30 long epc
= regs
->cp0_epc
;
32 /* Calculate exception PC in branch delay slot. */
33 if (__get_user(inst
, (u16 __user
*) msk_isa16_mode(epc
))) {
34 /* This should never happen because delay slot was checked. */
35 force_sig(SIGSEGV
, current
);
39 if (((union mips16e_instruction
)inst
).ri
.opcode
44 } else if (mm_insn_16bit(inst
))
52 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
53 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
55 int __mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
56 unsigned long *contpc
)
58 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
66 switch (insn
.mm_i_format
.opcode
) {
68 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
70 switch (insn
.mm_i_format
.simmediate
>>
71 MM_POOL32A_MINOR_SHIFT
) {
76 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
77 regs
->regs
[insn
.mm_i_format
.rt
] =
81 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
87 switch (insn
.mm_i_format
.rt
) {
90 regs
->regs
[31] = regs
->cp0_epc
+
95 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
96 *contpc
= regs
->cp0_epc
+
98 (insn
.mm_i_format
.simmediate
<< 1);
100 *contpc
= regs
->cp0_epc
+
102 dec_insn
.next_pc_inc
;
106 regs
->regs
[31] = regs
->cp0_epc
+
108 dec_insn
.next_pc_inc
;
111 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
112 *contpc
= regs
->cp0_epc
+
114 (insn
.mm_i_format
.simmediate
<< 1);
116 *contpc
= regs
->cp0_epc
+
118 dec_insn
.next_pc_inc
;
121 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
122 *contpc
= regs
->cp0_epc
+
124 (insn
.mm_i_format
.simmediate
<< 1);
126 *contpc
= regs
->cp0_epc
+
128 dec_insn
.next_pc_inc
;
131 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
132 *contpc
= regs
->cp0_epc
+
134 (insn
.mm_i_format
.simmediate
<< 1);
136 *contpc
= regs
->cp0_epc
+
138 dec_insn
.next_pc_inc
;
148 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
150 fcr31
= current
->thread
.fpu
.fcr31
;
156 bit
= (insn
.mm_i_format
.rs
>> 2);
159 if (fcr31
& (1 << bit
))
160 *contpc
= regs
->cp0_epc
+
162 (insn
.mm_i_format
.simmediate
<< 1);
164 *contpc
= regs
->cp0_epc
+
165 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
170 switch (insn
.mm_i_format
.rt
) {
173 regs
->regs
[31] = regs
->cp0_epc
+
174 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
177 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
182 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
183 *contpc
= regs
->cp0_epc
+
185 (insn
.mm_b1_format
.simmediate
<< 1);
187 *contpc
= regs
->cp0_epc
+
188 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
191 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
192 *contpc
= regs
->cp0_epc
+
194 (insn
.mm_b1_format
.simmediate
<< 1);
196 *contpc
= regs
->cp0_epc
+
197 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
200 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
201 (insn
.mm_b0_format
.simmediate
<< 1);
204 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
205 regs
->regs
[insn
.mm_i_format
.rt
])
206 *contpc
= regs
->cp0_epc
+
208 (insn
.mm_i_format
.simmediate
<< 1);
210 *contpc
= regs
->cp0_epc
+
212 dec_insn
.next_pc_inc
;
215 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
216 regs
->regs
[insn
.mm_i_format
.rt
])
217 *contpc
= regs
->cp0_epc
+
219 (insn
.mm_i_format
.simmediate
<< 1);
221 *contpc
= regs
->cp0_epc
+
222 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
225 regs
->regs
[31] = regs
->cp0_epc
+
226 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
227 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
230 *contpc
|= (insn
.j_format
.target
<< 2);
234 regs
->regs
[31] = regs
->cp0_epc
+
235 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
238 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
241 *contpc
|= (insn
.j_format
.target
<< 1);
242 set_isa16_mode(*contpc
);
249 * Compute return address and emulate branch in microMIPS mode after an
250 * exception only. It does not handle compact branches/jumps and cannot
251 * be used in interrupt context. (Compact branches/jumps do not cause
254 int __microMIPS_compute_return_epc(struct pt_regs
*regs
)
259 unsigned long contpc
;
260 struct mm_decoded_insn mminsn
= { 0 };
262 mminsn
.micro_mips_mode
= 1;
264 /* This load never faults. */
265 pc16
= (unsigned short __user
*)msk_isa16_mode(regs
->cp0_epc
);
266 __get_user(halfword
, pc16
);
268 contpc
= regs
->cp0_epc
+ 2;
269 word
= ((unsigned int)halfword
<< 16);
272 if (!mm_insn_16bit(halfword
)) {
273 __get_user(halfword
, pc16
);
275 contpc
= regs
->cp0_epc
+ 4;
281 if (get_user(halfword
, pc16
))
283 mminsn
.next_pc_inc
= 2;
284 word
= ((unsigned int)halfword
<< 16);
286 if (!mm_insn_16bit(halfword
)) {
288 if (get_user(halfword
, pc16
))
290 mminsn
.next_pc_inc
= 4;
293 mminsn
.next_insn
= word
;
295 mm_isBranchInstr(regs
, mminsn
, &contpc
);
297 regs
->cp0_epc
= contpc
;
302 force_sig(SIGSEGV
, current
);
307 * Compute return address and emulate branch in MIPS16e mode after an
308 * exception only. It does not handle compact branches/jumps and cannot
309 * be used in interrupt context. (Compact branches/jumps do not cause
312 int __MIPS16e_compute_return_epc(struct pt_regs
*regs
)
315 union mips16e_instruction inst
;
322 /* Read the instruction. */
323 addr
= (u16 __user
*)msk_isa16_mode(epc
);
324 if (__get_user(inst
.full
, addr
)) {
325 force_sig(SIGSEGV
, current
);
329 switch (inst
.ri
.opcode
) {
330 case MIPS16e_extend_op
:
335 * JAL and JALX in MIPS16e mode
339 if (__get_user(inst2
, addr
)) {
340 force_sig(SIGSEGV
, current
);
343 fullinst
= ((unsigned)inst
.full
<< 16) | inst2
;
344 regs
->regs
[31] = epc
+ 6;
349 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
351 * ......TARGET[15:0].................TARGET[20:16]...........
352 * ......TARGET[25:21]
355 ((fullinst
& 0xffff) << 2) | ((fullinst
& 0x3e00000) >> 3) |
356 ((fullinst
& 0x1f0000) << 7);
358 set_isa16_mode(epc
); /* Set ISA mode bit. */
366 if (inst
.rr
.func
== MIPS16e_jr_func
) {
369 regs
->cp0_epc
= regs
->regs
[31];
372 regs
->regs
[reg16to32
[inst
.rr
.rx
]];
376 regs
->regs
[31] = epc
+ 2;
378 regs
->regs
[31] = epc
+ 4;
386 * All other cases have no branch delay slot and are 16-bits.
387 * Branches do not cause an exception.
395 * __compute_return_epc_for_insn - Computes the return address and do emulate
396 * branch simulation, if required.
398 * @regs: Pointer to pt_regs
399 * @insn: branch instruction to decode
400 * @returns: -EFAULT on error and forces SIGBUS, and on success
401 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
402 * evaluating the branch.
404 * MIPS R6 Compact branches and forbidden slots:
405 * Compact branches do not throw exceptions because they do
406 * not have delay slots. The forbidden slot instruction ($PC+4)
407 * is only executed if the branch was not taken. Otherwise the
408 * forbidden slot is skipped entirely. This means that the
409 * only possible reason to be here because of a MIPS R6 compact
410 * branch instruction is that the forbidden slot has thrown one.
411 * In that case the branch was not taken, so the EPC can be safely
414 int __compute_return_epc_for_insn(struct pt_regs
*regs
,
415 union mips_instruction insn
)
417 unsigned int bit
, fcr31
, dspcontrol
, reg
;
418 long epc
= regs
->cp0_epc
;
421 switch (insn
.i_format
.opcode
) {
423 * jr and jalr are in r_format format.
426 switch (insn
.r_format
.func
) {
428 regs
->regs
[insn
.r_format
.rd
] = epc
+ 8;
431 if (NO_R6EMU
&& insn
.r_format
.func
== jr_op
)
433 regs
->cp0_epc
= regs
->regs
[insn
.r_format
.rs
];
439 * This group contains:
440 * bltz_op, bgez_op, bltzl_op, bgezl_op,
441 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
444 switch (insn
.i_format
.rt
) {
449 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0) {
450 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
451 if (insn
.i_format
.rt
== bltzl_op
)
452 ret
= BRANCH_LIKELY_TAKEN
;
462 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0) {
463 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
464 if (insn
.i_format
.rt
== bgezl_op
)
465 ret
= BRANCH_LIKELY_TAKEN
;
473 if (NO_R6EMU
&& (insn
.i_format
.rs
||
474 insn
.i_format
.rt
== bltzall_op
)) {
478 regs
->regs
[31] = epc
+ 8;
480 * OK we are here either because we hit a NAL
481 * instruction or because we are emulating an
482 * old bltzal{,l} one. Lets figure out what the
485 if (!insn
.i_format
.rs
) {
487 * NAL or BLTZAL with rs == 0
488 * Doesn't matter if we are R6 or not. The
492 (insn
.i_format
.simmediate
<< 2);
495 /* Now do the real thing for non-R6 BLTZAL{,L} */
496 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0) {
497 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
498 if (insn
.i_format
.rt
== bltzall_op
)
499 ret
= BRANCH_LIKELY_TAKEN
;
507 if (NO_R6EMU
&& (insn
.i_format
.rs
||
508 insn
.i_format
.rt
== bgezall_op
)) {
512 regs
->regs
[31] = epc
+ 8;
514 * OK we are here either because we hit a BAL
515 * instruction or because we are emulating an
516 * old bgezal{,l} one. Lets figure out what the
519 if (!insn
.i_format
.rs
) {
521 * BAL or BGEZAL with rs == 0
522 * Doesn't matter if we are R6 or not. The
526 (insn
.i_format
.simmediate
<< 2);
529 /* Now do the real thing for non-R6 BGEZAL{,L} */
530 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0) {
531 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
532 if (insn
.i_format
.rt
== bgezall_op
)
533 ret
= BRANCH_LIKELY_TAKEN
;
543 dspcontrol
= rddsp(0x01);
545 if (dspcontrol
>= 32) {
546 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
555 * These are unconditional and in j_format.
558 regs
->regs
[31] = regs
->cp0_epc
+ 8;
563 epc
|= (insn
.j_format
.target
<< 2);
565 if (insn
.i_format
.opcode
== jalx_op
)
566 set_isa16_mode(regs
->cp0_epc
);
570 * These are conditional and in i_format.
576 if (regs
->regs
[insn
.i_format
.rs
] ==
577 regs
->regs
[insn
.i_format
.rt
]) {
578 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
579 if (insn
.i_format
.opcode
== beql_op
)
580 ret
= BRANCH_LIKELY_TAKEN
;
590 if (regs
->regs
[insn
.i_format
.rs
] !=
591 regs
->regs
[insn
.i_format
.rt
]) {
592 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
593 if (insn
.i_format
.opcode
== bnel_op
)
594 ret
= BRANCH_LIKELY_TAKEN
;
600 case blezl_op
: /* not really i_format */
605 * Compact branches for R6 for the
606 * blez and blezl opcodes.
607 * BLEZ | rs = 0 | rt != 0 == BLEZALC
608 * BLEZ | rs = rt != 0 == BGEZALC
609 * BLEZ | rs != 0 | rt != 0 == BGEUC
610 * BLEZL | rs = 0 | rt != 0 == BLEZC
611 * BLEZL | rs = rt != 0 == BGEZC
612 * BLEZL | rs != 0 | rt != 0 == BGEC
614 * For real BLEZ{,L}, rt is always 0.
617 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
618 if ((insn
.i_format
.opcode
== blez_op
) &&
619 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
620 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
621 regs
->regs
[31] = epc
+ 4;
625 /* rt field assumed to be zero */
626 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0) {
627 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
628 if (insn
.i_format
.opcode
== blezl_op
)
629 ret
= BRANCH_LIKELY_TAKEN
;
640 * Compact branches for R6 for the
641 * bgtz and bgtzl opcodes.
642 * BGTZ | rs = 0 | rt != 0 == BGTZALC
643 * BGTZ | rs = rt != 0 == BLTZALC
644 * BGTZ | rs != 0 | rt != 0 == BLTUC
645 * BGTZL | rs = 0 | rt != 0 == BGTZC
646 * BGTZL | rs = rt != 0 == BLTZC
647 * BGTZL | rs != 0 | rt != 0 == BLTC
649 * *ZALC varint for BGTZ &&& rt != 0
650 * For real GTZ{,L}, rt is always 0.
652 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
653 if ((insn
.i_format
.opcode
== blez_op
) &&
654 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
655 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
656 regs
->regs
[31] = epc
+ 4;
661 /* rt field assumed to be zero */
662 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0) {
663 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
664 if (insn
.i_format
.opcode
== bgtzl_op
)
665 ret
= BRANCH_LIKELY_TAKEN
;
672 * And now the FPA/cp1 branch instructions.
675 if (cpu_has_mips_r6
&&
676 ((insn
.i_format
.rs
== bc1eqz_op
) ||
677 (insn
.i_format
.rs
== bc1nez_op
))) {
678 if (!used_math()) { /* First time FPU user */
680 if (ret
&& NO_R6EMU
) {
687 lose_fpu(1); /* Save FPU state for the emulator. */
688 reg
= insn
.i_format
.rt
;
690 switch (insn
.i_format
.rs
) {
693 if (get_fpr32(¤t
->thread
.fpu
.fpr
[reg
], 0)
699 if (!(get_fpr32(¤t
->thread
.fpu
.fpr
[reg
], 0)
707 (insn
.i_format
.simmediate
<< 2);
717 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
719 fcr31
= current
->thread
.fpu
.fcr31
;
722 bit
= (insn
.i_format
.rt
>> 2);
725 switch (insn
.i_format
.rt
& 3) {
728 if (~fcr31
& (1 << bit
)) {
730 (insn
.i_format
.simmediate
<< 2);
731 if (insn
.i_format
.rt
== 2)
732 ret
= BRANCH_LIKELY_TAKEN
;
740 if (fcr31
& (1 << bit
)) {
742 (insn
.i_format
.simmediate
<< 2);
743 if (insn
.i_format
.rt
== 3)
744 ret
= BRANCH_LIKELY_TAKEN
;
752 #ifdef CONFIG_CPU_CAVIUM_OCTEON
753 case lwc2_op
: /* This is bbit0 on Octeon */
754 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
756 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
761 case ldc2_op
: /* This is bbit032 on Octeon */
762 if ((regs
->regs
[insn
.i_format
.rs
] &
763 (1ull<<(insn
.i_format
.rt
+32))) == 0)
764 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
769 case swc2_op
: /* This is bbit1 on Octeon */
770 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
771 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
776 case sdc2_op
: /* This is bbit132 on Octeon */
777 if (regs
->regs
[insn
.i_format
.rs
] &
778 (1ull<<(insn
.i_format
.rt
+32)))
779 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
786 /* Only valid for MIPS R6 */
787 if (!cpu_has_mips_r6
) {
794 if (!cpu_has_mips_r6
) {
798 /* Compact branch: BALC */
799 regs
->regs
[31] = epc
+ 4;
800 epc
+= 4 + (insn
.i_format
.simmediate
<< 2);
804 if (!cpu_has_mips_r6
) {
808 /* Compact branch: BEQZC || JIC */
812 if (!cpu_has_mips_r6
) {
816 /* Compact branch: BNEZC || JIALC */
817 if (insn
.i_format
.rs
)
818 regs
->regs
[31] = epc
+ 4;
824 /* Only valid for MIPS R6 */
825 if (!cpu_has_mips_r6
) {
831 * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
833 if (insn
.i_format
.rt
&& !insn
.i_format
.rs
)
834 regs
->regs
[31] = epc
+ 4;
842 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current
->comm
);
843 force_sig(SIGBUS
, current
);
846 pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
848 force_sig(SIGILL
, current
);
851 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn
);
853 int __compute_return_epc(struct pt_regs
*regs
)
855 unsigned int __user
*addr
;
857 union mips_instruction insn
;
864 * Read the instruction
866 addr
= (unsigned int __user
*) epc
;
867 if (__get_user(insn
.word
, addr
)) {
868 force_sig(SIGSEGV
, current
);
872 return __compute_return_epc_for_insn(regs
, insn
);
875 printk("%s: unaligned epc - sending SIGBUS.\n", current
->comm
);
876 force_sig(SIGBUS
, current
);